Commit 451436b7 authored by Russell King's avatar Russell King

[ARM] Add support code for ARM hardware vector floating point

This cset adds the code to handle the hardware vector floating point
unit found on some ARM926 and later CPUs.  The hardware provides
an implementation for the common cases, and bounces exceptions for
other cases, which have to be handled in software, and signalling
SIGFPE as appropriate.
parent cda97ee3
Release notes for Linux Kernel VFP support code
-----------------------------------------------
Date: 20 May 2004
Author: Russell King
This is the first release of the Linux Kernel VFP support code. It
provides support for the exceptions bounced from VFP hardware found
on ARM926EJ-S.
This release has been validated against the SoftFloat-2b library by
John R. Hauser using the TestFloat-2a test suite. Details of this
library and test suite can be found at:
http://www.cs.berkeley.edu/~jhauser/arithmetic/SoftFloat.html
The operations which have been tested with this package are:
- fdiv
- fsub
- fadd
- fmul
- fcmp
- fcmpe
- fcvtd
- fcvts
- fsito
- ftosi
- fsqrt
All the above pass softfloat tests with the following exceptions:
- fadd/fsub shows some differences in the handling of +0 / -0 results
when input operands differ in signs.
- the handling of underflow exceptions is slightly different. If a
result underflows before rounding, but becomes a normalised number
after rounding, we do not signal an underflow exception.
Other operations which have been tested by basic assembly-only tests
are:
- fcpy
- fabs
- fneg
- ftoui
- ftosiz
- ftouiz
The combination operations have not been tested:
- fmac
- fnmac
- fmsc
- fnmsc
- fnmul
......@@ -421,6 +421,17 @@ config FPE_FASTFPE
If you do not feel you need a faster FP emulation you should better
choose NWFPE.
config VFP
bool "VFP-format floating point maths"
help
Say Y to include VFP support code in the kernel. This is needed
if your hardware includes a VFP unit.
Please see <file:Documentation/arm/VFP/release-notes.txt> for
release notes and additional status information.
Say N if your target does not have VFP hardware.
source "fs/Kconfig.binfmt"
source "drivers/base/Kconfig"
......
......@@ -119,6 +119,7 @@ core-y += arch/arm/mach-$(machine-y)/
endif
core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
core-$(CONFIG_VFP) += arch/arm/vfp/
drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
......
......@@ -19,6 +19,7 @@
#include <asm/thread_info.h>
#include <asm/glue.h>
#include <asm/ptrace.h>
#include <asm/vfpmacros.h>
#include "entry-header.S"
......@@ -1198,8 +1199,13 @@ call_fpe: enable_irq r10 @ Enable interrupts
mov pc, lr @ CP#7
mov pc, lr @ CP#8
mov pc, lr @ CP#9
#ifdef CONFIG_VFP
b do_vfp @ CP#10 (VFP)
b do_vfp @ CP#11 (VFP)
#else
mov pc, lr @ CP#10 (VFP)
mov pc, lr @ CP#11 (VFP)
#endif
mov pc, lr @ CP#12
mov pc, lr @ CP#13
mov pc, lr @ CP#14 (Debug)
......@@ -1260,6 +1266,13 @@ ENTRY(__switch_to)
ldr r3, [r2, #TI_CPU_DOMAIN]!
stmia ip, {r4 - sl, fp, sp, lr} @ Store most regs on stack
mcr p15, 0, r3, c3, c0, 0 @ Set domain register
#ifdef CONFIG_VFP
@ Always disable VFP so we can lazily save/restore the old
@ state. This occurs in the context of the previous thread.
VFPFMRX r4, FPEXC
bic r4, r4, #FPEXC_ENABLE
VFPFMXR FPEXC, r4
#endif
ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
__INIT
......
......@@ -314,10 +314,16 @@ void flush_thread(void)
memset(thread->used_cp, 0, sizeof(thread->used_cp));
memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
fp_init(&thread->fpstate);
#if defined(CONFIG_VFP)
vfp_flush_thread(&thread->vfpstate);
#endif
}
void release_thread(struct task_struct *dead_task)
{
#if defined(CONFIG_VFP)
vfp_release_thread(&dead_task->thread_info->vfpstate);
#endif
}
asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
......
#
# linux/arch/arm/vfp/Makefile
#
# Copyright (C) 2001 ARM Limited
#
# EXTRA_CFLAGS := -DDEBUG
# EXTRA_AFLAGS := -DDEBUG
obj-y += vfp.o
vfp-$(CONFIG_VFP) += entry.o vfpmodule.o vfphw.o vfpsingle.o vfpdouble.o
/*
* linux/arch/arm/vfp/entry.S
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Basic entry code, called from the kernel's undefined instruction trap.
* r0 = faulted instruction
* r5 = faulted PC+4
* r9 = successful return
* r10 = thread_info structure
* lr = failure return
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
.globl do_vfp
do_vfp:
ldr r4, .LCvfp
add r10, r10, #TI_VFPSTATE @ r10 = workspace
ldr pc, [r4] @ call VFP entry point
.LCvfp:
.word vfp_vector
@ This code is called if the VFP does not exist. It needs to flag the
@ failure to the VFP initialisation code.
__INIT
.globl vfp_testing_entry
vfp_testing_entry:
ldr r0, VFP_arch_address
str r5, [r0] @ known non-zero value
mov pc, r9 @ we have handled the fault
VFP_arch_address:
.word VFP_arch
__FINIT
/*
* linux/arch/arm/vfp/vfp.h
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
static inline u32 vfp_shiftright32jamming(u32 val, unsigned int shift)
{
if (shift) {
if (shift < 32)
val = val >> shift | ((val << (32 - shift)) != 0);
else
val = val != 0;
}
return val;
}
static inline u64 vfp_shiftright64jamming(u64 val, unsigned int shift)
{
if (shift) {
if (shift < 64)
val = val >> shift | ((val << (64 - shift)) != 0);
else
val = val != 0;
}
return val;
}
static inline u32 vfp_hi64to32jamming(u64 val)
{
u32 v;
asm(
"cmp %Q1, #1 @ vfp_hi64to32jamming\n\t"
"movcc %0, %R1\n\t"
"orrcs %0, %R1, #1"
: "=r" (v) : "r" (val) : "cc");
return v;
}
static inline void add128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
{
asm( "adds %Q0, %Q2, %Q4\n\t"
"adcs %R0, %R2, %R4\n\t"
"adcs %Q1, %Q3, %Q5\n\t"
"adc %R1, %R3, %R5"
: "=r" (nl), "=r" (nh)
: "0" (nl), "1" (nh), "r" (ml), "r" (mh)
: "cc");
*resh = nh;
*resl = nl;
}
static inline void sub128(u64 *resh, u64 *resl, u64 nh, u64 nl, u64 mh, u64 ml)
{
asm( "subs %Q0, %Q2, %Q4\n\t"
"sbcs %R0, %R2, %R4\n\t"
"sbcs %Q1, %Q3, %Q5\n\t"
"sbc %R1, %R3, %R5\n\t"
: "=r" (nl), "=r" (nh)
: "0" (nl), "1" (nh), "r" (ml), "r" (mh)
: "cc");
*resh = nh;
*resl = nl;
}
static inline void mul64to128(u64 *resh, u64 *resl, u64 n, u64 m)
{
u32 nh, nl, mh, ml;
u64 rh, rma, rmb, rl;
nl = n;
ml = m;
rl = (u64)nl * ml;
nh = n >> 32;
rma = (u64)nh * ml;
mh = m >> 32;
rmb = (u64)nl * mh;
rma += rmb;
rh = (u64)nh * mh;
rh += ((u64)(rma < rmb) << 32) + (rma >> 32);
rma <<= 32;
rl += rma;
rh += (rl < rma);
*resl = rl;
*resh = rh;
}
static inline void shift64left(u64 *resh, u64 *resl, u64 n)
{
*resh = n >> 63;
*resl = n << 1;
}
static inline u64 vfp_hi64multiply64(u64 n, u64 m)
{
u64 rh, rl;
mul64to128(&rh, &rl, n, m);
return rh | (rl != 0);
}
static inline u64 vfp_estimate_div128to64(u64 nh, u64 nl, u64 m)
{
u64 mh, ml, remh, reml, termh, terml, z;
if (nh >= m)
return ~0ULL;
mh = m >> 32;
z = (mh << 32 <= nh) ? 0xffffffff00000000ULL : (nh / mh) << 32;
mul64to128(&termh, &terml, m, z);
sub128(&remh, &reml, nh, nl, termh, terml);
ml = m << 32;
while ((s64)remh < 0) {
z -= 0x100000000ULL;
add128(&remh, &reml, remh, reml, mh, ml);
}
remh = (remh << 32) | (reml >> 32);
z |= (mh << 32 <= remh) ? 0xffffffff : remh / mh;
return z;
}
/*
* Operations on unpacked elements
*/
#define vfp_sign_negate(sign) (sign ^ 0x8000)
/*
* Single-precision
*/
struct vfp_single {
s16 exponent;
u16 sign;
u32 significand;
};
extern s32 vfp_get_float(unsigned int reg);
extern void vfp_put_float(unsigned int reg, s32 val);
/*
* VFP_SINGLE_MANTISSA_BITS - number of bits in the mantissa
* VFP_SINGLE_EXPONENT_BITS - number of bits in the exponent
* VFP_SINGLE_LOW_BITS - number of low bits in the unpacked significand
* which are not propagated to the float upon packing.
*/
#define VFP_SINGLE_MANTISSA_BITS (23)
#define VFP_SINGLE_EXPONENT_BITS (8)
#define VFP_SINGLE_LOW_BITS (32 - VFP_SINGLE_MANTISSA_BITS - 2)
#define VFP_SINGLE_LOW_BITS_MASK ((1 << VFP_SINGLE_LOW_BITS) - 1)
/*
* The bit in an unpacked float which indicates that it is a quiet NaN
*/
#define VFP_SINGLE_SIGNIFICAND_QNAN (1 << (VFP_SINGLE_MANTISSA_BITS - 1 + VFP_SINGLE_LOW_BITS))
/*
* Operations on packed single-precision numbers
*/
#define vfp_single_packed_sign(v) ((v) & 0x80000000)
#define vfp_single_packed_negate(v) ((v) ^ 0x80000000)
#define vfp_single_packed_abs(v) ((v) & ~0x80000000)
#define vfp_single_packed_exponent(v) (((v) >> VFP_SINGLE_MANTISSA_BITS) & ((1 << VFP_SINGLE_EXPONENT_BITS) - 1))
#define vfp_single_packed_mantissa(v) ((v) & ((1 << VFP_SINGLE_MANTISSA_BITS) - 1))
/*
* Unpack a single-precision float. Note that this returns the magnitude
* of the single-precision float mantissa with the 1. if necessary,
* aligned to bit 30.
*/
static inline void vfp_single_unpack(struct vfp_single *s, s32 val)
{
u32 significand;
s->sign = vfp_single_packed_sign(val) >> 16,
s->exponent = vfp_single_packed_exponent(val);
significand = (u32) val;
significand = (significand << (32 - VFP_SINGLE_MANTISSA_BITS)) >> 2;
if (s->exponent && s->exponent != 255)
significand |= 0x40000000;
s->significand = significand;
}
/*
* Re-pack a single-precision float. This assumes that the float is
* already normalised such that the MSB is bit 30, _not_ bit 31.
*/
static inline s32 vfp_single_pack(struct vfp_single *s)
{
u32 val;
val = (s->sign << 16) +
(s->exponent << VFP_SINGLE_MANTISSA_BITS) +
(s->significand >> VFP_SINGLE_LOW_BITS);
return (s32)val;
}
#define VFP_NUMBER (1<<0)
#define VFP_ZERO (1<<1)
#define VFP_DENORMAL (1<<2)
#define VFP_INFINITY (1<<3)
#define VFP_NAN (1<<4)
#define VFP_NAN_SIGNAL (1<<5)
#define VFP_QNAN (VFP_NAN)
#define VFP_SNAN (VFP_NAN|VFP_NAN_SIGNAL)
static inline int vfp_single_type(struct vfp_single *s)
{
int type = VFP_NUMBER;
if (s->exponent == 255) {
if (s->significand == 0)
type = VFP_INFINITY;
else if (s->significand & VFP_SINGLE_SIGNIFICAND_QNAN)
type = VFP_QNAN;
else
type = VFP_SNAN;
} else if (s->exponent == 0) {
if (s->significand == 0)
type |= VFP_ZERO;
else
type |= VFP_DENORMAL;
}
return type;
}
#ifndef DEBUG
#define vfp_single_normaliseround(sd,vsd,fpscr,except,func) __vfp_single_normaliseround(sd,vsd,fpscr,except)
u32 __vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions);
#else
u32 vfp_single_normaliseround(int sd, struct vfp_single *vs, u32 fpscr, u32 exceptions, const char *func);
#endif
/*
* Double-precision
*/
struct vfp_double {
s16 exponent;
u16 sign;
u64 significand;
};
extern u64 vfp_get_double(unsigned int reg);
extern void vfp_put_double(unsigned int reg, u64 val);
#define VFP_DOUBLE_MANTISSA_BITS (52)
#define VFP_DOUBLE_EXPONENT_BITS (11)
#define VFP_DOUBLE_LOW_BITS (64 - VFP_DOUBLE_MANTISSA_BITS - 2)
#define VFP_DOUBLE_LOW_BITS_MASK ((1 << VFP_DOUBLE_LOW_BITS) - 1)
/*
* The bit in an unpacked double which indicates that it is a quiet NaN
*/
#define VFP_DOUBLE_SIGNIFICAND_QNAN (1ULL << (VFP_DOUBLE_MANTISSA_BITS - 1 + VFP_DOUBLE_LOW_BITS))
/*
* Operations on packed single-precision numbers
*/
#define vfp_double_packed_sign(v) ((v) & (1ULL << 63))
#define vfp_double_packed_negate(v) ((v) ^ (1ULL << 63))
#define vfp_double_packed_abs(v) ((v) & ~(1ULL << 63))
#define vfp_double_packed_exponent(v) (((v) >> VFP_DOUBLE_MANTISSA_BITS) & ((1 << VFP_DOUBLE_EXPONENT_BITS) - 1))
#define vfp_double_packed_mantissa(v) ((v) & ((1ULL << VFP_DOUBLE_MANTISSA_BITS) - 1))
/*
* Unpack a double-precision float. Note that this returns the magnitude
* of the double-precision float mantissa with the 1. if necessary,
* aligned to bit 62.
*/
static inline void vfp_double_unpack(struct vfp_double *s, s64 val)
{
u64 significand;
s->sign = vfp_double_packed_sign(val) >> 48;
s->exponent = vfp_double_packed_exponent(val);
significand = (u64) val;
significand = (significand << (64 - VFP_DOUBLE_MANTISSA_BITS)) >> 2;
if (s->exponent && s->exponent != 2047)
significand |= (1ULL << 62);
s->significand = significand;
}
/*
* Re-pack a double-precision float. This assumes that the float is
* already normalised such that the MSB is bit 30, _not_ bit 31.
*/
static inline s64 vfp_double_pack(struct vfp_double *s)
{
u64 val;
val = ((u64)s->sign << 48) +
((u64)s->exponent << VFP_DOUBLE_MANTISSA_BITS) +
(s->significand >> VFP_DOUBLE_LOW_BITS);
return (s64)val;
}
static inline int vfp_double_type(struct vfp_double *s)
{
int type = VFP_NUMBER;
if (s->exponent == 2047) {
if (s->significand == 0)
type = VFP_INFINITY;
else if (s->significand & VFP_DOUBLE_SIGNIFICAND_QNAN)
type = VFP_QNAN;
else
type = VFP_SNAN;
} else if (s->exponent == 0) {
if (s->significand == 0)
type |= VFP_ZERO;
else
type |= VFP_DENORMAL;
}
return type;
}
u32 vfp_double_normaliseround(int dd, struct vfp_double *vd, u32 fpscr, u32 exceptions, const char *func);
/*
* System registers
*/
extern u32 vfp_get_sys(unsigned int reg);
extern void vfp_put_sys(unsigned int reg, u32 val);
u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
This diff is collapsed.
/*
* linux/arch/arm/vfp/vfphw.S
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This code is called from the kernel's undefined instruction trap.
* r9 holds the return address for successful handling.
* lr holds the return address for unrecognised instructions.
* r10 points at the start of the private FP workspace in the thread structure
* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
*/
#include <asm/thread_info.h>
#include <asm/vfpmacros.h>
#include "../kernel/entry-header.S"
.macro DBGSTR, str
#ifdef DEBUG
stmfd sp!, {r0-r3, ip, lr}
add r0, pc, #4
bl printk
b 1f
.asciz "<7>VFP: \str\n"
.balign 4
1: ldmfd sp!, {r0-r3, ip, lr}
#endif
.endm
.macro DBGSTR1, str, arg
#ifdef DEBUG
stmfd sp!, {r0-r3, ip, lr}
mov r1, \arg
add r0, pc, #4
bl printk
b 1f
.asciz "<7>VFP: \str\n"
.balign 4
1: ldmfd sp!, {r0-r3, ip, lr}
#endif
.endm
.macro DBGSTR3, str, arg1, arg2, arg3
#ifdef DEBUG
stmfd sp!, {r0-r3, ip, lr}
mov r3, \arg3
mov r2, \arg2
mov r1, \arg1
add r0, pc, #4
bl printk
b 1f
.asciz "<7>VFP: \str\n"
.balign 4
1: ldmfd sp!, {r0-r3, ip, lr}
#endif
.endm
@ VFP hardware support entry point.
@
@ r0 = faulted instruction
@ r5 = faulted PC+4
@ r9 = successful return
@ r10 = vfp_state union
@ lr = failure return
.globl vfp_support_entry
vfp_support_entry:
DBGSTR3 "instr %08x pc %08x state %p", r0, r5, r10
VFPFMRX r1, FPEXC @ Is the VFP enabled?
DBGSTR1 "fpexc %08x", r1
tst r1, #FPEXC_ENABLE
bne look_for_VFP_exceptions @ VFP is already enabled
DBGSTR1 "enable %x", r10
ldr r3, last_VFP_context_address
orr r1, r1, #FPEXC_ENABLE @ user FPEXC has the enable bit set
ldr r4, [r3] @ last_VFP_context pointer
bic r2, r1, #FPEXC_EXCEPTION @ make sure exceptions are disabled
cmp r4, r10
beq check_for_exception @ we are returning to the same
@ process, so the registers are
@ still there. In this case, we do
@ not want to drop a pending exception.
VFPFMXR FPEXC, r2 @ enable VFP, disable any pending
@ exceptions, so we can get at the
@ rest of it
@ Save out the current registers to the old thread state
DBGSTR1 "save old state %p", r4
cmp r4, #0
beq no_old_VFP_process
VFPFMRX r2, FPSCR @ current status
VFPFMRX r6, FPINST @ FPINST (always there, rev0 onwards)
tst r1, #FPEXC_FPV2 @ is there an FPINST2 to read?
VFPFMRX r8, FPINST2, NE @ FPINST2 if needed - avoids reading
@ nonexistant reg on rev0
VFPFSTMIA r4 @ save the working registers
add r4, r4, #8*16+4
stmia r4, {r1, r2, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
@ and point r4 at the word at the
@ start of the register dump
no_old_VFP_process:
DBGSTR1 "load state %p", r10
str r10, [r3] @ update the last_VFP_context pointer
@ Load the saved state back into the VFP
add r4, r10, #8*16+4
ldmia r4, {r1, r2, r6, r8} @ load FPEXC, FPSCR, FPINST, FPINST2
VFPFLDMIA r10 @ reload the working registers while
@ FPEXC is in a safe state
tst r1, #FPEXC_FPV2 @ is there an FPINST2 to write?
VFPFMXR FPINST2, r8, NE @ FPINST2 if needed - avoids writing
@ nonexistant reg on rev0
VFPFMXR FPINST, r6
VFPFMXR FPSCR, r2 @ restore status
check_for_exception:
tst r1, #FPEXC_EXCEPTION
bne process_exception @ might as well handle the pending
@ exception before retrying branch
@ out before setting an FPEXC that
@ stops us reading stuff
VFPFMXR FPEXC, r1 @ restore FPEXC last
sub r5, r5, #4
str r5, [sp, #S_PC] @ retry the instruction
mov pc, r9 @ we think we have handled things
look_for_VFP_exceptions:
tst r1, #FPEXC_EXCEPTION
bne process_exception
VFPFMRX r2, FPSCR
tst r2, #FPSCR_IXE @ IXE doesn't set FPEXC_EXCEPTION !
bne process_exception
@ Fall into hand on to next handler - appropriate coproc instr
@ not recognised by VFP
DBGSTR "not VFP"
mov pc, lr
process_exception:
DBGSTR "bounce"
sub r5, r5, #4
str r5, [sp, #S_PC] @ retry the instruction on exit from
@ the imprecise exception handling in
@ the support code
mov r2, sp @ nothing stacked - regdump is at TOS
mov lr, r9 @ setup for a return to the user code.
@ Now call the C code to package up the bounce to the support code
@ r0 holds the trigger instruction
@ r1 holds the FPEXC value
@ r2 pointer to register dump
b VFP9_bounce @ we have handled this - the support
@ code will raise an exception if
@ required. If not, the user code will
@ retry the faulted instruction
last_VFP_context_address:
.word last_VFP_context
.globl vfp_get_float
vfp_get_float:
add pc, pc, r0, lsl #3
mov r0, r0
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
mrc p10, 0, r0, c\dr, c0, 0 @ fmrs r0, s0
mov pc, lr
mrc p10, 0, r0, c\dr, c0, 4 @ fmrs r0, s1
mov pc, lr
.endr
.globl vfp_put_float
vfp_put_float:
add pc, pc, r0, lsl #3
mov r0, r0
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
mcr p10, 0, r1, c\dr, c0, 0 @ fmsr r0, s0
mov pc, lr
mcr p10, 0, r1, c\dr, c0, 4 @ fmsr r0, s1
mov pc, lr
.endr
.globl vfp_get_double
vfp_get_double:
mov r0, r0, lsr #1
add pc, pc, r0, lsl #3
mov r0, r0
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
mrrc p10, 1, r0, r1, c\dr @ fmrrd r0, r1, d\dr
mov pc, lr
.endr
.globl vfp_put_double
vfp_put_double:
mov r0, r0, lsr #1
add pc, pc, r0, lsl #3
mov r0, r0
.irp dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
mcrr p10, 1, r1, r2, c\dr @ fmrrd r1, r2, d\dr
mov pc, lr
.endr
/*
* linux/arch/arm/vfp/vfpinstr.h
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* VFP instruction masks.
*/
#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
#define INST_CPRT(inst) ((inst) & (1 << 4))
#define INST_CPRT_L(inst) ((inst) & (1 << 20))
#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
#define INST_CPNUM(inst) ((inst) & 0xf00)
#define CPNUM(cp) ((cp) << 8)
#define FOP_MASK (0x00b00040)
#define FOP_FMAC (0x00000000)
#define FOP_FNMAC (0x00000040)
#define FOP_FMSC (0x00100000)
#define FOP_FNMSC (0x00100040)
#define FOP_FMUL (0x00200000)
#define FOP_FNMUL (0x00200040)
#define FOP_FADD (0x00300000)
#define FOP_FSUB (0x00300040)
#define FOP_FDIV (0x00800000)
#define FOP_EXT (0x00b00040)
#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
#define FEXT_MASK (0x000f0080)
#define FEXT_FCPY (0x00000000)
#define FEXT_FABS (0x00000080)
#define FEXT_FNEG (0x00010000)
#define FEXT_FSQRT (0x00010080)
#define FEXT_FCMP (0x00040000)
#define FEXT_FCMPE (0x00040080)
#define FEXT_FCMPZ (0x00050000)
#define FEXT_FCMPEZ (0x00050080)
#define FEXT_FCVT (0x00070080)
#define FEXT_FUITO (0x00080000)
#define FEXT_FSITO (0x00080080)
#define FEXT_FTOUI (0x000c0000)
#define FEXT_FTOUIZ (0x000c0080)
#define FEXT_FTOSI (0x000d0000)
#define FEXT_FTOSIZ (0x000d0080)
#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12)
#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
#define vfp_get_dm(inst) ((inst & 0x0000000f))
#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16)
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
#define FPSCR_N (1 << 31)
#define FPSCR_Z (1 << 30)
#define FPSCR_C (1 << 29)
#define FPSCR_V (1 << 28)
/*
* Since we aren't building with -mfpu=vfp, we need to code
* these instructions using their MRC/MCR equivalents.
*/
#define vfpreg(_vfp_) #_vfp_
#define fmrx(_vfp_) ({ \
u32 __v; \
asm("mrc%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmrx %0, " #_vfp_ \
: "=r" (__v)); \
__v; \
})
#define fmxr(_vfp_,_var_) \
asm("mcr%? p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
: : "r" (_var_))
u32 vfp_single_cpdo(u32 inst, u32 fpscr);
u32 vfp_single_cprt(u32 inst, u32 fpscr, struct pt_regs *regs);
u32 vfp_double_cpdo(u32 inst, u32 fpscr);
/*
* linux/arch/arm/vfp/vfpmodule.c
*
* Copyright (C) 2004 ARM Limited.
* Written by Deep Blue Solutions Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <asm/vfp.h>
#include "vfpinstr.h"
#include "vfp.h"
/*
* Our undef handlers (in entry.S)
*/
void vfp_testing_entry(void);
void vfp_support_entry(void);
void (*vfp_vector)(void) = vfp_testing_entry;
union vfp_state *last_VFP_context;
/*
* Dual-use variable.
* Used in startup: set to non-zero if VFP checks fail
* After startup, holds VFP architecture
*/
unsigned int VFP_arch;
/*
* Per-thread VFP initialisation.
*/
void vfp_flush_thread(union vfp_state *vfp)
{
memset(vfp, 0, sizeof(union vfp_state));
vfp->hard.fpexc = FPEXC_ENABLE;
vfp->hard.fpscr = FPSCR_ROUND_NEAREST;
/*
* Disable VFP to ensure we initialise it first.
*/
fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_ENABLE);
/*
* Ensure we don't try to overwrite our newly initialised
* state information on the first fault.
*/
if (last_VFP_context == vfp)
last_VFP_context = NULL;
}
/*
* Per-thread VFP cleanup.
*/
void vfp_release_thread(union vfp_state *vfp)
{
if (last_VFP_context == vfp)
last_VFP_context = NULL;
}
/*
* Raise a SIGFPE for the current process.
* sicode describes the signal being raised.
*/
void vfp_raise_sigfpe(unsigned int sicode, struct pt_regs *regs)
{
siginfo_t info;
memset(&info, 0, sizeof(info));
info.si_signo = SIGFPE;
info.si_code = sicode;
info.si_addr = (void *)(instruction_pointer(regs) - 4);
/*
* This is the same as NWFPE, because it's not clear what
* this is used for
*/
current->thread.error_code = 0;
current->thread.trap_no = 6;
force_sig_info(SIGFPE, &info, current);
}
static void vfp_panic(char *reason)
{
int i;
printk(KERN_ERR "VFP: Error: %s\n", reason);
printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
fmrx(FPEXC), fmrx(FPSCR), fmrx(FPINST));
for (i = 0; i < 32; i += 2)
printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
i, vfp_get_float(i), i+1, vfp_get_float(i+1));
}
/*
* Process bitmask of exception conditions.
*/
static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_regs *regs)
{
int si_code = 0;
pr_debug("VFP: raising exceptions %08x\n", exceptions);
if (exceptions == (u32)-1) {
vfp_panic("unhandled bounce");
vfp_raise_sigfpe(0, regs);
return;
}
/*
* If any of the status flags are set, update the FPSCR.
* Comparison instructions always return at least one of
* these flags set.
*/
if (exceptions & (FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V))
fpscr &= ~(FPSCR_N|FPSCR_Z|FPSCR_C|FPSCR_V);
fpscr |= exceptions;
fmxr(FPSCR, fpscr);
#define RAISE(stat,en,sig) \
if (exceptions & stat && fpscr & en) \
si_code = sig;
/*
* These are arranged in priority order, least to highest.
*/
RAISE(FPSCR_IXC, FPSCR_IXE, FPE_FLTRES);
RAISE(FPSCR_UFC, FPSCR_UFE, FPE_FLTUND);
RAISE(FPSCR_OFC, FPSCR_OFE, FPE_FLTOVF);
RAISE(FPSCR_IOC, FPSCR_IOE, FPE_FLTINV);
if (si_code)
vfp_raise_sigfpe(si_code, regs);
}
/*
* Emulate a VFP instruction.
*/
static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs)
{
u32 exceptions = (u32)-1;
pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr);
if (INST_CPRTDO(inst)) {
if (!INST_CPRT(inst)) {
/*
* CPDO
*/
if (vfp_single(inst)) {
exceptions = vfp_single_cpdo(inst, fpscr);
} else {
exceptions = vfp_double_cpdo(inst, fpscr);
}
} else {
/*
* A CPRT instruction can not appear in FPINST2, nor
* can it cause an exception. Therefore, we do not
* have to emulate it.
*/
}
} else {
/*
* A CPDT instruction can not appear in FPINST2, nor can
* it cause an exception. Therefore, we do not have to
* emulate it.
*/
}
return exceptions;
}
/*
* Package up a bounce condition.
*/
void VFP9_bounce(u32 trigger, u32 fpexc, struct pt_regs *regs)
{
u32 fpscr, orig_fpscr, exceptions, inst;
pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
/*
* Enable access to the VFP so we can handle the bounce.
*/
fmxr(FPEXC, fpexc & ~(FPEXC_EXCEPTION|FPEXC_INV|FPEXC_UFC|FPEXC_IOC));
orig_fpscr = fpscr = fmrx(FPSCR);
/*
* If we are running with inexact exceptions enabled, we need to
* emulate the trigger instruction. Note that as we're emulating
* the trigger instruction, we need to increment PC.
*/
if (fpscr & FPSCR_IXE) {
regs->ARM_pc += 4;
goto emulate;
}
barrier();
/*
* Modify fpscr to indicate the number of iterations remaining
*/
if (fpexc & FPEXC_EXCEPTION) {
u32 len;
len = fpexc + (1 << FPEXC_LENGTH_BIT);
fpscr &= ~FPSCR_LENGTH_MASK;
fpscr |= (len & FPEXC_LENGTH_MASK) << (FPSCR_LENGTH_BIT - FPEXC_LENGTH_BIT);
}
/*
* Handle the first FP instruction. We used to take note of the
* FPEXC bounce reason, but this appears to be unreliable.
* Emulate the bounced instruction instead.
*/
inst = fmrx(FPINST);
exceptions = vfp_emulate_instruction(inst, fpscr, regs);
if (exceptions)
vfp_raise_exceptions(exceptions, inst, orig_fpscr, regs);
/*
* If there isn't a second FP instruction, exit now.
*/
if (!(fpexc & FPEXC_FPV2))
return;
/*
* The barrier() here prevents fpinst2 being read
* before the condition above.
*/
barrier();
trigger = fmrx(FPINST2);
fpscr = fmrx(FPSCR);
emulate:
exceptions = vfp_emulate_instruction(trigger, fpscr, regs);
if (exceptions)
vfp_raise_exceptions(exceptions, trigger, orig_fpscr, regs);
}
/*
* VFP support code initialisation.
*/
static int __init vfp_init(void)
{
unsigned int vfpsid;
/*
* First check that there is a VFP that we can use.
* The handler is already setup to just log calls, so
* we just need to read the VFPSID register.
*/
vfpsid = fmrx(FPSID);
printk(KERN_INFO "VFP support v0.3: ");
if (VFP_arch) {
printk("not present\n");
} else if (vfpsid & FPSID_NODOUBLE) {
printk("no double precision support\n");
} else {
VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
(vfpsid & FPSID_VARIANT_MASK) >> FPSID_VARIANT_BIT,
(vfpsid & FPSID_REV_MASK) >> FPSID_REV_BIT);
vfp_vector = vfp_support_entry;
}
return 0;
}
late_initcall(vfp_init);
This diff is collapsed.
......@@ -13,6 +13,36 @@
#define FP_SIZE 35
#ifndef __ASSEMBLY__
/*
* VFP storage area has:
* - FPEXC, FPSCR, FPINST and FPINST2.
* - 16 double precision data registers
* - an implementation-dependant word of state for FLDMX/FSTMX
*
* FPEXC will always be non-zero once the VFP has been used in this process.
*/
struct vfp_hard_struct {
__u64 fpregs[16];
__u32 fpmx_state;
__u32 fpexc;
__u32 fpscr;
/*
* VFP implementation specific state
*/
__u32 fpinst;
__u32 fpinst2;
};
union vfp_state {
struct vfp_hard_struct hard;
};
extern void vfp_flush_thread(union vfp_state *);
extern void vfp_release_thread(union vfp_state *);
struct fp_hard_struct {
unsigned int save[FP_SIZE]; /* as yet undefined */
};
......@@ -27,3 +57,5 @@ union fp_state {
};
#endif
#endif
......@@ -12,12 +12,13 @@
#ifdef __KERNEL__
#include <asm/fpstate.h>
#ifndef __ASSEMBLY__
struct task_struct;
struct exec_domain;
#include <asm/fpstate.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/domain.h>
......@@ -53,6 +54,7 @@ struct thread_info {
struct cpu_context_save cpu_context; /* cpu context */
__u8 used_cp[16]; /* thread used copro */
union fp_state fpstate;
union vfp_state vfpstate;
struct restart_block restart_block;
};
......@@ -110,6 +112,7 @@ extern void free_thread_info(struct thread_info *);
#define TI_CPU_SAVE 28
#define TI_USED_CP 76
#define TI_FPSTATE (TI_USED_CP+16)
#define TI_VFPSTATE (TI_FPSTATE+FP_SIZE*4)
#endif
......
/*
* linux/include/asm-arm/vfp.h
*
* VFP register definitions.
* First, the standard VFP set.
*/
#define FPSID cr0
#define FPSCR cr1
#define FPEXC cr8
/* FPSID bits */
#define FPSID_IMPLEMENTER_BIT (24)
#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
#define FPSID_SOFTWARE (1<<23)
#define FPSID_FORMAT_BIT (21)
#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
#define FPSID_NODOUBLE (1<<20)
#define FPSID_ARCH_BIT (16)
#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
#define FPSID_PART_BIT (8)
#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
#define FPSID_VARIANT_BIT (4)
#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
#define FPSID_REV_BIT (0)
#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
/* FPEXC bits */
#define FPEXC_EXCEPTION (1<<31)
#define FPEXC_ENABLE (1<<30)
/* FPSCR bits */
#define FPSCR_DEFAULT_NAN (1<<25)
#define FPSCR_FLUSHTOZERO (1<<24)
#define FPSCR_ROUND_NEAREST (0<<22)
#define FPSCR_ROUND_PLUSINF (1<<22)
#define FPSCR_ROUND_MINUSINF (2<<22)
#define FPSCR_ROUND_TOZERO (3<<22)
#define FPSCR_RMODE_BIT (22)
#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
#define FPSCR_STRIDE_BIT (20)
#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
#define FPSCR_LENGTH_BIT (16)
#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
#define FPSCR_IOE (1<<8)
#define FPSCR_DZE (1<<9)
#define FPSCR_OFE (1<<10)
#define FPSCR_UFE (1<<11)
#define FPSCR_IXE (1<<12)
#define FPSCR_IDE (1<<15)
#define FPSCR_IOC (1<<0)
#define FPSCR_DZC (1<<1)
#define FPSCR_OFC (1<<2)
#define FPSCR_UFC (1<<3)
#define FPSCR_IXC (1<<4)
#define FPSCR_IDC (1<<7)
/*
* VFP9-S specific.
*/
#define FPINST cr9
#define FPINST2 cr10
/* FPEXC bits */
#define FPEXC_FPV2 (1<<28)
#define FPEXC_LENGTH_BIT (8)
#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
#define FPEXC_INV (1 << 7)
#define FPEXC_UFC (1 << 3)
#define FPEXC_OFC (1 << 2)
#define FPEXC_IOC (1 << 0)
/* Bit patterns for decoding the packaged operation descriptors */
#define VFPOPDESC_LENGTH_BIT (9)
#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
#define VFPOPDESC_UNUSED_BIT (24)
#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
/*
* linux/include/asm-arm/vfpmacros.h
*
* Assembler-only file containing VFP macros and register definitions.
*/
#include "vfp.h"
@ Macros to allow building with old toolkits (with no VFP support)
.macro VFPFMRX, rd, sysreg, cond
MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
.endm
.macro VFPFMXR, sysreg, rd, cond
MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
.endm
@ read all the working registers back into the VFP
.macro VFPFLDMIA, base
LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15}
.endm
@ write all the working registers out of the VFP
.macro VFPFSTMIA, base
STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15}
.endm
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