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Commit 4667fbe2 authored by Le Ma's avatar Le Ma Committed by Alex Deucher
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drm/amdgpu: do gfxhub init for all XCDs 

Each XCD needs to do gfxhub init
Signed-off-by: default avatarLe Ma <le.ma@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c0c27428
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Inline Side-by-side
Showing with 317 additions and 264 deletions
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
View file @ 4667fbe2
...@@ -43,19 +43,25 @@ static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev, ...@@ -43,19 +43,25 @@ static void gfxhub_v1_2_setup_vm_pt_regs(struct amdgpu_device *adev,
uint64_t page_table_base) uint64_t page_table_base)
{ {
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
int i;
WREG32_SOC15_OFFSET(GC, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, for (i = 0; i < adev->gfx.num_xcd; i++) {
hub->ctx_addr_distance * vmid, WREG32_SOC15_OFFSET(GC, i,
lower_32_bits(page_table_base)); regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
hub->ctx_addr_distance * vmid,
lower_32_bits(page_table_base));
WREG32_SOC15_OFFSET(GC, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, WREG32_SOC15_OFFSET(GC, i,
hub->ctx_addr_distance * vmid, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
upper_32_bits(page_table_base)); hub->ctx_addr_distance * vmid,
upper_32_bits(page_table_base));
}
} }
static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev) static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev)
{ {
uint64_t pt_base; uint64_t pt_base;
int i;
if (adev->gmc.pdb0_bo) if (adev->gmc.pdb0_bo)
pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
...@@ -67,26 +73,36 @@ static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev) ...@@ -67,26 +73,36 @@ static void gfxhub_v1_2_init_gart_aperture_regs(struct amdgpu_device *adev)
/* If use GART for FB translation, vmid0 page table covers both /* If use GART for FB translation, vmid0 page table covers both
* vram and system memory (gart) * vram and system memory (gart)
*/ */
if (adev->gmc.pdb0_bo) { for (i = 0; i < adev->gfx.num_xcd; i++) {
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, if (adev->gmc.pdb0_bo) {
(u32)(adev->gmc.fb_start >> 12)); WREG32_SOC15(GC, i,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
(u32)(adev->gmc.fb_start >> 44)); (u32)(adev->gmc.fb_start >> 12));
WREG32_SOC15(GC, i,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 12)); (u32)(adev->gmc.fb_start >> 44));
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 44)); WREG32_SOC15(GC, i,
} else { regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, (u32)(adev->gmc.gart_end >> 12));
(u32)(adev->gmc.gart_start >> 12)); WREG32_SOC15(GC, i,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_start >> 44)); (u32)(adev->gmc.gart_end >> 44));
} else {
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, WREG32_SOC15(GC, i,
(u32)(adev->gmc.gart_end >> 12)); regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, (u32)(adev->gmc.gart_start >> 12));
(u32)(adev->gmc.gart_end >> 44)); WREG32_SOC15(GC, i,
regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
(u32)(adev->gmc.gart_start >> 44));
WREG32_SOC15(GC, i,
regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
(u32)(adev->gmc.gart_end >> 12));
WREG32_SOC15(GC, i,
regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 44));
}
} }
} }
...@@ -94,160 +110,183 @@ static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev) ...@@ -94,160 +110,183 @@ static void gfxhub_v1_2_init_system_aperture_regs(struct amdgpu_device *adev)
{ {
uint64_t value; uint64_t value;
uint32_t tmp; uint32_t tmp;
int i;
/* Program the AGP BAR */ for (i = 0; i < adev->gfx.num_xcd; i++) {
WREG32_SOC15_RLC(GC, 0, regMC_VM_AGP_BASE, 0); /* Program the AGP BAR */
WREG32_SOC15_RLC(GC, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24); WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BASE, 0);
WREG32_SOC15_RLC(GC, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24); WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
WREG32_SOC15_RLC(GC, i, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
/* Program the system aperture low logical page number. */ if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
WREG32_SOC15_RLC(GC, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, /* Program the system aperture low logical page number. */
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18); WREG32_SOC15_RLC(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
/* if (adev->apu_flags & AMD_APU_IS_RAVEN2)
* Raven2 has a HW issue that it is unable to use the /*
* vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. * Raven2 has a HW issue that it is unable to use the
* So here is the workaround that increase system * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
* aperture high address (add 1) to get rid of the VM * So here is the workaround that increase system
* fault and hardware hang. * aperture high address (add 1) to get rid of the VM
*/ * fault and hardware hang.
WREG32_SOC15_RLC(GC, 0, */
regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32_SOC15_RLC(GC, i,
max((adev->gmc.fb_end >> 18) + 0x1, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
adev->gmc.agp_end >> 18)); max((adev->gmc.fb_end >> 18) + 0x1,
else adev->gmc.agp_end >> 18));
WREG32_SOC15_RLC(GC, 0, else
regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, WREG32_SOC15_RLC(GC, i,
max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18); regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
/* Set default page address. */
value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr); /* Set default page address. */
WREG32_SOC15(GC, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
(u32)(value >> 12)); WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
WREG32_SOC15(GC, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, (u32)(value >> 12));
(u32)(value >> 44)); WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
(u32)(value >> 44));
/* Program "protection fault". */
WREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, /* Program "protection fault". */
(u32)(adev->dummy_page_addr >> 12)); WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
WREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, (u32)(adev->dummy_page_addr >> 12));
(u32)((u64)adev->dummy_page_addr >> 44)); WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
(u32)((u64)adev->dummy_page_addr >> 44));
tmp = RREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2);
ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
WREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp); ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
} WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
}
/* In the case squeezing vram into GART aperture, we don't use
* FB aperture and AGP aperture. Disable them. /* In the case squeezing vram into GART aperture, we don't use
*/ * FB aperture and AGP aperture. Disable them.
if (adev->gmc.pdb0_bo) { */
WREG32_SOC15(GC, 0, regMC_VM_FB_LOCATION_TOP, 0); if (adev->gmc.pdb0_bo) {
WREG32_SOC15(GC, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF); WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_TOP, 0);
WREG32_SOC15(GC, 0, regMC_VM_AGP_TOP, 0); WREG32_SOC15(GC, i, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
WREG32_SOC15(GC, 0, regMC_VM_AGP_BOT, 0xFFFFFF); WREG32_SOC15(GC, i, regMC_VM_AGP_TOP, 0);
WREG32_SOC15(GC, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF); WREG32_SOC15(GC, i, regMC_VM_AGP_BOT, 0xFFFFFF);
WREG32_SOC15(GC, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0); WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
WREG32_SOC15(GC, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
}
} }
} }
static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev) static void gfxhub_v1_2_init_tlb_regs(struct amdgpu_device *adev)
{ {
uint32_t tmp; uint32_t tmp;
int i;
/* Setup TLB control */ for (i = 0; i < adev->gfx.num_xcd; i++) {
tmp = RREG32_SOC15(GC, 0, regMC_VM_MX_L1_TLB_CNTL); /* Setup TLB control */
tmp = RREG32_SOC15(GC, i, regMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
ENABLE_ADVANCED_DRIVER_MODEL, 1); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
MTYPE, MTYPE_UC);/* XXX for emulation. */ tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
WREG32_SOC15_RLC(GC, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); MTYPE, MTYPE_UC);/* XXX for emulation. */
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
WREG32_SOC15_RLC(GC, i, regMC_VM_MX_L1_TLB_CNTL, tmp);
}
} }
static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev) static void gfxhub_v1_2_init_cache_regs(struct amdgpu_device *adev)
{ {
uint32_t tmp; uint32_t tmp;
int i;
/* Setup L2 cache */ for (i = 0; i < adev->gfx.num_xcd; i++) {
tmp = RREG32_SOC15(GC, 0, regVM_L2_CNTL); /* Setup L2 cache */
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
/* XXX for emulation, Refer to closed source code.*/ tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, /* XXX for emulation, Refer to closed source code.*/
0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0); 0);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
WREG32_SOC15_RLC(GC, 0, regVM_L2_CNTL, tmp); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL, tmp);
tmp = RREG32_SOC15(GC, 0, regVM_L2_CNTL2);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); tmp = RREG32_SOC15(GC, i, regVM_L2_CNTL2);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
WREG32_SOC15_RLC(GC, 0, regVM_L2_CNTL2, tmp); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL2, tmp);
tmp = regVM_L2_CNTL3_DEFAULT;
if (adev->gmc.translate_further) { tmp = regVM_L2_CNTL3_DEFAULT;
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); if (adev->gmc.translate_further) {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
L2_CACHE_BIGK_FRAGMENT_SIZE, 9); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
} else { L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); } else {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
L2_CACHE_BIGK_FRAGMENT_SIZE, 6); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
} L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
WREG32_SOC15_RLC(GC, 0, regVM_L2_CNTL3, tmp); }
WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL3, tmp);
tmp = regVM_L2_CNTL4_DEFAULT;
if (adev->gmc.xgmi.connected_to_cpu) { tmp = regVM_L2_CNTL4_DEFAULT;
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1); if (adev->gmc.xgmi.connected_to_cpu) {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
} else { tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); } else {
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
}
WREG32_SOC15_RLC(GC, i, regVM_L2_CNTL4, tmp);
} }
WREG32_SOC15_RLC(GC, 0, regVM_L2_CNTL4, tmp);
} }
static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev) static void gfxhub_v1_2_enable_system_domain(struct amdgpu_device *adev)
{ {
uint32_t tmp; uint32_t tmp;
int i;
tmp = RREG32_SOC15(GC, 0, regVM_CONTEXT0_CNTL); for (i = 0; i < adev->gfx.num_xcd; i++) {
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); tmp = RREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
adev->gmc.vmid0_page_table_depth); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE, adev->gmc.vmid0_page_table_depth);
adev->gmc.vmid0_page_table_block_size); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, adev->gmc.vmid0_page_table_block_size);
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
WREG32_SOC15(GC, 0, regVM_CONTEXT0_CNTL, tmp); RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
WREG32_SOC15(GC, i, regVM_CONTEXT0_CNTL, tmp);
}
} }
static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev) static void gfxhub_v1_2_disable_identity_aperture(struct amdgpu_device *adev)
{ {
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, int i;
0XFFFFFFFF);
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0x0000000F);
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0);
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0);
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
WREG32_SOC15(GC, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
for (i = 0; i < adev->gfx.num_xcd; i++) {
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0XFFFFFFFF);
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0x0000000F);
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0);
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0);
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
WREG32_SOC15(GC, i,
regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
}
} }
static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
...@@ -255,7 +294,7 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) ...@@ -255,7 +294,7 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
unsigned num_level, block_size; unsigned num_level, block_size;
uint32_t tmp; uint32_t tmp;
int i; int i, j;
num_level = adev->vm_manager.num_level; num_level = adev->vm_manager.num_level;
block_size = adev->vm_manager.block_size; block_size = adev->vm_manager.block_size;
...@@ -264,81 +303,89 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev) ...@@ -264,81 +303,89 @@ static void gfxhub_v1_2_setup_vmid_config(struct amdgpu_device *adev)
else else
block_size -= 9; block_size -= 9;
for (i = 0; i <= 14; i++) { for (j = 0; j < adev->gfx.num_xcd; j++) {
tmp = RREG32_SOC15_OFFSET(GC, 0, regVM_CONTEXT1_CNTL, i); for (i = 0; i <= 14; i++) {
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); tmp = RREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL, i);
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
num_level); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, num_level);
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
1); DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, 1);
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
PAGE_TABLE_BLOCK_SIZE, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
block_size); PAGE_TABLE_BLOCK_SIZE,
/* Send no-retry XNACK on fault to suppress VM fault storm. block_size);
* On Aldebaran, XNACK can be enabled in the SQ per-process. /* Send no-retry XNACK on fault to suppress VM fault storm.
* Retry faults need to be enabled for that to work. * On Aldebaran, XNACK can be enabled in the SQ per-process.
*/ * Retry faults need to be enabled for that to work.
tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, */
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
!adev->gmc.noretry || RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
adev->asic_type == CHIP_ALDEBARAN); !adev->gmc.noretry ||
WREG32_SOC15_OFFSET(GC, 0, regVM_CONTEXT1_CNTL, adev->asic_type == CHIP_ALDEBARAN);
i * hub->ctx_distance, tmp); WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT1_CNTL,
WREG32_SOC15_OFFSET(GC, 0, i * hub->ctx_distance, tmp);
regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, WREG32_SOC15_OFFSET(GC, j,
i * hub->ctx_addr_distance, 0); regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
WREG32_SOC15_OFFSET(GC, 0, i * hub->ctx_addr_distance, 0);
regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, WREG32_SOC15_OFFSET(GC, j,
i * hub->ctx_addr_distance, 0); regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
WREG32_SOC15_OFFSET(GC, 0, i * hub->ctx_addr_distance, 0);
regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, WREG32_SOC15_OFFSET(GC, j,
i * hub->ctx_addr_distance, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
lower_32_bits(adev->vm_manager.max_pfn - 1)); i * hub->ctx_addr_distance,
WREG32_SOC15_OFFSET(GC, 0, lower_32_bits(adev->vm_manager.max_pfn - 1));
regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, WREG32_SOC15_OFFSET(GC, j,
i * hub->ctx_addr_distance, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
upper_32_bits(adev->vm_manager.max_pfn - 1)); i * hub->ctx_addr_distance,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}
} }
} }
static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev) static void gfxhub_v1_2_program_invalidation(struct amdgpu_device *adev)
{ {
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
unsigned i; unsigned i, j;
for (i = 0 ; i < 18; ++i) { for (j = 0; j < adev->gfx.num_xcd; j++) {
WREG32_SOC15_OFFSET(GC, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, for (i = 0 ; i < 18; ++i) {
i * hub->eng_addr_distance, 0xffffffff); WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
WREG32_SOC15_OFFSET(GC, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, i * hub->eng_addr_distance, 0xffffffff);
i * hub->eng_addr_distance, 0x1f); WREG32_SOC15_OFFSET(GC, j, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
i * hub->eng_addr_distance, 0x1f);
}
} }
} }
static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev) static int gfxhub_v1_2_gart_enable(struct amdgpu_device *adev)
{ {
if (amdgpu_sriov_vf(adev) && adev->asic_type != CHIP_ARCTURUS) { int i;
for (i = 0; i < adev->gfx.num_xcd; i++) {
if (amdgpu_sriov_vf(adev)) {
/* /*
* MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
* VF copy registers so vbios post doesn't program them, for * VF copy registers so vbios post doesn't program them, for
* SRIOV driver need to program them * SRIOV driver need to program them
*/ */
WREG32_SOC15_RLC(GC, 0, regMC_VM_FB_LOCATION_BASE, WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_BASE,
adev->gmc.vram_start >> 24); adev->gmc.vram_start >> 24);
WREG32_SOC15_RLC(GC, 0, regMC_VM_FB_LOCATION_TOP, WREG32_SOC15_RLC(GC, i, regMC_VM_FB_LOCATION_TOP,
adev->gmc.vram_end >> 24); adev->gmc.vram_end >> 24);
}
} }
/* GART Enable. */ /* GART Enable. */
...@@ -361,27 +408,29 @@ static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev) ...@@ -361,27 +408,29 @@ static void gfxhub_v1_2_gart_disable(struct amdgpu_device *adev)
{ {
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0]; struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
u32 tmp; u32 tmp;
u32 i; u32 i, j;
/* Disable all tables */ for (j = 0; j < adev->gfx.num_xcd; j++) {
for (i = 0; i < 16; i++) /* Disable all tables */
WREG32_SOC15_OFFSET(GC, 0, regVM_CONTEXT0_CNTL, for (i = 0; i < 16; i++)
i * hub->ctx_distance, 0); WREG32_SOC15_OFFSET(GC, j, regVM_CONTEXT0_CNTL,
i * hub->ctx_distance, 0);
/* Setup TLB control */
tmp = RREG32_SOC15(GC, 0, regMC_VM_MX_L1_TLB_CNTL); /* Setup TLB control */
tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); tmp = RREG32_SOC15(GC, j, regMC_VM_MX_L1_TLB_CNTL);
tmp = REG_SET_FIELD(tmp, tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
MC_VM_MX_L1_TLB_CNTL, tmp = REG_SET_FIELD(tmp,
ENABLE_ADVANCED_DRIVER_MODEL, MC_VM_MX_L1_TLB_CNTL,
0); ENABLE_ADVANCED_DRIVER_MODEL,
WREG32_SOC15_RLC(GC, 0, regMC_VM_MX_L1_TLB_CNTL, tmp); 0);
WREG32_SOC15_RLC(GC, j, regMC_VM_MX_L1_TLB_CNTL, tmp);
/* Setup L2 cache */
tmp = RREG32_SOC15(GC, 0, regVM_L2_CNTL); /* Setup L2 cache */
tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); tmp = RREG32_SOC15(GC, j, regVM_L2_CNTL);
WREG32_SOC15(GC, 0, regVM_L2_CNTL, tmp); tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
WREG32_SOC15(GC, 0, regVM_L2_CNTL3, 0); WREG32_SOC15(GC, j, regVM_L2_CNTL, tmp);
WREG32_SOC15(GC, j, regVM_L2_CNTL3, 0);
}
} }
/** /**
...@@ -394,38 +443,42 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev, ...@@ -394,38 +443,42 @@ static void gfxhub_v1_2_set_fault_enable_default(struct amdgpu_device *adev,
bool value) bool value)
{ {
u32 tmp; u32 tmp;
tmp = RREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL); int i;
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); for (i = 0; i < adev->gfx.num_xcd; i++) {
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, tmp = RREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL);
PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
VM_L2_PROTECTION_FAULT_CNTL, tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
value); tmp = REG_SET_FIELD(tmp,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, VM_L2_PROTECTION_FAULT_CNTL,
NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, value);
DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
if (!value) {
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
CRASH_ON_NO_RETRY_FAULT, 1); WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
CRASH_ON_RETRY_FAULT, 1); EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
if (!value) {
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
CRASH_ON_NO_RETRY_FAULT, 1);
tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
CRASH_ON_RETRY_FAULT, 1);
}
WREG32_SOC15(GC, i, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
} }
WREG32_SOC15(GC, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
} }
static void gfxhub_v1_2_init(struct amdgpu_device *adev) static void gfxhub_v1_2_init(struct amdgpu_device *adev)
......
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