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Commit 467f54b2 authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper
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ARM: dts: mvebu: introduce internal-regs node 

Introduce a 'internal-regs' subnode, under which all devices are
moved. This is not really needed for now, but will be for the
mvebu-mbus driver. This generates a lot of code movement since it's
indenting by one more tab all the devices.  So it was a good
opportunity to fix all the bad indentation.
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 82a68267
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Showing with 1452 additions and 1432 deletions
arch/arm/boot/dts/armada-370-db.dts
View file @ 467f54b2
...@@ -30,85 +30,87 @@ memory { ...@@ -30,85 +30,87 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
sata@a0000 {
phy1: ethernet-phy@1 { nr-ports = <2>;
reg = <1>; status = "okay";
}; };
};
ethernet@70000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
phy = <&phy0>; reg = <0>;
phy-mode = "rgmii-id"; };
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d4000 { phy1: ethernet-phy@1 {
pinctrl-0 = <&sdio_pins1>; reg = <1>;
pinctrl-names = "default"; };
/* };
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
usb@50000 { ethernet@70000 {
status = "okay"; status = "okay";
}; phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
usb@51000 { mvsdio@d4000 {
status = "okay"; pinctrl-0 = <&sdio_pins1>;
}; pinctrl-names = "default";
/*
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
spi0: spi@10600 { usb@50000 {
status = "okay"; status = "okay";
};
spi-flash@0 { usb@51000 {
#address-cells = <1>; status = "okay";
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
}; };
};
pcie-controller { spi0: spi@10600 {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};
}; };
pcie@2,0 {
/* Port 1, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-370-mirabox.dts
View file @ 467f54b2
...@@ -25,113 +25,115 @@ memory { ...@@ -25,113 +25,115 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
timer@20300 {
clock-frequency = <600000000>;
status = "okay";
};
pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
marvell,function = "gpo";
}; };
timer@20300 {
stat_led_pins: stat-led-pins { clock-frequency = <600000000>;
marvell,pins = "mpp64", "mpp65"; status = "okay";
marvell,function = "gpio";
}; };
};
gpio_leds { pinctrl {
compatible = "gpio-leds"; pwr_led_pin: pwr-led-pin {
pinctrl-names = "default"; marvell,pins = "mpp63";
pinctrl-0 = <&pwr_led_pin &stat_led_pins>; marvell,function = "gpo";
};
green_pwr_led { stat_led_pins: stat-led-pins {
label = "mirabox:green:pwr"; marvell,pins = "mpp64", "mpp65";
gpios = <&gpio1 31 1>; marvell,function = "gpio";
linux,default-trigger = "heartbeat"; };
}; };
blue_stat_led { gpio_leds {
label = "mirabox:blue:stat"; compatible = "gpio-leds";
gpios = <&gpio2 0 1>; pinctrl-names = "default";
linux,default-trigger = "cpu0"; pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
green_pwr_led {
label = "mirabox:green:pwr";
gpios = <&gpio1 31 1>;
linux,default-trigger = "heartbeat";
};
blue_stat_led {
label = "mirabox:blue:stat";
gpios = <&gpio2 0 1>;
linux,default-trigger = "cpu0";
};
green_stat_led {
label = "mirabox:green:stat";
gpios = <&gpio2 1 1>;
default-state = "off";
};
}; };
green_stat_led { mdio {
label = "mirabox:green:stat"; phy0: ethernet-phy@0 {
gpios = <&gpio2 1 1>; reg = <0>;
default-state = "off"; };
};
};
mdio { phy1: ethernet-phy@1 {
phy0: ethernet-phy@0 { reg = <1>;
reg = <0>; };
}; };
ethernet@70000 {
phy1: ethernet-phy@1 { status = "okay";
reg = <1>; phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
}; };
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
usb@50000 {
status = "okay";
};
usb@51000 { mvsdio@d4000 {
status = "okay"; pinctrl-0 = <&sdio_pins3>;
}; pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
i2c@11000 { usb@50000 {
status = "okay"; status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
}; };
};
pcie-controller { usb@51000 {
status = "okay"; status = "okay";
};
/* Internal mini-PCIe connector */ i2c@11000 {
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
};
}; };
/* Connected on the PCB to a USB 3.0 XHCI controller */ pcie-controller {
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay"; status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-370-rd.dts
View file @ 467f54b2
...@@ -28,60 +28,62 @@ memory { ...@@ -28,60 +28,62 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <200000000>; serial@12000 {
status = "okay"; clock-frequency = <200000000>;
}; status = "okay";
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
};
}; };
};
ethernet@70000 { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@74000 { ethernet@74000 {
status = "okay"; status = "okay";
phy = <&phy1>; phy = <&phy1>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
}; };
mvsdio@d4000 { mvsdio@d4000 {
pinctrl-0 = <&sdio_pins1>; pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default"; pinctrl-names = "default";
status = "okay"; status = "okay";
/* No CD or WP GPIOs */ /* No CD or WP GPIOs */
}; };
usb@50000 { usb@50000 {
status = "okay"; status = "okay";
}; };
usb@51000 { usb@51000 {
status = "okay"; status = "okay";
}; };
};
gpio-keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
button@1 { button@1 {
label = "Software Button"; label = "Software Button";
linux,code = <116>; linux,code = <116>;
gpios = <&gpio0 6 1>; gpios = <&gpio0 6 1>;
};
};
}; };
}; };
}; };
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ 467f54b2
...@@ -28,7 +28,6 @@ cpu@0 { ...@@ -28,7 +28,6 @@ cpu@0 {
}; };
}; };
soc { soc {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -36,192 +35,196 @@ soc { ...@@ -36,192 +35,196 @@ soc {
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
ranges = <0 0xd0000000 0x100000>; ranges = <0 0xd0000000 0x100000>;
mpic: interrupt-controller@20000 { internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic"; compatible = "marvell,mpic";
#interrupt-cells = <1>; #interrupt-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-controller; interrupt-controller;
}; };
coherency-fabric@20200 { coherency-fabric@20200 {
compatible = "marvell,coherency-fabric"; compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, reg = <0x20200 0xb0>, <0x21810 0x1c>;
<0x21810 0x1c>; };
};
serial@12000 { serial@12000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x12000 0x100>; reg = <0x12000 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <41>; interrupts = <41>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
serial@12100 { serial@12100 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x12100 0x100>; reg = <0x12100 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <42>; interrupts = <42>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
timer@20300 { timer@20300 {
compatible = "marvell,armada-370-xp-timer"; compatible = "marvell,armada-370-xp-timer";
reg = <0x20300 0x30>, reg = <0x20300 0x30>, <0x21040 0x30>;
<0x21040 0x30>; interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>; clocks = <&coreclk 2>;
clocks = <&coreclk 2>; };
};
sata@a0000 {
sata@a0000 { compatible = "marvell,orion-sata";
compatible = "marvell,orion-sata"; reg = <0xa0000 0x2400>;
reg = <0xa0000 0x2400>; interrupts = <55>;
interrupts = <55>; clocks = <&gateclk 15>, <&gateclk 30>;
clocks = <&gateclk 15>, <&gateclk 30>; clock-names = "0", "1";
clock-names = "0", "1"; status = "disabled";
status = "disabled"; };
};
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "marvell,orion-mdio"; compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>; reg = <0x72004 0x4>;
}; };
ethernet@70000 { ethernet@70000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0x70000 0x2500>; reg = <0x70000 0x2500>;
interrupts = <8>; interrupts = <8>;
clocks = <&gateclk 4>; clocks = <&gateclk 4>;
status = "disabled"; status = "disabled";
}; };
ethernet@74000 { ethernet@74000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0x74000 0x2500>; reg = <0x74000 0x2500>;
interrupts = <10>; interrupts = <10>;
clocks = <&gateclk 3>; clocks = <&gateclk 3>;
status = "disabled"; status = "disabled";
}; };
i2c0: i2c@11000 { i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c"; compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>; reg = <0x11000 0x20>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <31>; interrupts = <31>;
timeout-ms = <1000>; timeout-ms = <1000>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
i2c1: i2c@11100 { i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c"; compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>; reg = <0x11100 0x20>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
interrupts = <32>; interrupts = <32>;
timeout-ms = <1000>; timeout-ms = <1000>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
rtc@10300 { rtc@10300 {
compatible = "marvell,orion-rtc"; compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>; reg = <0x10300 0x20>;
interrupts = <50>; interrupts = <50>;
}; };
mvsdio@d4000 { mvsdio@d4000 {
compatible = "marvell,orion-sdio"; compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>; reg = <0xd4000 0x200>;
interrupts = <54>; interrupts = <54>;
clocks = <&gateclk 17>; clocks = <&gateclk 17>;
status = "disabled"; status = "disabled";
}; };
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
status = "disabled";
};
spi0: spi@10600 { usb@50000 {
compatible = "marvell,orion-spi"; compatible = "marvell,orion-ehci";
reg = <0x10600 0x28>; reg = <0x50000 0x500>;
#address-cells = <1>; interrupts = <45>;
#size-cells = <0>; status = "disabled";
cell-index = <0>; };
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 { usb@51000 {
compatible = "marvell,orion-spi"; compatible = "marvell,orion-ehci";
reg = <0x10680 0x28>; reg = <0x51000 0x500>;
#address-cells = <1>; interrupts = <46>;
#size-cells = <0>; status = "disabled";
cell-index = <1>; };
interrupts = <92>;
clocks = <&coreclk 0>; spi0: spi@10600 {
status = "disabled"; compatible = "marvell,orion-spi";
}; reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-bootcs@10400 { devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>; reg = <0x10400 0x8>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
devbus-cs0@10408 { devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>; reg = <0x10408 0x8>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
devbus-cs1@10410 { devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>; reg = <0x10410 0x8>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
devbus-cs2@10418 { devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>; reg = <0x10418 0x8>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
}; };
devbus-cs3@10420 { devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus"; compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>; reg = <0x10420 0x8>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
status = "disabled"; status = "disabled";
};
}; };
}; };
}; };
arch/arm/boot/dts/armada-370.dtsi
View file @ 467f54b2
...@@ -28,195 +28,195 @@ aliases { ...@@ -28,195 +28,195 @@ aliases {
}; };
soc { soc {
internal-regs {
mpic: interrupt-controller@20000 { system-controller@18200 {
reg = <0x20a00 0x1d0>,
<0x21870 0x58>;
};
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller"; compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x100>; reg = <0x18200 0x100>;
};
L2: l2-cache {
compatible = "marvell,aurora-outer-cache";
reg = <0xd0008000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0x18000 0x38>;
sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
"mpp13", "mpp14", "mpp15";
marvell,function = "sd0";
}; };
sdio_pins2: sdio-pins2 { L2: l2-cache {
marvell,pins = "mpp47", "mpp48", "mpp49", compatible = "marvell,aurora-outer-cache";
"mpp50", "mpp51", "mpp52"; reg = <0xd0008000 0x1000>;
marvell,function = "sd0"; cache-id-part = <0x100>;
wt-override;
}; };
sdio_pins3: sdio-pins3 { mpic: interrupt-controller@20000 {
marvell,pins = "mpp48", "mpp49", "mpp50", reg = <0x20a00 0x1d0>, <0x21870 0x58>;
"mpp51", "mpp52", "mpp53";
marvell,function = "sd0";
}; };
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@18180 { pinctrl {
compatible = "marvell,orion-gpio"; compatible = "marvell,mv88f6710-pinctrl";
reg = <0x18180 0x40>; reg = <0x18000 0x38>;
ngpios = <2>;
gpio-controller; sdio_pins1: sdio-pins1 {
#gpio-cells = <2>; marvell,pins = "mpp9", "mpp11", "mpp12",
interrupt-controller; "mpp13", "mpp14", "mpp15";
#interrupts-cells = <2>; marvell,function = "sd0";
interrupts = <91>; };
};
sdio_pins2: sdio-pins2 {
coreclk: mvebu-sar@18230 { marvell,pins = "mpp47", "mpp48", "mpp49",
compatible = "marvell,armada-370-core-clock"; "mpp50", "mpp51", "mpp52";
reg = <0x18230 0x08>; marvell,function = "sd0";
#clock-cells = <1>; };
};
sdio_pins3: sdio-pins3 {
gateclk: clock-gating-control@18220 { marvell,pins = "mpp48", "mpp49", "mpp50",
compatible = "marvell,armada-370-gating-clock"; "mpp51", "mpp52", "mpp53";
reg = <0x18220 0x4>; marvell,function = "sd0";
clocks = <&coreclk 0>; };
#clock-cells = <1>;
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
status = "okay";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
}; };
};
xor@60900 { gpio0: gpio@18100 {
compatible = "marvell,orion-xor"; compatible = "marvell,orion-gpio";
reg = <0x60900 0x100 reg = <0x18100 0x40>;
0x60b00 0x100>; ngpios = <32>;
status = "okay"; gpio-controller;
#gpio-cells = <2>;
xor10 { interrupt-controller;
interrupts = <94>; #interrupts-cells = <2>;
dmacap,memcpy; interrupts = <82>, <83>, <84>, <85>;
dmacap,xor;
};
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
}; };
};
usb@50000 {
clocks = <&coreclk 0>;
};
usb@51000 { gpio1: gpio@18140 {
clocks = <&coreclk 0>; compatible = "marvell,orion-gpio";
}; reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
thermal@18300 { gpio2: gpio@18180 {
compatible = "marvell,armada370-thermal"; compatible = "marvell,orion-gpio";
reg = <0x18300 0x4 reg = <0x18180 0x40>;
0x18304 0x4>; ngpios = <2>;
status = "okay"; gpio-controller;
}; #gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
pcie-controller { coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-370-pcie"; compatible = "marvell,armada-370-core-clock";
status = "disabled"; reg = <0x18230 0x08>;
device_type = "pci"; #clock-cells = <1>;
};
#address-cells = <3>; gateclk: clock-gating-control@18220 {
#size-cells = <2>; compatible = "marvell,armada-370-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
bus-range = <0x00 0xff>; xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
status = "okay";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
reg = <0x40000 0x2000>, <0x80000 0x2000>; xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
status = "okay";
xor10 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
reg-names = "pcie0.0", "pcie1.0"; usb@50000 {
clocks = <&coreclk 0>;
};
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ usb@51000 {
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ clocks = <&coreclk 0>;
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ };
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 { thermal@18300 {
device_type = "pci"; compatible = "marvell,armada370-thermal";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; reg = <0x18300 0x4
reg = <0x0800 0 0 0 0>; 0x18304 0x4>;
#address-cells = <3>; status = "okay";
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
}; };
pcie@2,0 { pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>;
ranges; bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>; reg = <0x40000 0x2000>, <0x80000 0x2000>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; reg-names = "pcie0.0", "pcie1.0";
clocks = <&gateclk 9>;
status = "disabled"; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-db.dts
View file @ 467f54b2
...@@ -30,128 +30,130 @@ memory { ...@@ -30,128 +30,130 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
}; };
serial@12100 {
phy1: ethernet-phy@1 { clock-frequency = <250000000>;
reg = <1>; status = "okay";
}; };
serial@12200 {
phy2: ethernet-phy@2 { clock-frequency = <250000000>;
reg = <25>; status = "okay";
}; };
serial@12300 {
phy3: ethernet-phy@3 { clock-frequency = <250000000>;
reg = <27>; status = "okay";
}; };
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@50000 { sata@a0000 {
status = "okay"; nr-ports = <2>;
}; status = "okay";
};
usb@51000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
}; reg = <0>;
};
usb@52000 { phy1: ethernet-phy@1 {
status = "okay"; reg = <1>;
}; };
spi0: spi@10600 { phy2: ethernet-phy@2 {
status = "okay"; reg = <25>;
};
spi-flash@0 { phy3: ethernet-phy@3 {
#address-cells = <1>; reg = <27>;
#size-cells = <1>; };
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
}; };
};
pcie-controller { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
/* mvsdio@d4000 {
* All 6 slots are physically present as pinctrl-0 = <&sdio_pins>;
* standard PCIe slots on the board. pinctrl-names = "default";
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
/* No CD or WP GPIOs */
}; };
pcie@2,0 {
/* Port 0, Lane 1 */ usb@50000 {
status = "okay"; status = "okay";
}; };
pcie@3,0 {
/* Port 0, Lane 2 */ usb@51000 {
status = "okay"; status = "okay";
}; };
pcie@4,0 {
/* Port 0, Lane 3 */ usb@52000 {
status = "okay"; status = "okay";
}; };
pcie@9,0 {
/* Port 2, Lane 0 */ spi0: spi@10600 {
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
}; };
pcie@10,0 {
/* Port 3, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-gp.dts
View file @ 467f54b2
...@@ -37,126 +37,128 @@ memory { ...@@ -37,126 +37,128 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
}; };
serial@12100 {
phy1: ethernet-phy@1 { clock-frequency = <250000000>;
reg = <17>; status = "okay";
}; };
serial@12200 {
phy2: ethernet-phy@2 { clock-frequency = <250000000>;
reg = <18>; status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
}; };
phy3: ethernet-phy@3 { sata@a0000 {
reg = <19>; nr-ports = <2>;
status = "okay";
}; };
};
ethernet@70000 { mdio {
status = "okay"; phy0: ethernet-phy@0 {
phy = <&phy0>; reg = <16>;
phy-mode = "rgmii-id"; };
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
spi0: spi@10600 { phy1: ethernet-phy@1 {
status = "okay"; reg = <17>;
};
spi-flash@0 { phy2: ethernet-phy@2 {
#address-cells = <1>; reg = <18>;
#size-cells = <1>; };
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
devbus-bootcs@10400 { phy3: ethernet-phy@3 {
status = "okay"; reg = <19>;
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */ };
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
}; };
};
pcie-controller { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
/* spi0: spi@10600 {
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
}; };
pcie@9,0 {
/* Port 2, Lane 0 */ devbus-bootcs@10400 {
status = "okay"; status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
}; };
pcie@10,0 {
/* Port 3, Lane 0 */ pcie-controller {
status = "okay"; status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file @ 467f54b2
...@@ -44,140 +44,142 @@ cpu@1 { ...@@ -44,140 +44,142 @@ cpu@1 {
}; };
soc { soc {
pinctrl { internal-regs {
compatible = "marvell,mv78230-pinctrl"; pinctrl {
reg = <0x18000 0x38>; compatible = "marvell,mv78230-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32", sdio_pins: sdio-pins {
"mpp33", "mpp34", "mpp35"; marvell,pins = "mpp30", "mpp31", "mpp32",
marvell,function = "sd0"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
}; };
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
/* gpio0: gpio@18100 {
* MV78230 has 2 PCIe units Gen2.0: One unit can be compatible = "marvell,orion-gpio";
* configured as x4 or quad x1 lanes. One unit is reg = <0x18100 0x40>;
* x4/x1. ngpios = <32>;
*/ gpio-controller;
pcie-controller { #gpio-cells = <2>;
compatible = "marvell,armada-xp-pcie"; interrupt-controller;
status = "disabled"; #interrupts-cells = <2>;
device_type = "pci"; interrupts = <82>, <83>, <84>, <85>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
}; };
pcie@2,0 { gpio1: gpio@18140 {
device_type = "pci"; compatible = "marvell,orion-gpio";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; reg = <0x18140 0x40>;
reg = <0x1000 0 0 0 0>; ngpios = <17>;
#address-cells = <3>; gpio-controller;
#size-cells = <2>; #gpio-cells = <2>;
#interrupt-cells = <1>; interrupt-controller;
ranges; #interrupts-cells = <2>;
interrupt-map-mask = <0 0 0 0>; interrupts = <87>, <88>, <89>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
}; };
pcie@3,0 { /*
device_type = "pci"; * MV78230 has 2 PCIe units Gen2.0: One unit can be
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; * configured as x4 or quad x1 lanes. One unit is
reg = <0x1800 0 0 0 0>; * x4/x1.
#address-cells = <3>; */
#size-cells = <2>; pcie-controller {
#interrupt-cells = <1>; compatible = "marvell,armada-xp-pcie";
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled"; status = "disabled";
};
pcie@4,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 { #address-cells = <3>;
device_type = "pci"; #size-cells = <2>;
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>; bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
#interrupt-cells = <1>; 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
ranges; 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
interrupt-map-mask = <0 0 0 0>; 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
interrupt-map = <0 0 0 0 &mpic 99>; 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
marvell,pcie-port = <2>; 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
marvell,pcie-lane = <0>; 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
clocks = <&gateclk 26>;
status = "disabled"; pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file @ 467f54b2
...@@ -45,177 +45,179 @@ cpu@1 { ...@@ -45,177 +45,179 @@ cpu@1 {
}; };
soc { soc {
pinctrl { internal-regs {
compatible = "marvell,mv78260-pinctrl"; pinctrl {
reg = <0x18000 0x38>; compatible = "marvell,mv78260-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32", sdio_pins: sdio-pins {
"mpp33", "mpp34", "mpp35"; marvell,pins = "mpp30", "mpp31", "mpp32",
marvell,function = "sd0"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
}; };
};
gpio0: gpio@18100 { gpio0: gpio@18100 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>; reg = <0x18100 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>; interrupts = <82>, <83>, <84>, <85>;
}; };
gpio1: gpio@18140 { gpio1: gpio@18140 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>; reg = <0x18140 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>; interrupts = <87>, <88>, <89>, <90>;
}; };
gpio2: gpio@18180 { gpio2: gpio@18180 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>; reg = <0x18180 0x40>;
ngpios = <3>; ngpios = <3>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <91>; interrupts = <91>;
}; };
ethernet@34000 { ethernet@34000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0x34000 0x2500>; reg = <0x34000 0x2500>;
interrupts = <14>; interrupts = <14>;
clocks = <&gateclk 1>; clocks = <&gateclk 1>;
status = "disabled"; status = "disabled";
};
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
}; };
pcie@2,0 { /*
device_type = "pci"; * MV78260 has 3 PCIe units Gen2.0: Two units can be
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; * configured as x4 or quad x1 lanes. One unit is
reg = <0x1000 0 0 0 0>; * x4/x1.
#address-cells = <3>; */
#size-cells = <2>; pcie-controller {
#interrupt-cells = <1>; compatible = "marvell,armada-xp-pcie";
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled"; status = "disabled";
};
pcie@3,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 { bus-range = <0x00 0xff>;
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
reg = <0x4800 0 0 0 0>; 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
#address-cells = <3>; 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
#size-cells = <2>; 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
#interrupt-cells = <1>; 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
ranges; 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
interrupt-map-mask = <0 0 0 0>; 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
interrupt-map = <0 0 0 0 &mpic 99>; 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
marvell,pcie-port = <2>; 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>; pcie@1,0 {
status = "disabled"; device_type = "pci";
}; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
pcie@10,0 { #address-cells = <3>;
device_type = "pci"; #size-cells = <2>;
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; #interrupt-cells = <1>;
reg = <0x5000 0 0 0 0>; ranges;
#address-cells = <3>; interrupt-map-mask = <0 0 0 0>;
#size-cells = <2>; interrupt-map = <0 0 0 0 &mpic 58>;
#interrupt-cells = <1>; marvell,pcie-port = <0>;
ranges; marvell,pcie-lane = <0>;
interrupt-map-mask = <0 0 0 0>; clocks = <&gateclk 5>;
interrupt-map = <0 0 0 0 &mpic 103>; status = "disabled";
marvell,pcie-port = <3>; };
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>; pcie@2,0 {
status = "disabled"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View file @ 467f54b2
...@@ -60,243 +60,245 @@ cpu@3 { ...@@ -60,243 +60,245 @@ cpu@3 {
}; };
soc { soc {
pinctrl { internal-regs {
compatible = "marvell,mv78460-pinctrl"; pinctrl {
reg = <0x18000 0x38>; compatible = "marvell,mv78460-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins { sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32", marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35"; "mpp33", "mpp34", "mpp35";
marvell,function = "sd0"; marvell,function = "sd0";
};
}; };
};
gpio0: gpio@18100 { gpio0: gpio@18100 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>; reg = <0x18100 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>; interrupts = <82>, <83>, <84>, <85>;
}; };
gpio1: gpio@18140 { gpio1: gpio@18140 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>; reg = <0x18140 0x40>;
ngpios = <32>; ngpios = <32>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>; interrupts = <87>, <88>, <89>, <90>;
}; };
gpio2: gpio@18180 { gpio2: gpio@18180 {
compatible = "marvell,orion-gpio"; compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>; reg = <0x18180 0x40>;
ngpios = <3>; ngpios = <3>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupts-cells = <2>; #interrupts-cells = <2>;
interrupts = <91>; interrupts = <91>;
}; };
ethernet@34000 { ethernet@34000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0x34000 0x2500>; reg = <0x34000 0x2500>;
interrupts = <14>; interrupts = <14>;
clocks = <&gateclk 1>; clocks = <&gateclk 1>;
status = "disabled"; status = "disabled";
}; };
/* /*
* MV78460 has 4 PCIe units Gen2.0: Two units can be * MV78460 has 4 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. Two units are * configured as x4 or quad x1 lanes. Two units are
* x4/x1. * x4/x1.
*/ */
pcie-controller { pcie-controller {
compatible = "marvell,armada-xp-pcie"; compatible = "marvell,armada-xp-pcie";
status = "disabled"; status = "disabled";
device_type = "pci"; device_type = "pci";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
bus-range = <0x00 0xff>; bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 { pcie@1,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>; reg = <0x0800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>; interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 5>; clocks = <&gateclk 5>;
status = "disabled"; status = "disabled";
}; };
pcie@2,0 { pcie@2,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>; reg = <0x1000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>; interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
marvell,pcie-lane = <1>; marvell,pcie-lane = <1>;
clocks = <&gateclk 6>; clocks = <&gateclk 6>;
status = "disabled"; status = "disabled";
}; };
pcie@3,0 { pcie@3,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>; reg = <0x1800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>; interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
marvell,pcie-lane = <2>; marvell,pcie-lane = <2>;
clocks = <&gateclk 7>; clocks = <&gateclk 7>;
status = "disabled"; status = "disabled";
}; };
pcie@4,0 { pcie@4,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>; reg = <0x2000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>; interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>; marvell,pcie-port = <0>;
marvell,pcie-lane = <3>; marvell,pcie-lane = <3>;
clocks = <&gateclk 8>; clocks = <&gateclk 8>;
status = "disabled"; status = "disabled";
}; };
pcie@5,0 { pcie@5,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>; reg = <0x2800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>; interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>; marvell,pcie-port = <1>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 9>; clocks = <&gateclk 9>;
status = "disabled"; status = "disabled";
}; };
pcie@6,0 { pcie@6,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>; reg = <0x3000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>; interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>; marvell,pcie-port = <1>;
marvell,pcie-lane = <1>; marvell,pcie-lane = <1>;
clocks = <&gateclk 10>; clocks = <&gateclk 10>;
status = "disabled"; status = "disabled";
}; };
pcie@7,0 { pcie@7,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>; reg = <0x3800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>; interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>; marvell,pcie-port = <1>;
marvell,pcie-lane = <2>; marvell,pcie-lane = <2>;
clocks = <&gateclk 11>; clocks = <&gateclk 11>;
status = "disabled"; status = "disabled";
}; };
pcie@8,0 { pcie@8,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>; reg = <0x4000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>; interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>; marvell,pcie-port = <1>;
marvell,pcie-lane = <3>; marvell,pcie-lane = <3>;
clocks = <&gateclk 12>; clocks = <&gateclk 12>;
status = "disabled"; status = "disabled";
}; };
pcie@9,0 { pcie@9,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>; reg = <0x4800 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>; interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>; marvell,pcie-port = <2>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 26>; clocks = <&gateclk 26>;
status = "disabled"; status = "disabled";
}; };
pcie@10,0 { pcie@10,0 {
device_type = "pci"; device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>; reg = <0x5000 0 0 0 0>;
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
ranges; ranges;
interrupt-map-mask = <0 0 0 0>; interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>; interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>; marvell,pcie-port = <3>;
marvell,pcie-lane = <0>; marvell,pcie-lane = <0>;
clocks = <&gateclk 27>; clocks = <&gateclk 27>;
status = "disabled"; status = "disabled";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ 467f54b2
...@@ -27,154 +27,156 @@ memory { ...@@ -27,154 +27,156 @@ memory {
}; };
soc { soc {
serial@12000 { internal-regs {
clock-frequency = <250000000>; serial@12000 {
status = "okay"; clock-frequency = <250000000>;
}; status = "okay";
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
marvell,function = "gpio";
}; };
}; serial@12100 {
leds { clock-frequency = <250000000>;
compatible = "gpio-leds"; status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
}; };
pinctrl {
yellow_led { led_pins: led-pins-0 {
label = "yellow_led"; marvell,pins = "mpp49", "mpp51", "mpp53";
gpios = <&gpio1 19 1>; marvell,function = "gpio";
default-state = "off"; };
}; };
leds {
green_led { compatible = "gpio-leds";
label = "green_led"; pinctrl-names = "default";
gpios = <&gpio1 21 1>; pinctrl-0 = <&led_pins>;
default-state = "off";
linux,default-trigger = "heartbeat"; red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
};
yellow_led {
label = "yellow_led";
gpios = <&gpio1 19 1>;
default-state = "off";
};
green_led {
label = "green_led";
gpios = <&gpio1 21 1>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
}; };
};
gpio_keys { gpio_keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
button@1 { button@1 {
label = "Init Button"; label = "Init Button";
linux,code = <116>; linux,code = <116>;
gpios = <&gpio1 28 0>; gpios = <&gpio1 28 0>;
};
}; };
};
mdio { mdio {
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
}; };
phy1: ethernet-phy@1 { phy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
}; };
phy2: ethernet-phy@2 { phy2: ethernet-phy@2 {
reg = <2>; reg = <2>;
}; };
phy3: ethernet-phy@3 { phy3: ethernet-phy@3 {
reg = <3>; reg = <3>;
};
}; };
};
ethernet@70000 { ethernet@70000 {
status = "okay"; status = "okay";
phy = <&phy0>; phy = <&phy0>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@74000 { ethernet@74000 {
status = "okay"; status = "okay";
phy = <&phy1>; phy = <&phy1>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@30000 { ethernet@30000 {
status = "okay"; status = "okay";
phy = <&phy2>; phy = <&phy2>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
ethernet@34000 { ethernet@34000 {
status = "okay"; status = "okay";
phy = <&phy3>; phy = <&phy3>;
phy-mode = "sgmii"; phy-mode = "sgmii";
}; };
i2c@11000 { i2c@11000 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
}; };
i2c@11100 { i2c@11100 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
s35390a: s35390a@30 { s35390a: s35390a@30 {
compatible = "s35390a"; compatible = "s35390a";
reg = <0x30>; reg = <0x30>;
};
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
}; };
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
devbus-bootcs@10400 { devbus-bootcs@10400 {
status = "okay"; status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */ /* Device Bus parameters are required */
/* Read parameters */ /* Read parameters */
devbus,bus-width = <8>; devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>; devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>; devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>; devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>; devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>; devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>; devbus,rd-hold-ps = <0>;
/* Write parameters */ /* Write parameters */
devbus,sync-enable = <0>; devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>; devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>; devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>; devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */ /* NOR 128 MiB */
nor@0 { nor@0 {
compatible = "cfi-flash"; compatible = "cfi-flash";
reg = <0 0x8000000>; reg = <0 0x8000000>;
bank-width = <2>; bank-width = <2>;
};
}; };
};
pcie-controller { pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay"; status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
}; };
}; };
}; };
......
arch/arm/boot/dts/armada-xp.dtsi
View file @ 467f54b2
...@@ -22,141 +22,140 @@ / { ...@@ -22,141 +22,140 @@ / {
model = "Marvell Armada XP family SoC"; model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp"; compatible = "marvell,armadaxp", "marvell,armada-370-xp";
soc { soc {
L2: l2-cache { internal-regs {
compatible = "marvell,aurora-system-cache"; L2: l2-cache {
reg = <0x08000 0x1000>; compatible = "marvell,aurora-system-cache";
cache-id-part = <0x100>; reg = <0x08000 0x1000>;
wt-override; cache-id-part = <0x100>;
}; wt-override;
};
mpic: interrupt-controller@20000 { mpic: interrupt-controller@20000 {
reg = <0x20a00 0x2d0>, reg = <0x20a00 0x2d0>, <0x21070 0x58>;
<0x21070 0x58>; };
};
armada-370-xp-pmsu@22000 { armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu"; compatible = "marvell,armada-370-xp-pmsu";
reg = <0x22100 0x430>, reg = <0x22100 0x430>, <0x20800 0x20>;
<0x20800 0x20>; };
};
serial@12200 { serial@12200 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x12200 0x100>; reg = <0x12200 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <43>; interrupts = <43>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
serial@12300 { serial@12300 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x12300 0x100>; reg = <0x12300 0x100>;
reg-shift = <2>; reg-shift = <2>;
interrupts = <44>; interrupts = <44>;
reg-io-width = <1>; reg-io-width = <1>;
status = "disabled"; status = "disabled";
}; };
timer@20300 { timer@20300 {
marvell,timer-25Mhz; marvell,timer-25Mhz;
}; };
coreclk: mvebu-sar@18230 { coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-xp-core-clock"; compatible = "marvell,armada-xp-core-clock";
reg = <0x18230 0x08>; reg = <0x18230 0x08>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
cpuclk: clock-complex@18700 { cpuclk: clock-complex@18700 {
#clock-cells = <1>; #clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock"; compatible = "marvell,armada-xp-cpu-clock";
reg = <0x18700 0xA0>; reg = <0x18700 0xA0>;
clocks = <&coreclk 1>; clocks = <&coreclk 1>;
}; };
gateclk: clock-gating-control@18220 { gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-xp-gating-clock"; compatible = "marvell,armada-xp-gating-clock";
reg = <0x18220 0x4>; reg = <0x18220 0x4>;
clocks = <&coreclk 0>; clocks = <&coreclk 0>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
system-controller@18200 { system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller"; compatible = "marvell,armada-370-xp-system-controller";
reg = <0x18200 0x500>; reg = <0x18200 0x500>;
}; };
ethernet@30000 { ethernet@30000 {
compatible = "marvell,armada-370-neta"; compatible = "marvell,armada-370-neta";
reg = <0x30000 0x2500>; reg = <0x30000 0x2500>;
interrupts = <12>; interrupts = <12>;
clocks = <&gateclk 2>; clocks = <&gateclk 2>;
status = "disabled"; status = "disabled";
};
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
}; };
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor@f0900 { xor@60900 {
compatible = "marvell,orion-xor"; compatible = "marvell,orion-xor";
reg = <0xF0900 0x100 reg = <0x60900 0x100
0xF0B00 0x100>; 0x60b00 0x100>;
clocks = <&gateclk 28>; clocks = <&gateclk 22>;
status = "okay"; status = "okay";
xor00 { xor10 {
interrupts = <94>; interrupts = <51>;
dmacap,memcpy; dmacap,memcpy;
dmacap,xor; dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
}; };
xor01 {
interrupts = <95>; xor@f0900 {
dmacap,memcpy; compatible = "marvell,orion-xor";
dmacap,xor; reg = <0xF0900 0x100
dmacap,memset; 0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
}; };
};
usb@50000 { usb@50000 {
clocks = <&gateclk 18>; clocks = <&gateclk 18>;
}; };
usb@51000 { usb@51000 {
clocks = <&gateclk 19>; clocks = <&gateclk 19>;
}; };
usb@52000 { usb@52000 {
compatible = "marvell,orion-ehci"; compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>; reg = <0x52000 0x500>;
interrupts = <47>; interrupts = <47>;
clocks = <&gateclk 20>; clocks = <&gateclk 20>;
status = "disabled"; status = "disabled";
}; };
thermal@182b0 { thermal@182b0 {
compatible = "marvell,armadaxp-thermal"; compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4 reg = <0x182b0 0x4
0x184d0 0x4>; 0x184d0 0x4>;
status = "okay"; status = "okay";
};
}; };
}; };
}; };
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