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Commit 47e68987 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu: add SMU 8.0 register headers 

These are register headers for the SMU (System Management Unit)
block on the GPU.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Acked-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bc136e13
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drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_d.h 0 → 100644
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/*
* SMU_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_8_0_D_H
#define SMU_8_0_D_H
#define ixTHM_TCON_CSR_CONFIG 0xd82014a4
#define ixTHM_TCON_CSR_DATA 0xd82014a8
#define ixTHM_TCON_HTC 0xd8200c64
#define ixTHM_TCON_CUR_TMP 0xd8200ca4
#define ixTHM_TCON_THERM_TRIP 0xd8200ce4
#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
#define ixTHM_THERMAL_INT_ENA 0xd8200d10
#define ixTHM_THERMAL_INT_CTRL 0xd8200d14
#define ixTHM_THERMAL_INT_STATUS 0xd8200d18
#define ixTMON0_RDIL0_DATA 0xd8202000
#define ixTMON0_RDIL1_DATA 0xd8202004
#define ixTMON0_RDIL2_DATA 0xd8202008
#define ixTMON0_RDIL3_DATA 0xd820200c
#define ixTMON0_RDIL4_DATA 0xd8202010
#define ixTMON0_RDIL5_DATA 0xd8202014
#define ixTMON0_RDIL6_DATA 0xd8202018
#define ixTMON0_RDIL7_DATA 0xd820201c
#define ixTMON0_RDIL8_DATA 0xd8202020
#define ixTMON0_RDIL9_DATA 0xd8202024
#define ixTMON0_RDIL10_DATA 0xd8202028
#define ixTMON0_RDIL11_DATA 0xd820202c
#define ixTMON0_RDIL12_DATA 0xd8202030
#define ixTMON0_RDIL13_DATA 0xd8202034
#define ixTMON0_RDIL14_DATA 0xd8202038
#define ixTMON0_RDIL15_DATA 0xd820203c
#define ixTMON0_RDIR0_DATA 0xd8202040
#define ixTMON0_RDIR1_DATA 0xd8202044
#define ixTMON0_RDIR2_DATA 0xd8202048
#define ixTMON0_RDIR3_DATA 0xd820204c
#define ixTMON0_RDIR4_DATA 0xd8202050
#define ixTMON0_RDIR5_DATA 0xd8202054
#define ixTMON0_RDIR6_DATA 0xd8202058
#define ixTMON0_RDIR7_DATA 0xd820205c
#define ixTMON0_RDIR8_DATA 0xd8202060
#define ixTMON0_RDIR9_DATA 0xd8202064
#define ixTMON0_RDIR10_DATA 0xd8202068
#define ixTMON0_RDIR11_DATA 0xd820206c
#define ixTMON0_RDIR12_DATA 0xd8202070
#define ixTMON0_RDIR13_DATA 0xd8202074
#define ixTMON0_RDIR14_DATA 0xd8202078
#define ixTMON0_RDIR15_DATA 0xd820207c
#define ixTMON0_INT_DATA 0xd8202080
#define ixTMON0_RDIL_PRESENT0 0xd8202084
#define ixTMON0_RDIL_PRESENT1 0xd8202088
#define ixTMON0_RDIR_PRESENT0 0xd820208c
#define ixTMON0_RDIR_PRESENT1 0xd8202090
#define ixTMON0_CONFIG 0xd8202098
#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0
#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4
#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8
#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac
#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0
#define ixTMON0_DEBUG0 0xd82020b4
#define ixTMON0_DEBUG1 0xd82020b8
#define ixTMON1_RDIL0_DATA 0xd8202100
#define ixTMON1_RDIL1_DATA 0xd8202104
#define ixTMON1_RDIL2_DATA 0xd8202108
#define ixTMON1_RDIL3_DATA 0xd820210c
#define ixTMON1_RDIL4_DATA 0xd8202110
#define ixTMON1_RDIL5_DATA 0xd8202114
#define ixTMON1_RDIL6_DATA 0xd8202118
#define ixTMON1_RDIL7_DATA 0xd820211c
#define ixTMON1_RDIL8_DATA 0xd8202120
#define ixTMON1_RDIL9_DATA 0xd8202124
#define ixTMON1_RDIL10_DATA 0xd8202128
#define ixTMON1_RDIL11_DATA 0xd820212c
#define ixTMON1_RDIL12_DATA 0xd8202130
#define ixTMON1_RDIL13_DATA 0xd8202134
#define ixTMON1_RDIL14_DATA 0xd8202138
#define ixTMON1_RDIL15_DATA 0xd820213c
#define ixTMON1_RDIR0_DATA 0xd8202140
#define ixTMON1_RDIR1_DATA 0xd8202144
#define ixTMON1_RDIR2_DATA 0xd8202148
#define ixTMON1_RDIR3_DATA 0xd820214c
#define ixTMON1_RDIR4_DATA 0xd8202150
#define ixTMON1_RDIR5_DATA 0xd8202154
#define ixTMON1_RDIR6_DATA 0xd8202158
#define ixTMON1_RDIR7_DATA 0xd820215c
#define ixTMON1_RDIR8_DATA 0xd8202160
#define ixTMON1_RDIR9_DATA 0xd8202164
#define ixTMON1_RDIR10_DATA 0xd8202168
#define ixTMON1_RDIR11_DATA 0xd820216c
#define ixTMON1_RDIR12_DATA 0xd8202170
#define ixTMON1_RDIR13_DATA 0xd8202174
#define ixTMON1_RDIR14_DATA 0xd8202178
#define ixTMON1_RDIR15_DATA 0xd820217c
#define ixTMON1_INT_DATA 0xd8202180
#define ixTMON1_RDIL_PRESENT0 0xd8202184
#define ixTMON1_RDIL_PRESENT1 0xd8202188
#define ixTMON1_RDIR_PRESENT0 0xd820218c
#define ixTMON1_RDIR_PRESENT1 0xd8202190
#define ixTMON1_CONFIG 0xd8202198
#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0
#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4
#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8
#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac
#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0
#define ixTMON1_DEBUG0 0xd82021b4
#define ixTMON1_DEBUG1 0xd82021b8
#define ixTHM_TMON0_REMOTE_START 0xd8202800
#define ixTHM_TMON0_REMOTE_END 0xd82028fc
#define ixTHM_TMON1_REMOTE_START 0xd8202900
#define ixTHM_TMON1_REMOTE_END 0xd82029fc
#define ixTHM_TCON_LOCAL0 0xd8202e00
#define ixTHM_TCON_LOCAL1 0xd8202e04
#define ixTHM_TCON_LOCAL2 0xd8202e08
#define ixTHM_TCON_LOCAL3 0xd8202e0c
#define ixTHM_TCON_LOCAL4 0xd8202e10
#define ixTHM_TCON_LOCAL5 0xd8202e14
#define ixTHM_TCON_LOCAL6 0xd8202e18
#define ixTHM_TCON_LOCAL7 0xd8202e1c
#define ixTHM_TCON_LOCAL8 0xd8202e20
#define ixTHM_TCON_LOCAL9 0xd8202e24
#define ixTHM_TCON_LOCAL10 0xd8202e28
#define ixTHM_TCON_LOCAL11 0xd8202e2c
#define ixTHM_TCON_LOCAL12 0xd8202e30
#define ixTHM_TCON_LOCAL13 0xd8202ef8
#define ixTHM_TCON_LOCAL14 0xd8202efc
#define ixTHM_FUSE0 0xd8210000
#define ixTHM_FUSE1 0xd8210004
#define ixTHM_FUSE2 0xd8210008
#define ixTHM_FUSE3 0xd821000c
#define ixTHM_FUSE4 0xd8210010
#define ixTHM_FUSE5 0xd8210014
#define ixTHM_FUSE6 0xd8210018
#define ixTHM_FUSE7 0xd821001c
#define ixTHM_FUSE8 0xd8210020
#define ixTHM_FUSE9 0xd8210024
#define ixTHM_FUSE10 0xd8210028
#define ixTHM_FUSE11 0xd821002c
#define ixTHM_FUSE12 0xd8210030
#define mmMP0PUB_IND_INDEX 0x180
#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180
#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182
#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184
#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186
#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188
#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a
#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c
#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e
#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190
#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192
#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194
#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196
#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198
#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a
#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c
#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e
#define mmMP0PUB_IND_DATA 0x181
#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181
#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183
#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185
#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187
#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189
#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b
#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d
#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f
#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191
#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193
#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195
#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197
#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199
#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b
#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d
#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f
#define mmMP0PUB_IND_INDEX_0 0x180
#define mmMP0PUB_IND_DATA_0 0x181
#define mmMP0PUB_IND_INDEX_1 0x182
#define mmMP0PUB_IND_DATA_1 0x183
#define mmMP0PUB_IND_INDEX_2 0x184
#define mmMP0PUB_IND_DATA_2 0x185
#define mmMP0PUB_IND_INDEX_3 0x186
#define mmMP0PUB_IND_DATA_3 0x187
#define mmMP0PUB_IND_INDEX_4 0x188
#define mmMP0PUB_IND_DATA_4 0x189
#define mmMP0PUB_IND_INDEX_5 0x18a
#define mmMP0PUB_IND_DATA_5 0x18b
#define mmMP0PUB_IND_INDEX_6 0x18c
#define mmMP0PUB_IND_DATA_6 0x18d
#define mmMP0PUB_IND_INDEX_7 0x18e
#define mmMP0PUB_IND_DATA_7 0x18f
#define mmMP0PUB_IND_INDEX_8 0x190
#define mmMP0PUB_IND_DATA_8 0x191
#define mmMP0PUB_IND_INDEX_9 0x192
#define mmMP0PUB_IND_DATA_9 0x193
#define mmMP0PUB_IND_INDEX_10 0x194
#define mmMP0PUB_IND_DATA_10 0x195
#define mmMP0PUB_IND_INDEX_11 0x196
#define mmMP0PUB_IND_DATA_11 0x197
#define mmMP0PUB_IND_INDEX_12 0x198
#define mmMP0PUB_IND_DATA_12 0x199
#define mmMP0PUB_IND_INDEX_13 0x19a
#define mmMP0PUB_IND_DATA_13 0x19b
#define mmMP0PUB_IND_INDEX_14 0x19c
#define mmMP0PUB_IND_DATA_14 0x19d
#define mmMP0PUB_IND_INDEX_15 0x19e
#define mmMP0PUB_IND_DATA_15 0x19f
#define mmMP0_IND_ACCESS_CNTL 0x1a0
#define mmMP0_MSP_MESSAGE_0 0x1a1
#define mmMP0_MSP_MESSAGE_1 0x1a2
#define mmMP0_MSP_MESSAGE_2 0x1a3
#define mmMP0_MSP_MESSAGE_3 0x1a4
#define mmMP0_MSP_MESSAGE_4 0x1a5
#define mmMP0_MSP_MESSAGE_5 0x1a6
#define mmMP0_MSP_MESSAGE_6 0x1a7
#define mmMP0_MSP_MESSAGE_7 0x1a8
#define mmSAM_IH_EXT_ERR_INTR 0x1a9
#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa
#define mmMP0_DISP_TIMER0_CTRL0 0x1ab
#define mmMP0_DISP_TIMER0_CTRL1 0x1ac
#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad
#define mmMP0_DISP_TIMER0_INTEN 0x1ae
#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af
#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0
#define mmMP0_DISP_TIMER0_CNT 0x1b1
#define mmMP0_DISP_TIMER1_CTRL0 0x1b2
#define mmMP0_DISP_TIMER1_CTRL1 0x1b3
#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4
#define mmMP0_DISP_TIMER1_INTEN 0x1b5
#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6
#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7
#define mmMP0_DISP_TIMER1_CNT 0x1b8
#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0
#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1
#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2
#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3
#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4
#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5
#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6
#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7
#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8
#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9
#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca
#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb
#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc
#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd
#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce
#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf
#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0
#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1
#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2
#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3
#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4
#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5
#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6
#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7
#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8
#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9
#define mmSMU_MP1_SRBM2P_RESP_10 0x1da
#define mmSMU_MP1_SRBM2P_RESP_11 0x1db
#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc
#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd
#define mmSMU_MP1_SRBM2P_RESP_14 0x1de
#define mmSMU_MP1_SRBM2P_RESP_15 0x1df
#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0
#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1
#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2
#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3
#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4
#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5
#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6
#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7
#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8
#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9
#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea
#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb
#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec
#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed
#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee
#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef
#define mmSMU_MP1_ACP2MP_RESP 0x1f0
#define mmSMU_MP1_DC2MP_RESP 0x1f1
#define mmSMU_MP1_UVD2MP_RESP 0x1f2
#define mmSMU_MP1_VCE2MP_RESP 0x1f3
#define mmSMU_MP1_RLC2MP_RESP 0x1f4
#define mmMP_FPS_CNT 0x1f5
#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6
#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7
#define mmSMU_SRBM_CONFIG 0x1f8
#define ixMP_FPS_CNT_XBAR 0xcf200800
#define ixMP_SRBM_CONFIG_XBAR 0xcf200804
#define ixMP_SRBM_CONTROL 0xcf200c00
#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04
#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08
#define ixMP_CRBBM_CONTROL 0xcf200c0c
#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10
#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14
#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000
#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004
#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008
#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c
#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010
#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014
#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018
#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c
#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020
#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024
#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028
#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c
#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030
#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038
#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c
#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040
#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044
#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048
#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c
#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050
#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054
#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058
#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c
#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060
#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064
#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068
#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c
#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070
#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074
#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078
#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c
#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080
#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084
#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088
#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c
#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090
#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094
#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098
#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c
#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0
#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4
#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8
#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac
#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0
#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4
#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8
#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc
#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0
#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4
#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8
#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc
#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0
#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4
#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8
#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc
#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0
#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4
#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8
#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec
#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0
#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4
#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8
#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc
#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100
#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104
#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108
#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c
#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110
#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114
#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118
#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c
#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120
#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124
#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128
#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c
#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130
#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134
#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138
#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c
#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140
#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144
#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148
#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c
#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150
#define ixMP_IOC_CTRL 0xcf100000
#define ixMP_IOC_RDDATA 0xcf100004
#define ixMP_IOC_PHASE1 0xcf100008
#define ixMP_IOC_PHASE2 0xcf10000c
#define ixMP_IOC_PHASE3 0xcf100010
#define ixMP_IOC_READ_0 0xcf100024
#define ixMP_IOC_READ_1 0xcf100028
#define ixMP_IOC_READ_2 0xcf10002c
#define ixMP_IOC_READ_3 0xcf100030
#define ixMP_IOC_READ_4 0xcf100034
#define ixMP_IOC_READ_5 0xcf100038
#define ixMP_IOC_READ_6 0xcf10003c
#define ixMP_IOC_READ_7 0xcf100040
#define ixMP_IOC_READ_8 0xcf100044
#define ixMP_IOC_READ_9 0xcf100048
#define ixMP_IOC_READ_10 0xcf10004c
#define ixMP_IOC_READ_11 0xcf100050
#define ixMP_IOC_READ_12 0xcf100054
#define ixMP_IOC_READ_13 0xcf100058
#define ixMP_IOC_READ_14 0xcf10005c
#define ixMP_IOC_READ_15 0xcf100060
#define ixMP_IOC_WRITE_0 0xcf100064
#define ixMP_IOC_WRITE_1 0xcf100068
#define ixMP_IOC_WRITE_2 0xcf10006c
#define ixMP_IOC_WRITE_3 0xcf100070
#define ixMP_IOC_WRITE_4 0xcf100074
#define ixMP_IOC_WRITE_5 0xcf100078
#define ixMP_IOC_WRITE_6 0xcf10007c
#define ixMP_IOC_WRITE_7 0xcf100080
#define ixMP_IOC_WRITE_8 0xcf100084
#define ixMP_IOC_WRITE_9 0xcf100088
#define ixMP_IOC_WRITE_10 0xcf10008c
#define ixMP_IOC_WRITE_11 0xcf100090
#define ixMP_IOC_WRITE_12 0xcf100094
#define ixMP_IOC_WRITE_13 0xcf100098
#define ixMP_IOC_WRITE_14 0xcf10009c
#define ixMP_IOC_WRITE_15 0xcf1000a0
#define ixMP_INTERRUPT_CONTROL 0xcf200400
#define ixMP0_SW_INT 0xcf200404
#define ixMP0_SW_INT_CTXID 0xcf200408
#define ixMP1_SW_INT 0xcf20040c
#define ixMP1_SW_INT_CTXID 0xcf200410
#define ixDISP_TIMER_ID 0xcf200414
#define mmPWRHW_SMC_IND_INDEX 0x180
#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180
#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182
#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184
#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186
#define mmPWRHW_SMC_IND_DATA 0x181
#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181
#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183
#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185
#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187
#define ixCURRENT_STATE_CPU0 0xd0210000
#define ixCURRENT_STATE_CPU1 0xd0210010
#define ixCPU_REDUN_DONE0 0xd0210004
#define ixCPU_REDUN_DONE1 0xd0210014
#define ixCURRENT_VID_CPU0 0xd0210008
#define ixCURRENT_VID_CPU1 0xd0210018
#define ixUNBPM_PWRMGT_ACK 0xd0211000
#define ixCURRENT_FREQ_STATE_NB 0xd0211004
#define ixCURRENT_PSTATE_NB 0xd0211008
#define ixUNBPM_MSG_INT_CONFIG 0xd021100c
#define ixUNBPM_NBPWRMGT_CMD 0xd0211010
#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014
#define ixDDR0_FUSE_SSB_XFER 0xd0211018
#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c
#define ixDDR1_FUSE_SSB_XFER 0xd0211020
#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024
#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028
#define ixSYNFIFO_CLK_RATIO 0xd021102c
#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030
#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034
#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038
#define ixMISC_GNB_PWRMGT_DATA 0xd021103c
#define ixGN_GNB_SLOW 0xd0211040
#define ixGN_FORCE_NBPS1 0xd0211044
#define ixMISC_SMU_PWRMGT_DATA 0xd0211048
#define ixNB_COF 0xd021104c
#define ixUNBPM_CK_IRESET 0xd0211050
#define ixCURRENT_VID_NB 0xd0211054
#define ixSPR_FUSE_PSTATEPWR1 0xd0211058
#define ixSPR_FUSE_PSTATEPWR2 0xd021105c
#define ixSPR_FUSE_PSTATEPWR3 0xd0211060
#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064
#define ixSPR_PRODUCT_INFO0 0xd0211068
#define ixSPR_SERIALNUM_REG1 0xd021106c
#define ixSPR_SERIALNUM_REG2 0xd0211070
#define ixSPR_PRODUCT_INFO1 0xd0211074
#define ixSPR_EXT_PRODUCT_INFO 0xd021107c
#define ixSPR_MSIDFUSE 0xd0211080
#define ixSPR_LINK_PRODUCT_INFO 0xd0211084
#define ixSPR_BRAND_NAME_ADDR 0xd0211088
#define ixSPR_BRAND_NAME_DATA 0xd021108c
#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090
#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094
#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098
#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c
#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0
#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4
#define ixNUM_BOOST_STATES 0xd02110a8
#define ixWARM_RESET_NB_CONTROL 0xd02110ac
#define ixONION_NO_STREAMS_PEND 0xd02110b0
#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4
#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8
#define ixUNBPM_PWRCTRL_MISC 0xd02110bc
#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0
#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4
#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8
#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc
#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0
#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4
#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8
#define ixUNBPM_SCRATCH_0 0xd021e000
#define ixUNBPM_SCRATCH_1 0xd021e004
#define ixPOWERON_CPU_0 0xd0220000
#define ixPOWERREADY_CPU_0 0xd0220004
#define ixPGRUNFEEDBACK_CPU_0 0xd0220008
#define ixRCC3ON_CPU_0 0xd022000c
#define ixRCC3EXITDONE_CPU_0 0xd0220010
#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014
#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018
#define ixCORE_REDUN_SSB_XFER_0 0xd022001c
#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020
#define ixCORE_APM_SSB_XFER_0 0xd0220024
#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028
#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c
#define ixLDOIVRON_CPU_0 0xd0220030
#define ixLDOIVREXITDONE_CPU_0 0xd0220034
#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038
#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c
#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044
#define ixCK_DISABLECORE_CPU_0 0xd0220048
#define ixCOREPM_ID_0 0xd022004c
#define ixCOREPM_SCRATCH_0 0xd0220050
#define ixRCC3_WAKEMIN_CPU_0 0xd0220054
#define ixSPMI_CONFIG0_0 0xd0221000
#define ixSPMI_CONFIG1_0 0xd0221004
#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008
#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c
#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010
#define ixSPMI_FSM_BUSY_0 0xd0221014
#define ixSPMI_PATH_0 0xd0221018
#define ixSPMI_C6_STATE_0 0xd022101c
#define ixSPMI_JTAG_OVER_0 0xd0221020
#define ixSPMI_SRAM_ADDRESS_0 0xd0221024
#define ixSPMI_SRAM_DATA_0 0xd0221028
#define ixSPMI_RESET_0 0xd022102c
#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030
#define ixSPMI_SPARE_0 0xd0221034
#define ixSPMI_SPARE_EX_0 0xd0221038
#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c
#define ixPOWERON_CPU_1 0xd0230000
#define ixPOWERREADY_CPU_1 0xd0230004
#define ixPGRUNFEEDBACK_CPU_1 0xd0230008
#define ixRCC3ON_CPU_1 0xd023000c
#define ixRCC3EXITDONE_CPU_1 0xd0230010
#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014
#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018
#define ixCORE_REDUN_SSB_XFER_1 0xd023001c
#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020
#define ixCORE_APM_SSB_XFER_1 0xd0230024
#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028
#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c
#define ixLDOIVRON_CPU_1 0xd0230030
#define ixLDOIVREXITDONE_CPU_1 0xd0230034
#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038
#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c
#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044
#define ixCK_DISABLECORE_CPU_1 0xd0230048
#define ixCOREPM_ID_1 0xd023004c
#define ixCOREPM_SCRATCH_1 0xd0230050
#define ixRCC3_WAKEMIN_CPU_1 0xd0230054
#define ixSPMI_CONFIG0_1 0xd0231000
#define ixSPMI_CONFIG1_1 0xd0231004
#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008
#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c
#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010
#define ixSPMI_FSM_BUSY_1 0xd0231014
#define ixSPMI_PATH_1 0xd0231018
#define ixSPMI_C6_STATE_1 0xd023101c
#define ixSPMI_JTAG_OVER_1 0xd0231020
#define ixSPMI_SRAM_ADDRESS_1 0xd0231024
#define ixSPMI_SRAM_DATA_1 0xd0231028
#define ixSPMI_RESET_1 0xd023102c
#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030
#define ixSPMI_SPARE_1 0xd0231034
#define ixSPMI_SPARE_EX_1 0xd0231038
#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c
#define ixGENERAL_PWRMGT 0xd0200000
#define ixCNB_PWRMGT_CNTL 0xd0200004
#define ixSCLK_PWRMGT_CNTL 0xd0200008
#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0
#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4
#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8
#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac
#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0
#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4
#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8
#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc
#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0
#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4
#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044
#define ixCG_ACPI_CNTL 0xd0200064
#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080
#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084
#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c
#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088
#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c
#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310
#define ixSMU_VOLTAGE_STATUS 0xd0200094
#define ixCG_ULV_PARAMETER 0xd020015c
#define ixPWR_DC_RESP 0xd0200300
#define ixPWR_VCE_RESP 0xd0200304
#define ixPWR_UVD_RESP 0xd0200308
#define ixPWR_ACP_RESP 0xd020030c
#define ixPWR_DC_REQ 0xd020031c
#define ixSCLK_MIN_DIV 0xd02003ac
#define ixPCIE_PGFSM_CONFIG 0xd02002d0
#define ixPCIE_PGFSM_WRITE 0xd02002d4
#define ixSERDES_BUSY 0xd02002d8
#define ixPCIE_PGFSM2_CONFIG 0xd02002dc
#define ixPCIE_PGFSM2_WRITE 0xd02002e0
#define ixSERDES2_BUSY 0xd02002e4
#define ixPCIE_PGFSM_0_READ 0xd02002e8
#define ixPCIE_PGFSM_1_READ 0xd02002ec
#define ixPWR_ACPI_INTERRUPT 0xd0200318
#define ixVDDGFX_IDLE_PARAMETER 0xd020036c
#define ixVDDGFX_IDLE_CONTROL 0xd0200370
#define ixVDDGFX_IDLE_EXIT 0xd0200374
#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378
#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c
#define ixLCAC_MC0_CNTL 0xd0208130
#define ixLCAC_MC0_OVR_SEL 0xd0208134
#define ixLCAC_MC0_OVR_VAL 0xd0208138
#define ixLCAC_MC1_CNTL 0xd020813c
#define ixLCAC_MC1_OVR_SEL 0xd0208140
#define ixLCAC_MC1_OVR_VAL 0xd0208144
#define ixLCAC_MC2_CNTL 0xd0208148
#define ixLCAC_MC2_OVR_SEL 0xd020814c
#define ixLCAC_MC2_OVR_VAL 0xd0208150
#define ixLCAC_MC3_CNTL 0xd0208154
#define ixLCAC_MC3_OVR_SEL 0xd0208158
#define ixLCAC_MC3_OVR_VAL 0xd020815c
#define ixLCAC_CPL_CNTL 0xd0208160
#define ixLCAC_CPL_OVR_SEL 0xd0208164
#define ixLCAC_CPL_OVR_VAL 0xd0208168
#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000
#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004
#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c
#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010
#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014
#define ixSOUTHBRIDGE_TYPE 0xd020c01c
#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020
#define ixALLOW_SR_INTR_CTRL 0xd020c024
#define mmGC_CAC_LKG_AGGR_LOWER 0x3294
#define mmGC_CAC_LKG_AGGR_UPPER 0x3295
#define ixGC_CAC_WEIGHT_CU_0 0x32
#define ixGC_CAC_WEIGHT_CU_1 0x33
#define ixGC_CAC_WEIGHT_CU_2 0x34
#define ixGC_CAC_WEIGHT_CU_3 0x35
#define ixGC_CAC_ACC_CU0 0xba
#define ixGC_CAC_ACC_CU1 0xbb
#define ixGC_CAC_ACC_CU2 0xbc
#define ixGC_CAC_ACC_CU3 0xbd
#define ixGC_CAC_ACC_CU4 0xbe
#define ixGC_CAC_ACC_CU5 0xbf
#define ixGC_CAC_ACC_CU6 0xc0
#define ixGC_CAC_ACC_CU7 0xc1
#define ixGC_CAC_OVRD_CU 0xe7
#endif /* SMU_8_0_D_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_enum.h 0 → 100644
View file @ 47e68987
/*
* SMU_8_0 Register documentation
*
* Copyright (C) 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef SMU_8_0_ENUM_H
#define SMU_8_0_ENUM_H
typedef enum DebugBlockId {
DBG_BLOCK_ID_RESERVED = 0x0,
DBG_BLOCK_ID_DBG = 0x1,
DBG_BLOCK_ID_VMC = 0x2,
DBG_BLOCK_ID_PDMA = 0x3,
DBG_BLOCK_ID_CG = 0x4,
DBG_BLOCK_ID_SRBM = 0x5,
DBG_BLOCK_ID_GRBM = 0x6,
DBG_BLOCK_ID_RLC = 0x7,
DBG_BLOCK_ID_CSC = 0x8,
DBG_BLOCK_ID_SEM = 0x9,
DBG_BLOCK_ID_IH = 0xa,
DBG_BLOCK_ID_SC = 0xb,
DBG_BLOCK_ID_SQ = 0xc,
DBG_BLOCK_ID_UVDU = 0xd,
DBG_BLOCK_ID_SQA = 0xe,
DBG_BLOCK_ID_SDMA0 = 0xf,
DBG_BLOCK_ID_SDMA1 = 0x10,
DBG_BLOCK_ID_SPIM = 0x11,
DBG_BLOCK_ID_GDS = 0x12,
DBG_BLOCK_ID_VC0 = 0x13,
DBG_BLOCK_ID_VC1 = 0x14,
DBG_BLOCK_ID_PA0 = 0x15,
DBG_BLOCK_ID_PA1 = 0x16,
DBG_BLOCK_ID_CP0 = 0x17,
DBG_BLOCK_ID_CP1 = 0x18,
DBG_BLOCK_ID_CP2 = 0x19,
DBG_BLOCK_ID_XBR = 0x1a,
DBG_BLOCK_ID_UVDM = 0x1b,
DBG_BLOCK_ID_VGT0 = 0x1c,
DBG_BLOCK_ID_VGT1 = 0x1d,
DBG_BLOCK_ID_IA = 0x1e,
DBG_BLOCK_ID_SXM0 = 0x1f,
DBG_BLOCK_ID_SXM1 = 0x20,
DBG_BLOCK_ID_SCT0 = 0x21,
DBG_BLOCK_ID_SCT1 = 0x22,
DBG_BLOCK_ID_SPM0 = 0x23,
DBG_BLOCK_ID_SPM1 = 0x24,
DBG_BLOCK_ID_UNUSED0 = 0x25,
DBG_BLOCK_ID_UNUSED1 = 0x26,
DBG_BLOCK_ID_TCAA = 0x27,
DBG_BLOCK_ID_TCAB = 0x28,
DBG_BLOCK_ID_TCCA = 0x29,
DBG_BLOCK_ID_TCCB = 0x2a,
DBG_BLOCK_ID_MCC0 = 0x2b,
DBG_BLOCK_ID_MCC1 = 0x2c,
DBG_BLOCK_ID_MCC2 = 0x2d,
DBG_BLOCK_ID_MCC3 = 0x2e,
DBG_BLOCK_ID_SXS0 = 0x2f,
DBG_BLOCK_ID_SXS1 = 0x30,
DBG_BLOCK_ID_SXS2 = 0x31,
DBG_BLOCK_ID_SXS3 = 0x32,
DBG_BLOCK_ID_SXS4 = 0x33,
DBG_BLOCK_ID_SXS5 = 0x34,
DBG_BLOCK_ID_SXS6 = 0x35,
DBG_BLOCK_ID_SXS7 = 0x36,
DBG_BLOCK_ID_SXS8 = 0x37,
DBG_BLOCK_ID_SXS9 = 0x38,
DBG_BLOCK_ID_BCI0 = 0x39,
DBG_BLOCK_ID_BCI1 = 0x3a,
DBG_BLOCK_ID_BCI2 = 0x3b,
DBG_BLOCK_ID_BCI3 = 0x3c,
DBG_BLOCK_ID_MCB = 0x3d,
DBG_BLOCK_ID_UNUSED6 = 0x3e,
DBG_BLOCK_ID_SQA00 = 0x3f,
DBG_BLOCK_ID_SQA01 = 0x40,
DBG_BLOCK_ID_SQA02 = 0x41,
DBG_BLOCK_ID_SQA10 = 0x42,
DBG_BLOCK_ID_SQA11 = 0x43,
DBG_BLOCK_ID_SQA12 = 0x44,
DBG_BLOCK_ID_UNUSED7 = 0x45,
DBG_BLOCK_ID_UNUSED8 = 0x46,
DBG_BLOCK_ID_SQB00 = 0x47,
DBG_BLOCK_ID_SQB01 = 0x48,
DBG_BLOCK_ID_SQB10 = 0x49,
DBG_BLOCK_ID_SQB11 = 0x4a,
DBG_BLOCK_ID_SQ00 = 0x4b,
DBG_BLOCK_ID_SQ01 = 0x4c,
DBG_BLOCK_ID_SQ10 = 0x4d,
DBG_BLOCK_ID_SQ11 = 0x4e,
DBG_BLOCK_ID_CB00 = 0x4f,
DBG_BLOCK_ID_CB01 = 0x50,
DBG_BLOCK_ID_CB02 = 0x51,
DBG_BLOCK_ID_CB03 = 0x52,
DBG_BLOCK_ID_CB04 = 0x53,
DBG_BLOCK_ID_UNUSED9 = 0x54,
DBG_BLOCK_ID_UNUSED10 = 0x55,
DBG_BLOCK_ID_UNUSED11 = 0x56,
DBG_BLOCK_ID_CB10 = 0x57,
DBG_BLOCK_ID_CB11 = 0x58,
DBG_BLOCK_ID_CB12 = 0x59,
DBG_BLOCK_ID_CB13 = 0x5a,
DBG_BLOCK_ID_CB14 = 0x5b,
DBG_BLOCK_ID_UNUSED12 = 0x5c,
DBG_BLOCK_ID_UNUSED13 = 0x5d,
DBG_BLOCK_ID_UNUSED14 = 0x5e,
DBG_BLOCK_ID_TCP0 = 0x5f,
DBG_BLOCK_ID_TCP1 = 0x60,
DBG_BLOCK_ID_TCP2 = 0x61,
DBG_BLOCK_ID_TCP3 = 0x62,
DBG_BLOCK_ID_TCP4 = 0x63,
DBG_BLOCK_ID_TCP5 = 0x64,
DBG_BLOCK_ID_TCP6 = 0x65,
DBG_BLOCK_ID_TCP7 = 0x66,
DBG_BLOCK_ID_TCP8 = 0x67,
DBG_BLOCK_ID_TCP9 = 0x68,
DBG_BLOCK_ID_TCP10 = 0x69,
DBG_BLOCK_ID_TCP11 = 0x6a,
DBG_BLOCK_ID_TCP12 = 0x6b,
DBG_BLOCK_ID_TCP13 = 0x6c,
DBG_BLOCK_ID_TCP14 = 0x6d,
DBG_BLOCK_ID_TCP15 = 0x6e,
DBG_BLOCK_ID_TCP16 = 0x6f,
DBG_BLOCK_ID_TCP17 = 0x70,
DBG_BLOCK_ID_TCP18 = 0x71,
DBG_BLOCK_ID_TCP19 = 0x72,
DBG_BLOCK_ID_TCP20 = 0x73,
DBG_BLOCK_ID_TCP21 = 0x74,
DBG_BLOCK_ID_TCP22 = 0x75,
DBG_BLOCK_ID_TCP23 = 0x76,
DBG_BLOCK_ID_TCP_RESERVED0 = 0x77,
DBG_BLOCK_ID_TCP_RESERVED1 = 0x78,
DBG_BLOCK_ID_TCP_RESERVED2 = 0x79,
DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a,
DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b,
DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c,
DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d,
DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e,
DBG_BLOCK_ID_DB00 = 0x7f,
DBG_BLOCK_ID_DB01 = 0x80,
DBG_BLOCK_ID_DB02 = 0x81,
DBG_BLOCK_ID_DB03 = 0x82,
DBG_BLOCK_ID_DB04 = 0x83,
DBG_BLOCK_ID_UNUSED15 = 0x84,
DBG_BLOCK_ID_UNUSED16 = 0x85,
DBG_BLOCK_ID_UNUSED17 = 0x86,
DBG_BLOCK_ID_DB10 = 0x87,
DBG_BLOCK_ID_DB11 = 0x88,
DBG_BLOCK_ID_DB12 = 0x89,
DBG_BLOCK_ID_DB13 = 0x8a,
DBG_BLOCK_ID_DB14 = 0x8b,
DBG_BLOCK_ID_UNUSED18 = 0x8c,
DBG_BLOCK_ID_UNUSED19 = 0x8d,
DBG_BLOCK_ID_UNUSED20 = 0x8e,
DBG_BLOCK_ID_TCC0 = 0x8f,
DBG_BLOCK_ID_TCC1 = 0x90,
DBG_BLOCK_ID_TCC2 = 0x91,
DBG_BLOCK_ID_TCC3 = 0x92,
DBG_BLOCK_ID_TCC4 = 0x93,
DBG_BLOCK_ID_TCC5 = 0x94,
DBG_BLOCK_ID_TCC6 = 0x95,
DBG_BLOCK_ID_TCC7 = 0x96,
DBG_BLOCK_ID_SPS00 = 0x97,
DBG_BLOCK_ID_SPS01 = 0x98,
DBG_BLOCK_ID_SPS02 = 0x99,
DBG_BLOCK_ID_SPS10 = 0x9a,
DBG_BLOCK_ID_SPS11 = 0x9b,
DBG_BLOCK_ID_SPS12 = 0x9c,
DBG_BLOCK_ID_UNUSED21 = 0x9d,
DBG_BLOCK_ID_UNUSED22 = 0x9e,
DBG_BLOCK_ID_TA00 = 0x9f,
DBG_BLOCK_ID_TA01 = 0xa0,
DBG_BLOCK_ID_TA02 = 0xa1,
DBG_BLOCK_ID_TA03 = 0xa2,
DBG_BLOCK_ID_TA04 = 0xa3,
DBG_BLOCK_ID_TA05 = 0xa4,
DBG_BLOCK_ID_TA06 = 0xa5,
DBG_BLOCK_ID_TA07 = 0xa6,
DBG_BLOCK_ID_TA08 = 0xa7,
DBG_BLOCK_ID_TA09 = 0xa8,
DBG_BLOCK_ID_TA0A = 0xa9,
DBG_BLOCK_ID_TA0B = 0xaa,
DBG_BLOCK_ID_UNUSED23 = 0xab,
DBG_BLOCK_ID_UNUSED24 = 0xac,
DBG_BLOCK_ID_UNUSED25 = 0xad,
DBG_BLOCK_ID_UNUSED26 = 0xae,
DBG_BLOCK_ID_TA10 = 0xaf,
DBG_BLOCK_ID_TA11 = 0xb0,
DBG_BLOCK_ID_TA12 = 0xb1,
DBG_BLOCK_ID_TA13 = 0xb2,
DBG_BLOCK_ID_TA14 = 0xb3,
DBG_BLOCK_ID_TA15 = 0xb4,
DBG_BLOCK_ID_TA16 = 0xb5,
DBG_BLOCK_ID_TA17 = 0xb6,
DBG_BLOCK_ID_TA18 = 0xb7,
DBG_BLOCK_ID_TA19 = 0xb8,
DBG_BLOCK_ID_TA1A = 0xb9,
DBG_BLOCK_ID_TA1B = 0xba,
DBG_BLOCK_ID_UNUSED27 = 0xbb,
DBG_BLOCK_ID_UNUSED28 = 0xbc,
DBG_BLOCK_ID_UNUSED29 = 0xbd,
DBG_BLOCK_ID_UNUSED30 = 0xbe,
DBG_BLOCK_ID_TD00 = 0xbf,
DBG_BLOCK_ID_TD01 = 0xc0,
DBG_BLOCK_ID_TD02 = 0xc1,
DBG_BLOCK_ID_TD03 = 0xc2,
DBG_BLOCK_ID_TD04 = 0xc3,
DBG_BLOCK_ID_TD05 = 0xc4,
DBG_BLOCK_ID_TD06 = 0xc5,
DBG_BLOCK_ID_TD07 = 0xc6,
DBG_BLOCK_ID_TD08 = 0xc7,
DBG_BLOCK_ID_TD09 = 0xc8,
DBG_BLOCK_ID_TD0A = 0xc9,
DBG_BLOCK_ID_TD0B = 0xca,
DBG_BLOCK_ID_UNUSED31 = 0xcb,
DBG_BLOCK_ID_UNUSED32 = 0xcc,
DBG_BLOCK_ID_UNUSED33 = 0xcd,
DBG_BLOCK_ID_UNUSED34 = 0xce,
DBG_BLOCK_ID_TD10 = 0xcf,
DBG_BLOCK_ID_TD11 = 0xd0,
DBG_BLOCK_ID_TD12 = 0xd1,
DBG_BLOCK_ID_TD13 = 0xd2,
DBG_BLOCK_ID_TD14 = 0xd3,
DBG_BLOCK_ID_TD15 = 0xd4,
DBG_BLOCK_ID_TD16 = 0xd5,
DBG_BLOCK_ID_TD17 = 0xd6,
DBG_BLOCK_ID_TD18 = 0xd7,
DBG_BLOCK_ID_TD19 = 0xd8,
DBG_BLOCK_ID_TD1A = 0xd9,
DBG_BLOCK_ID_TD1B = 0xda,
DBG_BLOCK_ID_UNUSED35 = 0xdb,
DBG_BLOCK_ID_UNUSED36 = 0xdc,
DBG_BLOCK_ID_UNUSED37 = 0xdd,
DBG_BLOCK_ID_UNUSED38 = 0xde,
DBG_BLOCK_ID_LDS00 = 0xdf,
DBG_BLOCK_ID_LDS01 = 0xe0,
DBG_BLOCK_ID_LDS02 = 0xe1,
DBG_BLOCK_ID_LDS03 = 0xe2,
DBG_BLOCK_ID_LDS04 = 0xe3,
DBG_BLOCK_ID_LDS05 = 0xe4,
DBG_BLOCK_ID_LDS06 = 0xe5,
DBG_BLOCK_ID_LDS07 = 0xe6,
DBG_BLOCK_ID_LDS08 = 0xe7,
DBG_BLOCK_ID_LDS09 = 0xe8,
DBG_BLOCK_ID_LDS0A = 0xe9,
DBG_BLOCK_ID_LDS0B = 0xea,
DBG_BLOCK_ID_UNUSED39 = 0xeb,
DBG_BLOCK_ID_UNUSED40 = 0xec,
DBG_BLOCK_ID_UNUSED41 = 0xed,
DBG_BLOCK_ID_UNUSED42 = 0xee,
DBG_BLOCK_ID_LDS10 = 0xef,
DBG_BLOCK_ID_LDS11 = 0xf0,
DBG_BLOCK_ID_LDS12 = 0xf1,
DBG_BLOCK_ID_LDS13 = 0xf2,
DBG_BLOCK_ID_LDS14 = 0xf3,
DBG_BLOCK_ID_LDS15 = 0xf4,
DBG_BLOCK_ID_LDS16 = 0xf5,
DBG_BLOCK_ID_LDS17 = 0xf6,
DBG_BLOCK_ID_LDS18 = 0xf7,
DBG_BLOCK_ID_LDS19 = 0xf8,
DBG_BLOCK_ID_LDS1A = 0xf9,
DBG_BLOCK_ID_LDS1B = 0xfa,
DBG_BLOCK_ID_UNUSED43 = 0xfb,
DBG_BLOCK_ID_UNUSED44 = 0xfc,
DBG_BLOCK_ID_UNUSED45 = 0xfd,
DBG_BLOCK_ID_UNUSED46 = 0xfe,
} DebugBlockId;
typedef enum DebugBlockId_BY2 {
DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
DBG_BLOCK_ID_VMC_BY2 = 0x1,
DBG_BLOCK_ID_UNUSED0_BY2 = 0x2,
DBG_BLOCK_ID_GRBM_BY2 = 0x3,
DBG_BLOCK_ID_CSC_BY2 = 0x4,
DBG_BLOCK_ID_IH_BY2 = 0x5,
DBG_BLOCK_ID_SQ_BY2 = 0x6,
DBG_BLOCK_ID_UVD_BY2 = 0x7,
DBG_BLOCK_ID_SDMA0_BY2 = 0x8,
DBG_BLOCK_ID_SPIM_BY2 = 0x9,
DBG_BLOCK_ID_VC0_BY2 = 0xa,
DBG_BLOCK_ID_PA_BY2 = 0xb,
DBG_BLOCK_ID_CP0_BY2 = 0xc,
DBG_BLOCK_ID_CP2_BY2 = 0xd,
DBG_BLOCK_ID_PC0_BY2 = 0xe,
DBG_BLOCK_ID_BCI0_BY2 = 0xf,
DBG_BLOCK_ID_SXM0_BY2 = 0x10,
DBG_BLOCK_ID_SCT0_BY2 = 0x11,
DBG_BLOCK_ID_SPM0_BY2 = 0x12,
DBG_BLOCK_ID_BCI2_BY2 = 0x13,
DBG_BLOCK_ID_TCA_BY2 = 0x14,
DBG_BLOCK_ID_TCCA_BY2 = 0x15,
DBG_BLOCK_ID_MCC_BY2 = 0x16,
DBG_BLOCK_ID_MCC2_BY2 = 0x17,
DBG_BLOCK_ID_MCD_BY2 = 0x18,
DBG_BLOCK_ID_MCD2_BY2 = 0x19,
DBG_BLOCK_ID_MCD4_BY2 = 0x1a,
DBG_BLOCK_ID_MCB_BY2 = 0x1b,
DBG_BLOCK_ID_SQA_BY2 = 0x1c,
DBG_BLOCK_ID_SQA02_BY2 = 0x1d,
DBG_BLOCK_ID_SQA11_BY2 = 0x1e,
DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f,
DBG_BLOCK_ID_SQB_BY2 = 0x20,
DBG_BLOCK_ID_SQB10_BY2 = 0x21,
DBG_BLOCK_ID_UNUSED10_BY2 = 0x22,
DBG_BLOCK_ID_UNUSED12_BY2 = 0x23,
DBG_BLOCK_ID_CB_BY2 = 0x24,
DBG_BLOCK_ID_CB02_BY2 = 0x25,
DBG_BLOCK_ID_CB10_BY2 = 0x26,
DBG_BLOCK_ID_CB12_BY2 = 0x27,
DBG_BLOCK_ID_SXS_BY2 = 0x28,
DBG_BLOCK_ID_SXS2_BY2 = 0x29,
DBG_BLOCK_ID_SXS4_BY2 = 0x2a,
DBG_BLOCK_ID_SXS6_BY2 = 0x2b,
DBG_BLOCK_ID_DB_BY2 = 0x2c,
DBG_BLOCK_ID_DB02_BY2 = 0x2d,
DBG_BLOCK_ID_DB10_BY2 = 0x2e,
DBG_BLOCK_ID_DB12_BY2 = 0x2f,
DBG_BLOCK_ID_TCP_BY2 = 0x30,
DBG_BLOCK_ID_TCP2_BY2 = 0x31,
DBG_BLOCK_ID_TCP4_BY2 = 0x32,
DBG_BLOCK_ID_TCP6_BY2 = 0x33,
DBG_BLOCK_ID_TCP8_BY2 = 0x34,
DBG_BLOCK_ID_TCP10_BY2 = 0x35,
DBG_BLOCK_ID_TCP12_BY2 = 0x36,
DBG_BLOCK_ID_TCP14_BY2 = 0x37,
DBG_BLOCK_ID_TCP16_BY2 = 0x38,
DBG_BLOCK_ID_TCP18_BY2 = 0x39,
DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
DBG_BLOCK_ID_TCC_BY2 = 0x40,
DBG_BLOCK_ID_TCC2_BY2 = 0x41,
DBG_BLOCK_ID_TCC4_BY2 = 0x42,
DBG_BLOCK_ID_TCC6_BY2 = 0x43,
DBG_BLOCK_ID_SPS_BY2 = 0x44,
DBG_BLOCK_ID_SPS02_BY2 = 0x45,
DBG_BLOCK_ID_SPS11_BY2 = 0x46,
DBG_BLOCK_ID_UNUSED14_BY2 = 0x47,
DBG_BLOCK_ID_TA_BY2 = 0x48,
DBG_BLOCK_ID_TA02_BY2 = 0x49,
DBG_BLOCK_ID_TA04_BY2 = 0x4a,
DBG_BLOCK_ID_TA06_BY2 = 0x4b,
DBG_BLOCK_ID_TA08_BY2 = 0x4c,
DBG_BLOCK_ID_TA0A_BY2 = 0x4d,
DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e,
DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f,
DBG_BLOCK_ID_TA10_BY2 = 0x50,
DBG_BLOCK_ID_TA12_BY2 = 0x51,
DBG_BLOCK_ID_TA14_BY2 = 0x52,
DBG_BLOCK_ID_TA16_BY2 = 0x53,
DBG_BLOCK_ID_TA18_BY2 = 0x54,
DBG_BLOCK_ID_TA1A_BY2 = 0x55,
DBG_BLOCK_ID_UNUSED24_BY2 = 0x56,
DBG_BLOCK_ID_UNUSED26_BY2 = 0x57,
DBG_BLOCK_ID_TD_BY2 = 0x58,
DBG_BLOCK_ID_TD02_BY2 = 0x59,
DBG_BLOCK_ID_TD04_BY2 = 0x5a,
DBG_BLOCK_ID_TD06_BY2 = 0x5b,
DBG_BLOCK_ID_TD08_BY2 = 0x5c,
DBG_BLOCK_ID_TD0A_BY2 = 0x5d,
DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e,
DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f,
DBG_BLOCK_ID_TD10_BY2 = 0x60,
DBG_BLOCK_ID_TD12_BY2 = 0x61,
DBG_BLOCK_ID_TD14_BY2 = 0x62,
DBG_BLOCK_ID_TD16_BY2 = 0x63,
DBG_BLOCK_ID_TD18_BY2 = 0x64,
DBG_BLOCK_ID_TD1A_BY2 = 0x65,
DBG_BLOCK_ID_UNUSED32_BY2 = 0x66,
DBG_BLOCK_ID_UNUSED34_BY2 = 0x67,
DBG_BLOCK_ID_LDS_BY2 = 0x68,
DBG_BLOCK_ID_LDS02_BY2 = 0x69,
DBG_BLOCK_ID_LDS04_BY2 = 0x6a,
DBG_BLOCK_ID_LDS06_BY2 = 0x6b,
DBG_BLOCK_ID_LDS08_BY2 = 0x6c,
DBG_BLOCK_ID_LDS0A_BY2 = 0x6d,
DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e,
DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f,
DBG_BLOCK_ID_LDS10_BY2 = 0x70,
DBG_BLOCK_ID_LDS12_BY2 = 0x71,
DBG_BLOCK_ID_LDS14_BY2 = 0x72,
DBG_BLOCK_ID_LDS16_BY2 = 0x73,
DBG_BLOCK_ID_LDS18_BY2 = 0x74,
DBG_BLOCK_ID_LDS1A_BY2 = 0x75,
DBG_BLOCK_ID_UNUSED40_BY2 = 0x76,
DBG_BLOCK_ID_UNUSED42_BY2 = 0x77,
} DebugBlockId_BY2;
typedef enum DebugBlockId_BY4 {
DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
DBG_BLOCK_ID_UNUSED0_BY4 = 0x1,
DBG_BLOCK_ID_CSC_BY4 = 0x2,
DBG_BLOCK_ID_SQ_BY4 = 0x3,
DBG_BLOCK_ID_SDMA0_BY4 = 0x4,
DBG_BLOCK_ID_VC0_BY4 = 0x5,
DBG_BLOCK_ID_CP0_BY4 = 0x6,
DBG_BLOCK_ID_UNUSED1_BY4 = 0x7,
DBG_BLOCK_ID_SXM0_BY4 = 0x8,
DBG_BLOCK_ID_SPM0_BY4 = 0x9,
DBG_BLOCK_ID_TCAA_BY4 = 0xa,
DBG_BLOCK_ID_MCC_BY4 = 0xb,
DBG_BLOCK_ID_MCD_BY4 = 0xc,
DBG_BLOCK_ID_MCD4_BY4 = 0xd,
DBG_BLOCK_ID_SQA_BY4 = 0xe,
DBG_BLOCK_ID_SQA11_BY4 = 0xf,
DBG_BLOCK_ID_SQB_BY4 = 0x10,
DBG_BLOCK_ID_UNUSED10_BY4 = 0x11,
DBG_BLOCK_ID_CB_BY4 = 0x12,
DBG_BLOCK_ID_CB10_BY4 = 0x13,
DBG_BLOCK_ID_SXS_BY4 = 0x14,
DBG_BLOCK_ID_SXS4_BY4 = 0x15,
DBG_BLOCK_ID_DB_BY4 = 0x16,
DBG_BLOCK_ID_DB10_BY4 = 0x17,
DBG_BLOCK_ID_TCP_BY4 = 0x18,
DBG_BLOCK_ID_TCP4_BY4 = 0x19,
DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
DBG_BLOCK_ID_TCC_BY4 = 0x20,
DBG_BLOCK_ID_TCC4_BY4 = 0x21,
DBG_BLOCK_ID_SPS_BY4 = 0x22,
DBG_BLOCK_ID_SPS11_BY4 = 0x23,
DBG_BLOCK_ID_TA_BY4 = 0x24,
DBG_BLOCK_ID_TA04_BY4 = 0x25,
DBG_BLOCK_ID_TA08_BY4 = 0x26,
DBG_BLOCK_ID_UNUSED20_BY4 = 0x27,
DBG_BLOCK_ID_TA10_BY4 = 0x28,
DBG_BLOCK_ID_TA14_BY4 = 0x29,
DBG_BLOCK_ID_TA18_BY4 = 0x2a,
DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b,
DBG_BLOCK_ID_TD_BY4 = 0x2c,
DBG_BLOCK_ID_TD04_BY4 = 0x2d,
DBG_BLOCK_ID_TD08_BY4 = 0x2e,
DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f,
DBG_BLOCK_ID_TD10_BY4 = 0x30,
DBG_BLOCK_ID_TD14_BY4 = 0x31,
DBG_BLOCK_ID_TD18_BY4 = 0x32,
DBG_BLOCK_ID_UNUSED32_BY4 = 0x33,
DBG_BLOCK_ID_LDS_BY4 = 0x34,
DBG_BLOCK_ID_LDS04_BY4 = 0x35,
DBG_BLOCK_ID_LDS08_BY4 = 0x36,
DBG_BLOCK_ID_UNUSED36_BY4 = 0x37,
DBG_BLOCK_ID_LDS10_BY4 = 0x38,
DBG_BLOCK_ID_LDS14_BY4 = 0x39,
DBG_BLOCK_ID_LDS18_BY4 = 0x3a,
DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b,
} DebugBlockId_BY4;
typedef enum DebugBlockId_BY8 {
DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
DBG_BLOCK_ID_CSC_BY8 = 0x1,
DBG_BLOCK_ID_SDMA0_BY8 = 0x2,
DBG_BLOCK_ID_CP0_BY8 = 0x3,
DBG_BLOCK_ID_SXM0_BY8 = 0x4,
DBG_BLOCK_ID_TCA_BY8 = 0x5,
DBG_BLOCK_ID_MCD_BY8 = 0x6,
DBG_BLOCK_ID_SQA_BY8 = 0x7,
DBG_BLOCK_ID_SQB_BY8 = 0x8,
DBG_BLOCK_ID_CB_BY8 = 0x9,
DBG_BLOCK_ID_SXS_BY8 = 0xa,
DBG_BLOCK_ID_DB_BY8 = 0xb,
DBG_BLOCK_ID_TCP_BY8 = 0xc,
DBG_BLOCK_ID_TCP8_BY8 = 0xd,
DBG_BLOCK_ID_TCP16_BY8 = 0xe,
DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
DBG_BLOCK_ID_TCC_BY8 = 0x10,
DBG_BLOCK_ID_SPS_BY8 = 0x11,
DBG_BLOCK_ID_TA_BY8 = 0x12,
DBG_BLOCK_ID_TA08_BY8 = 0x13,
DBG_BLOCK_ID_TA10_BY8 = 0x14,
DBG_BLOCK_ID_TA18_BY8 = 0x15,
DBG_BLOCK_ID_TD_BY8 = 0x16,
DBG_BLOCK_ID_TD08_BY8 = 0x17,
DBG_BLOCK_ID_TD10_BY8 = 0x18,
DBG_BLOCK_ID_TD18_BY8 = 0x19,
DBG_BLOCK_ID_LDS_BY8 = 0x1a,
DBG_BLOCK_ID_LDS08_BY8 = 0x1b,
DBG_BLOCK_ID_LDS10_BY8 = 0x1c,
DBG_BLOCK_ID_LDS18_BY8 = 0x1d,
} DebugBlockId_BY8;
typedef enum DebugBlockId_BY16 {
DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
DBG_BLOCK_ID_SDMA0_BY16 = 0x1,
DBG_BLOCK_ID_SXM_BY16 = 0x2,
DBG_BLOCK_ID_MCD_BY16 = 0x3,
DBG_BLOCK_ID_SQB_BY16 = 0x4,
DBG_BLOCK_ID_SXS_BY16 = 0x5,
DBG_BLOCK_ID_TCP_BY16 = 0x6,
DBG_BLOCK_ID_TCP16_BY16 = 0x7,
DBG_BLOCK_ID_TCC_BY16 = 0x8,
DBG_BLOCK_ID_TA_BY16 = 0x9,
DBG_BLOCK_ID_TA10_BY16 = 0xa,
DBG_BLOCK_ID_TD_BY16 = 0xb,
DBG_BLOCK_ID_TD10_BY16 = 0xc,
DBG_BLOCK_ID_LDS_BY16 = 0xd,
DBG_BLOCK_ID_LDS10_BY16 = 0xe,
} DebugBlockId_BY16;
typedef enum SurfaceEndian {
ENDIAN_NONE = 0x0,
ENDIAN_8IN16 = 0x1,
ENDIAN_8IN32 = 0x2,
ENDIAN_8IN64 = 0x3,
} SurfaceEndian;
typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL = 0x0,
ARRAY_LINEAR_ALIGNED = 0x1,
ARRAY_1D_TILED_THIN1 = 0x2,
ARRAY_1D_TILED_THICK = 0x3,
ARRAY_2D_TILED_THIN1 = 0x4,
ARRAY_PRT_TILED_THIN1 = 0x5,
ARRAY_PRT_2D_TILED_THIN1 = 0x6,
ARRAY_2D_TILED_THICK = 0x7,
ARRAY_2D_TILED_XTHICK = 0x8,
ARRAY_PRT_TILED_THICK = 0x9,
ARRAY_PRT_2D_TILED_THICK = 0xa,
ARRAY_PRT_3D_TILED_THIN1 = 0xb,
ARRAY_3D_TILED_THIN1 = 0xc,
ARRAY_3D_TILED_THICK = 0xd,
ARRAY_3D_TILED_XTHICK = 0xe,
ARRAY_PRT_3D_TILED_THICK = 0xf,
} ArrayMode;
typedef enum PipeTiling {
CONFIG_1_PIPE = 0x0,
CONFIG_2_PIPE = 0x1,
CONFIG_4_PIPE = 0x2,
CONFIG_8_PIPE = 0x3,
} PipeTiling;
typedef enum BankTiling {
CONFIG_4_BANK = 0x0,
CONFIG_8_BANK = 0x1,
} BankTiling;
typedef enum GroupInterleave {
CONFIG_256B_GROUP = 0x0,
CONFIG_512B_GROUP = 0x1,
} GroupInterleave;
typedef enum RowTiling {
CONFIG_1KB_ROW = 0x0,
CONFIG_2KB_ROW = 0x1,
CONFIG_4KB_ROW = 0x2,
CONFIG_8KB_ROW = 0x3,
CONFIG_1KB_ROW_OPT = 0x4,
CONFIG_2KB_ROW_OPT = 0x5,
CONFIG_4KB_ROW_OPT = 0x6,
CONFIG_8KB_ROW_OPT = 0x7,
} RowTiling;
typedef enum BankSwapBytes {
CONFIG_128B_SWAPS = 0x0,
CONFIG_256B_SWAPS = 0x1,
CONFIG_512B_SWAPS = 0x2,
CONFIG_1KB_SWAPS = 0x3,
} BankSwapBytes;
typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT = 0x0,
CONFIG_2KB_SPLIT = 0x1,
CONFIG_4KB_SPLIT = 0x2,
CONFIG_8KB_SPLIT = 0x3,
} SampleSplitBytes;
typedef enum NumPipes {
ADDR_CONFIG_1_PIPE = 0x0,
ADDR_CONFIG_2_PIPE = 0x1,
ADDR_CONFIG_4_PIPE = 0x2,
ADDR_CONFIG_8_PIPE = 0x3,
} NumPipes;
typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
} PipeInterleaveSize;
typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
} BankInterleaveSize;
typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
} NumShaderEngines;
typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16 = 0x0,
ADDR_CONFIG_SE_TILE_32 = 0x1,
} ShaderEngineTileSize;
typedef enum NumGPUs {
ADDR_CONFIG_1_GPU = 0x0,
ADDR_CONFIG_2_GPU = 0x1,
ADDR_CONFIG_4_GPU = 0x2,
} NumGPUs;
typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16 = 0x0,
ADDR_CONFIG_GPU_TILE_32 = 0x1,
ADDR_CONFIG_GPU_TILE_64 = 0x2,
ADDR_CONFIG_GPU_TILE_128 = 0x3,
} MultiGPUTileSize;
typedef enum RowSize {
ADDR_CONFIG_1KB_ROW = 0x0,
ADDR_CONFIG_2KB_ROW = 0x1,
ADDR_CONFIG_4KB_ROW = 0x2,
} RowSize;
typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES = 0x0,
ADDR_CONFIG_2_LOWER_PIPES = 0x1,
} NumLowerPipes;
typedef enum ColorTransform {
DCC_CT_AUTO = 0x0,
DCC_CT_NONE = 0x1,
ABGR_TO_A_BG_G_RB = 0x2,
BGRA_TO_BG_G_RB_A = 0x3,
} ColorTransform;
typedef enum CompareRef {
REF_NEVER = 0x0,
REF_LESS = 0x1,
REF_EQUAL = 0x2,
REF_LEQUAL = 0x3,
REF_GREATER = 0x4,
REF_NOTEQUAL = 0x5,
REF_GEQUAL = 0x6,
REF_ALWAYS = 0x7,
} CompareRef;
typedef enum ReadSize {
READ_256_BITS = 0x0,
READ_512_BITS = 0x1,
} ReadSize;
typedef enum DepthFormat {
DEPTH_INVALID = 0x0,
DEPTH_16 = 0x1,
DEPTH_X8_24 = 0x2,
DEPTH_8_24 = 0x3,
DEPTH_X8_24_FLOAT = 0x4,
DEPTH_8_24_FLOAT = 0x5,
DEPTH_32_FLOAT = 0x6,
DEPTH_X24_8_32_FLOAT = 0x7,
} DepthFormat;
typedef enum ZFormat {
Z_INVALID = 0x0,
Z_16 = 0x1,
Z_24 = 0x2,
Z_32_FLOAT = 0x3,
} ZFormat;
typedef enum StencilFormat {
STENCIL_INVALID = 0x0,
STENCIL_8 = 0x1,
} StencilFormat;
typedef enum CmaskMode {
CMASK_CLEAR_NONE = 0x0,
CMASK_CLEAR_ONE = 0x1,
CMASK_CLEAR_ALL = 0x2,
CMASK_ANY_EXPANDED = 0x3,
CMASK_ALPHA0_FRAG1 = 0x4,
CMASK_ALPHA0_FRAG2 = 0x5,
CMASK_ALPHA0_FRAG4 = 0x6,
CMASK_ALPHA0_FRAGS = 0x7,
CMASK_ALPHA1_FRAG1 = 0x8,
CMASK_ALPHA1_FRAG2 = 0x9,
CMASK_ALPHA1_FRAG4 = 0xa,
CMASK_ALPHA1_FRAGS = 0xb,
CMASK_ALPHAX_FRAG1 = 0xc,
CMASK_ALPHAX_FRAG2 = 0xd,
CMASK_ALPHAX_FRAG4 = 0xe,
CMASK_ALPHAX_FRAGS = 0xf,
} CmaskMode;
typedef enum QuadExportFormat {
EXPORT_UNUSED = 0x0,
EXPORT_32_R = 0x1,
EXPORT_32_GR = 0x2,
EXPORT_32_AR = 0x3,
EXPORT_FP16_ABGR = 0x4,
EXPORT_UNSIGNED16_ABGR = 0x5,
EXPORT_SIGNED16_ABGR = 0x6,
EXPORT_32_ABGR = 0x7,
} QuadExportFormat;
typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR = 0x0,
EXPORT_4P_16BPC_ABGR = 0x1,
EXPORT_4P_32BPC_GR = 0x2,
EXPORT_4P_32BPC_AR = 0x3,
EXPORT_2P_32BPC_ABGR = 0x4,
EXPORT_8P_32BPC_R = 0x5,
} QuadExportFormatOld;
typedef enum ColorFormat {
COLOR_INVALID = 0x0,
COLOR_8 = 0x1,
COLOR_16 = 0x2,
COLOR_8_8 = 0x3,
COLOR_32 = 0x4,
COLOR_16_16 = 0x5,
COLOR_10_11_11 = 0x6,
COLOR_11_11_10 = 0x7,
COLOR_10_10_10_2 = 0x8,
COLOR_2_10_10_10 = 0x9,
COLOR_8_8_8_8 = 0xa,
COLOR_32_32 = 0xb,
COLOR_16_16_16_16 = 0xc,
COLOR_RESERVED_13 = 0xd,
COLOR_32_32_32_32 = 0xe,
COLOR_RESERVED_15 = 0xf,
COLOR_5_6_5 = 0x10,
COLOR_1_5_5_5 = 0x11,
COLOR_5_5_5_1 = 0x12,
COLOR_4_4_4_4 = 0x13,
COLOR_8_24 = 0x14,
COLOR_24_8 = 0x15,
COLOR_X24_8_32_FLOAT = 0x16,
COLOR_RESERVED_23 = 0x17,
} ColorFormat;
typedef enum SurfaceFormat {
FMT_INVALID = 0x0,
FMT_8 = 0x1,
FMT_16 = 0x2,
FMT_8_8 = 0x3,
FMT_32 = 0x4,
FMT_16_16 = 0x5,
FMT_10_11_11 = 0x6,
FMT_11_11_10 = 0x7,
FMT_10_10_10_2 = 0x8,
FMT_2_10_10_10 = 0x9,
FMT_8_8_8_8 = 0xa,
FMT_32_32 = 0xb,
FMT_16_16_16_16 = 0xc,
FMT_32_32_32 = 0xd,
FMT_32_32_32_32 = 0xe,
FMT_RESERVED_4 = 0xf,
FMT_5_6_5 = 0x10,
FMT_1_5_5_5 = 0x11,
FMT_5_5_5_1 = 0x12,
FMT_4_4_4_4 = 0x13,
FMT_8_24 = 0x14,
FMT_24_8 = 0x15,
FMT_X24_8_32_FLOAT = 0x16,
FMT_RESERVED_33 = 0x17,
FMT_11_11_10_FLOAT = 0x18,
FMT_16_FLOAT = 0x19,
FMT_32_FLOAT = 0x1a,
FMT_16_16_FLOAT = 0x1b,
FMT_8_24_FLOAT = 0x1c,
FMT_24_8_FLOAT = 0x1d,
FMT_32_32_FLOAT = 0x1e,
FMT_10_11_11_FLOAT = 0x1f,
FMT_16_16_16_16_FLOAT = 0x20,
FMT_3_3_2 = 0x21,
FMT_6_5_5 = 0x22,
FMT_32_32_32_32_FLOAT = 0x23,
FMT_RESERVED_36 = 0x24,
FMT_1 = 0x25,
FMT_1_REVERSED = 0x26,
FMT_GB_GR = 0x27,
FMT_BG_RG = 0x28,
FMT_32_AS_8 = 0x29,
FMT_32_AS_8_8 = 0x2a,
FMT_5_9_9_9_SHAREDEXP = 0x2b,
FMT_8_8_8 = 0x2c,
FMT_16_16_16 = 0x2d,
FMT_16_16_16_FLOAT = 0x2e,
FMT_4_4 = 0x2f,
FMT_32_32_32_FLOAT = 0x30,
FMT_BC1 = 0x31,
FMT_BC2 = 0x32,
FMT_BC3 = 0x33,
FMT_BC4 = 0x34,
FMT_BC5 = 0x35,
FMT_BC6 = 0x36,
FMT_BC7 = 0x37,
FMT_32_AS_32_32_32_32 = 0x38,
FMT_APC3 = 0x39,
FMT_APC4 = 0x3a,
FMT_APC5 = 0x3b,
FMT_APC6 = 0x3c,
FMT_APC7 = 0x3d,
FMT_CTX1 = 0x3e,
FMT_RESERVED_63 = 0x3f,
} SurfaceFormat;
typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID = 0x0,
BUF_DATA_FORMAT_8 = 0x1,
BUF_DATA_FORMAT_16 = 0x2,
BUF_DATA_FORMAT_8_8 = 0x3,
BUF_DATA_FORMAT_32 = 0x4,
BUF_DATA_FORMAT_16_16 = 0x5,
BUF_DATA_FORMAT_10_11_11 = 0x6,
BUF_DATA_FORMAT_11_11_10 = 0x7,
BUF_DATA_FORMAT_10_10_10_2 = 0x8,
BUF_DATA_FORMAT_2_10_10_10 = 0x9,
BUF_DATA_FORMAT_8_8_8_8 = 0xa,
BUF_DATA_FORMAT_32_32 = 0xb,
BUF_DATA_FORMAT_16_16_16_16 = 0xc,
BUF_DATA_FORMAT_32_32_32 = 0xd,
BUF_DATA_FORMAT_32_32_32_32 = 0xe,
BUF_DATA_FORMAT_RESERVED_15 = 0xf,
} BUF_DATA_FORMAT;
typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID = 0x0,
IMG_DATA_FORMAT_8 = 0x1,
IMG_DATA_FORMAT_16 = 0x2,
IMG_DATA_FORMAT_8_8 = 0x3,
IMG_DATA_FORMAT_32 = 0x4,
IMG_DATA_FORMAT_16_16 = 0x5,
IMG_DATA_FORMAT_10_11_11 = 0x6,
IMG_DATA_FORMAT_11_11_10 = 0x7,
IMG_DATA_FORMAT_10_10_10_2 = 0x8,
IMG_DATA_FORMAT_2_10_10_10 = 0x9,
IMG_DATA_FORMAT_8_8_8_8 = 0xa,
IMG_DATA_FORMAT_32_32 = 0xb,
IMG_DATA_FORMAT_16_16_16_16 = 0xc,
IMG_DATA_FORMAT_32_32_32 = 0xd,
IMG_DATA_FORMAT_32_32_32_32 = 0xe,
IMG_DATA_FORMAT_RESERVED_15 = 0xf,
IMG_DATA_FORMAT_5_6_5 = 0x10,
IMG_DATA_FORMAT_1_5_5_5 = 0x11,
IMG_DATA_FORMAT_5_5_5_1 = 0x12,
IMG_DATA_FORMAT_4_4_4_4 = 0x13,
IMG_DATA_FORMAT_8_24 = 0x14,
IMG_DATA_FORMAT_24_8 = 0x15,
IMG_DATA_FORMAT_X24_8_32 = 0x16,
IMG_DATA_FORMAT_RESERVED_23 = 0x17,
IMG_DATA_FORMAT_RESERVED_24 = 0x18,
IMG_DATA_FORMAT_RESERVED_25 = 0x19,
IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
IMG_DATA_FORMAT_GB_GR = 0x20,
IMG_DATA_FORMAT_BG_RG = 0x21,
IMG_DATA_FORMAT_5_9_9_9 = 0x22,
IMG_DATA_FORMAT_BC1 = 0x23,
IMG_DATA_FORMAT_BC2 = 0x24,
IMG_DATA_FORMAT_BC3 = 0x25,
IMG_DATA_FORMAT_BC4 = 0x26,
IMG_DATA_FORMAT_BC5 = 0x27,
IMG_DATA_FORMAT_BC6 = 0x28,
IMG_DATA_FORMAT_BC7 = 0x29,
IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
IMG_DATA_FORMAT_4_4 = 0x39,
IMG_DATA_FORMAT_6_5_5 = 0x3a,
IMG_DATA_FORMAT_1 = 0x3b,
IMG_DATA_FORMAT_1_REVERSED = 0x3c,
IMG_DATA_FORMAT_32_AS_8 = 0x3d,
IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
} IMG_DATA_FORMAT;
typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM = 0x0,
BUF_NUM_FORMAT_SNORM = 0x1,
BUF_NUM_FORMAT_USCALED = 0x2,
BUF_NUM_FORMAT_SSCALED = 0x3,
BUF_NUM_FORMAT_UINT = 0x4,
BUF_NUM_FORMAT_SINT = 0x5,
BUF_NUM_FORMAT_RESERVED_6 = 0x6,
BUF_NUM_FORMAT_FLOAT = 0x7,
} BUF_NUM_FORMAT;
typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM = 0x0,
IMG_NUM_FORMAT_SNORM = 0x1,
IMG_NUM_FORMAT_USCALED = 0x2,
IMG_NUM_FORMAT_SSCALED = 0x3,
IMG_NUM_FORMAT_UINT = 0x4,
IMG_NUM_FORMAT_SINT = 0x5,
IMG_NUM_FORMAT_RESERVED_6 = 0x6,
IMG_NUM_FORMAT_FLOAT = 0x7,
IMG_NUM_FORMAT_RESERVED_8 = 0x8,
IMG_NUM_FORMAT_SRGB = 0x9,
IMG_NUM_FORMAT_RESERVED_10 = 0xa,
IMG_NUM_FORMAT_RESERVED_11 = 0xb,
IMG_NUM_FORMAT_RESERVED_12 = 0xc,
IMG_NUM_FORMAT_RESERVED_13 = 0xd,
IMG_NUM_FORMAT_RESERVED_14 = 0xe,
IMG_NUM_FORMAT_RESERVED_15 = 0xf,
} IMG_NUM_FORMAT;
typedef enum TileType {
ARRAY_COLOR_TILE = 0x0,
ARRAY_DEPTH_TILE = 0x1,
} TileType;
typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
} NonDispTilingOrder;
typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
ADDR_SURF_THIN_MICRO_TILING = 0x1,
ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
ADDR_SURF_THICK_MICRO_TILING = 0x4,
} MicroTileMode;
typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B = 0x0,
ADDR_SURF_TILE_SPLIT_128B = 0x1,
ADDR_SURF_TILE_SPLIT_256B = 0x2,
ADDR_SURF_TILE_SPLIT_512B = 0x3,
ADDR_SURF_TILE_SPLIT_1KB = 0x4,
ADDR_SURF_TILE_SPLIT_2KB = 0x5,
ADDR_SURF_TILE_SPLIT_4KB = 0x6,
} TileSplit;
typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
} SampleSplit;
typedef enum PipeConfig {
ADDR_SURF_P2 = 0x0,
ADDR_SURF_P2_RESERVED0 = 0x1,
ADDR_SURF_P2_RESERVED1 = 0x2,
ADDR_SURF_P2_RESERVED2 = 0x3,
ADDR_SURF_P4_8x16 = 0x4,
ADDR_SURF_P4_16x16 = 0x5,
ADDR_SURF_P4_16x32 = 0x6,
ADDR_SURF_P4_32x32 = 0x7,
ADDR_SURF_P8_16x16_8x16 = 0x8,
ADDR_SURF_P8_16x32_8x16 = 0x9,
ADDR_SURF_P8_32x32_8x16 = 0xa,
ADDR_SURF_P8_16x32_16x16 = 0xb,
ADDR_SURF_P8_32x32_16x16 = 0xc,
ADDR_SURF_P8_32x32_16x32 = 0xd,
ADDR_SURF_P8_32x64_32x32 = 0xe,
ADDR_SURF_P8_RESERVED0 = 0xf,
ADDR_SURF_P16_32x32_8x16 = 0x10,
ADDR_SURF_P16_32x32_16x16 = 0x11,
} PipeConfig;
typedef enum NumBanks {
ADDR_SURF_2_BANK = 0x0,
ADDR_SURF_4_BANK = 0x1,
ADDR_SURF_8_BANK = 0x2,
ADDR_SURF_16_BANK = 0x3,
} NumBanks;
typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1 = 0x0,
ADDR_SURF_BANK_WIDTH_2 = 0x1,
ADDR_SURF_BANK_WIDTH_4 = 0x2,
ADDR_SURF_BANK_WIDTH_8 = 0x3,
} BankWidth;
typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1 = 0x0,
ADDR_SURF_BANK_HEIGHT_2 = 0x1,
ADDR_SURF_BANK_HEIGHT_4 = 0x2,
ADDR_SURF_BANK_HEIGHT_8 = 0x3,
} BankHeight;
typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1 = 0x0,
ADDR_SURF_BANK_WH_2 = 0x1,
ADDR_SURF_BANK_WH_4 = 0x2,
ADDR_SURF_BANK_WH_8 = 0x3,
} BankWidthHeight;
typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1 = 0x0,
ADDR_SURF_MACRO_ASPECT_2 = 0x1,
ADDR_SURF_MACRO_ASPECT_4 = 0x2,
ADDR_SURF_MACRO_ASPECT_8 = 0x3,
} MacroTileAspect;
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x0,
GATCL1_TYPE_SHOOTDOWN = 0x1,
GATCL1_TYPE_BYPASS = 0x2,
} GATCL1RequestType;
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x0,
TCC_CACHE_POLICY_STREAM = 0x1,
} TCC_CACHE_POLICIES;
typedef enum MTYPE {
MTYPE_NC_NV = 0x0,
MTYPE_NC = 0x1,
MTYPE_CC = 0x2,
MTYPE_UC = 0x3,
} MTYPE;
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x0,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
PERFMON_COUNTER_MODE_MAX = 0x2,
PERFMON_COUNTER_MODE_DIRTY = 0x3,
PERFMON_COUNTER_MODE_SAMPLE = 0x4,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
PERFMON_COUNTER_MODE_RESERVED = 0xf,
} PERFMON_COUNTER_MODE;
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x0,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
PERFMON_SPM_MODE_RESERVED_5 = 0x5,
PERFMON_SPM_MODE_RESERVED_6 = 0x6,
PERFMON_SPM_MODE_RESERVED_7 = 0x7,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
} PERFMON_SPM_MODE;
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x0,
ARRAY_TILED = 0x1,
} SurfaceTiling;
typedef enum SurfaceArray {
ARRAY_1D = 0x0,
ARRAY_2D = 0x1,
ARRAY_3D = 0x2,
ARRAY_3D_SLICE = 0x3,
} SurfaceArray;
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x0,
ARRAY_2D_COLOR = 0x1,
ARRAY_3D_SLICE_COLOR = 0x3,
} ColorArray;
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x0,
ARRAY_2D_DEPTH = 0x1,
} DepthArray;
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x4,
} ENUM_NUM_SIMD_PER_CU;
typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST = 0x0,
FORCE_LIGHT_SLEEP_REQUEST = 0x1,
FORCE_DEEP_SLEEP_REQUEST = 0x2,
FORCE_SHUT_DOWN_REQUEST = 0x3,
} MEM_PWR_FORCE_CTRL;
typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ = 0x0,
FORCE_LIGHT_SLEEP_REQ = 0x1,
} MEM_PWR_FORCE_CTRL2;
typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL = 0x0,
DISABLE_MEM_PWR_CTRL = 0x1,
} MEM_PWR_DIS_CTRL;
typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
} MEM_PWR_SEL_CTRL;
typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN = 0x0,
DYNAMIC_LIGHT_SLEEP_EN = 0x1,
} MEM_PWR_SEL_CTRL2;
#define CG_SRBM_START_ADDR 0x600
#define CG_SRBM_END_ADDR 0x8ff
#define CG_SRBM_DEC0_START_ADDR 0x200
#define CG_SRBM_DEC0_END_ADDR 0x2ff
#endif /* SMU_8_0_ENUM_H */
drivers/gpu/drm/amd/include/asic_reg/smu/smu_8_0_sh_mask.h 0 → 100644
View file @ 47e68987
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