Commit 48dd7cef authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'vfio-v4.7-rc1' of git://github.com/awilliam/linux-vfio

Pull VFIO updates from Alex Williamson:

 - Hide INTx on certain known broken devices (Alex Williamson)

 - Additional backdoor reset detection (Alex Williamson)

 - Remove unused iommudata reference (Alexey Kardashevskiy)

 - Use cfg_size to avoid probing extended config space (Alexey
   Kardashevskiy)

* tag 'vfio-v4.7-rc1' of git://github.com/awilliam/linux-vfio:
  vfio_pci: Test for extended capabilities if config space > 256 bytes
  vfio_iommu_spapr_tce: Remove unneeded iommu_group_get_iommudata
  vfio/pci: Add test for BAR restore
  vfio/pci: Hide broken INTx support from user
parents b462b37b f7055280
...@@ -113,6 +113,35 @@ static inline bool vfio_pci_is_vga(struct pci_dev *pdev) ...@@ -113,6 +113,35 @@ static inline bool vfio_pci_is_vga(struct pci_dev *pdev)
static void vfio_pci_try_bus_reset(struct vfio_pci_device *vdev); static void vfio_pci_try_bus_reset(struct vfio_pci_device *vdev);
static void vfio_pci_disable(struct vfio_pci_device *vdev); static void vfio_pci_disable(struct vfio_pci_device *vdev);
/*
* INTx masking requires the ability to disable INTx signaling via PCI_COMMAND
* _and_ the ability detect when the device is asserting INTx via PCI_STATUS.
* If a device implements the former but not the latter we would typically
* expect broken_intx_masking be set and require an exclusive interrupt.
* However since we do have control of the device's ability to assert INTx,
* we can instead pretend that the device does not implement INTx, virtualizing
* the pin register to report zero and maintaining DisINTx set on the host.
*/
static bool vfio_pci_nointx(struct pci_dev *pdev)
{
switch (pdev->vendor) {
case PCI_VENDOR_ID_INTEL:
switch (pdev->device) {
/* All i40e (XL710/X710) 10/20/40GbE NICs */
case 0x1572:
case 0x1574:
case 0x1580 ... 0x1581:
case 0x1583 ... 0x1589:
case 0x37d0 ... 0x37d2:
return true;
default:
return false;
}
}
return false;
}
static int vfio_pci_enable(struct vfio_pci_device *vdev) static int vfio_pci_enable(struct vfio_pci_device *vdev)
{ {
struct pci_dev *pdev = vdev->pdev; struct pci_dev *pdev = vdev->pdev;
...@@ -136,16 +165,14 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev) ...@@ -136,16 +165,14 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
pr_debug("%s: Couldn't store %s saved state\n", pr_debug("%s: Couldn't store %s saved state\n",
__func__, dev_name(&pdev->dev)); __func__, dev_name(&pdev->dev));
ret = vfio_config_init(vdev); if (likely(!nointxmask)) {
if (ret) { if (vfio_pci_nointx(pdev)) {
kfree(vdev->pci_saved_state); dev_info(&pdev->dev, "Masking broken INTx support\n");
vdev->pci_saved_state = NULL; vdev->nointx = true;
pci_disable_device(pdev); pci_intx(pdev, 0);
return ret; } else
}
if (likely(!nointxmask))
vdev->pci_2_3 = pci_intx_mask_supported(pdev); vdev->pci_2_3 = pci_intx_mask_supported(pdev);
}
pci_read_config_word(pdev, PCI_COMMAND, &cmd); pci_read_config_word(pdev, PCI_COMMAND, &cmd);
if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) { if (vdev->pci_2_3 && (cmd & PCI_COMMAND_INTX_DISABLE)) {
...@@ -153,6 +180,14 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev) ...@@ -153,6 +180,14 @@ static int vfio_pci_enable(struct vfio_pci_device *vdev)
pci_write_config_word(pdev, PCI_COMMAND, cmd); pci_write_config_word(pdev, PCI_COMMAND, cmd);
} }
ret = vfio_config_init(vdev);
if (ret) {
kfree(vdev->pci_saved_state);
vdev->pci_saved_state = NULL;
pci_disable_device(pdev);
return ret;
}
msix_pos = pdev->msix_cap; msix_pos = pdev->msix_cap;
if (msix_pos) { if (msix_pos) {
u16 flags; u16 flags;
...@@ -304,7 +339,7 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type) ...@@ -304,7 +339,7 @@ static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type)
if (irq_type == VFIO_PCI_INTX_IRQ_INDEX) { if (irq_type == VFIO_PCI_INTX_IRQ_INDEX) {
u8 pin; u8 pin;
pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin); pci_read_config_byte(vdev->pdev, PCI_INTERRUPT_PIN, &pin);
if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && pin) if (IS_ENABLED(CONFIG_VFIO_PCI_INTX) && !vdev->nointx && pin)
return 1; return 1;
} else if (irq_type == VFIO_PCI_MSI_IRQ_INDEX) { } else if (irq_type == VFIO_PCI_MSI_IRQ_INDEX) {
......
...@@ -408,6 +408,7 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev) ...@@ -408,6 +408,7 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev)
{ {
struct pci_dev *pdev = vdev->pdev; struct pci_dev *pdev = vdev->pdev;
u32 *rbar = vdev->rbar; u32 *rbar = vdev->rbar;
u16 cmd;
int i; int i;
if (pdev->is_virtfn) if (pdev->is_virtfn)
...@@ -420,6 +421,12 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev) ...@@ -420,6 +421,12 @@ static void vfio_bar_restore(struct vfio_pci_device *vdev)
pci_user_write_config_dword(pdev, i, *rbar); pci_user_write_config_dword(pdev, i, *rbar);
pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar); pci_user_write_config_dword(pdev, PCI_ROM_ADDRESS, *rbar);
if (vdev->nointx) {
pci_user_read_config_word(pdev, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_INTX_DISABLE;
pci_user_write_config_word(pdev, PCI_COMMAND, cmd);
}
} }
static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar) static __le32 vfio_generate_bar_flags(struct pci_dev *pdev, int bar)
...@@ -515,6 +522,23 @@ static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos, ...@@ -515,6 +522,23 @@ static int vfio_basic_config_read(struct vfio_pci_device *vdev, int pos,
return count; return count;
} }
/* Test whether BARs match the value we think they should contain */
static bool vfio_need_bar_restore(struct vfio_pci_device *vdev)
{
int i = 0, pos = PCI_BASE_ADDRESS_0, ret;
u32 bar;
for (; pos <= PCI_BASE_ADDRESS_5; i++, pos += 4) {
if (vdev->rbar[i]) {
ret = pci_user_read_config_dword(vdev->pdev, pos, &bar);
if (ret || vdev->rbar[i] != bar)
return true;
}
}
return false;
}
static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
int count, struct perm_bits *perm, int count, struct perm_bits *perm,
int offset, __le32 val) int offset, __le32 val)
...@@ -553,7 +577,8 @@ static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos, ...@@ -553,7 +577,8 @@ static int vfio_basic_config_write(struct vfio_pci_device *vdev, int pos,
* SR-IOV devices will trigger this, but we catch them later * SR-IOV devices will trigger this, but we catch them later
*/ */
if ((new_mem && virt_mem && !phys_mem) || if ((new_mem && virt_mem && !phys_mem) ||
(new_io && virt_io && !phys_io)) (new_io && virt_io && !phys_io) ||
vfio_need_bar_restore(vdev))
vfio_bar_restore(vdev); vfio_bar_restore(vdev);
} }
...@@ -1124,9 +1149,12 @@ static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) ...@@ -1124,9 +1149,12 @@ static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
return pcibios_err_to_errno(ret); return pcibios_err_to_errno(ret);
if (PCI_X_CMD_VERSION(word)) { if (PCI_X_CMD_VERSION(word)) {
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
/* Test for extended capabilities */ /* Test for extended capabilities */
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE,
&dword);
vdev->extended_caps = (dword != 0); vdev->extended_caps = (dword != 0);
}
return PCI_CAP_PCIX_SIZEOF_V2; return PCI_CAP_PCIX_SIZEOF_V2;
} else } else
return PCI_CAP_PCIX_SIZEOF_V0; return PCI_CAP_PCIX_SIZEOF_V0;
...@@ -1138,9 +1166,11 @@ static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos) ...@@ -1138,9 +1166,11 @@ static int vfio_cap_len(struct vfio_pci_device *vdev, u8 cap, u8 pos)
return byte; return byte;
case PCI_CAP_ID_EXP: case PCI_CAP_ID_EXP:
if (pdev->cfg_size > PCI_CFG_SPACE_SIZE) {
/* Test for extended capabilities */ /* Test for extended capabilities */
pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword); pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &dword);
vdev->extended_caps = (dword != 0); vdev->extended_caps = (dword != 0);
}
/* length based on version */ /* length based on version */
if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1) if ((pcie_caps_reg(pdev) & PCI_EXP_FLAGS_VERS) == 1)
...@@ -1545,7 +1575,7 @@ int vfio_config_init(struct vfio_pci_device *vdev) ...@@ -1545,7 +1575,7 @@ int vfio_config_init(struct vfio_pci_device *vdev)
*(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device); *(__le16 *)&vconfig[PCI_DEVICE_ID] = cpu_to_le16(pdev->device);
} }
if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX)) if (!IS_ENABLED(CONFIG_VFIO_PCI_INTX) || vdev->nointx)
vconfig[PCI_INTERRUPT_PIN] = 0; vconfig[PCI_INTERRUPT_PIN] = 0;
ret = vfio_cap_init(vdev); ret = vfio_cap_init(vdev);
......
...@@ -83,6 +83,7 @@ struct vfio_pci_device { ...@@ -83,6 +83,7 @@ struct vfio_pci_device {
bool bardirty; bool bardirty;
bool has_vga; bool has_vga;
bool needs_reset; bool needs_reset;
bool nointx;
struct pci_saved_state *pci_saved_state; struct pci_saved_state *pci_saved_state;
int refcnt; int refcnt;
struct eventfd_ctx *err_trigger; struct eventfd_ctx *err_trigger;
......
...@@ -331,14 +331,12 @@ static void tce_iommu_free_table(struct iommu_table *tbl); ...@@ -331,14 +331,12 @@ static void tce_iommu_free_table(struct iommu_table *tbl);
static void tce_iommu_release(void *iommu_data) static void tce_iommu_release(void *iommu_data)
{ {
struct tce_container *container = iommu_data; struct tce_container *container = iommu_data;
struct iommu_table_group *table_group;
struct tce_iommu_group *tcegrp; struct tce_iommu_group *tcegrp;
long i; long i;
while (tce_groups_attached(container)) { while (tce_groups_attached(container)) {
tcegrp = list_first_entry(&container->group_list, tcegrp = list_first_entry(&container->group_list,
struct tce_iommu_group, next); struct tce_iommu_group, next);
table_group = iommu_group_get_iommudata(tcegrp->grp);
tce_iommu_detach_group(iommu_data, tcegrp->grp); tce_iommu_detach_group(iommu_data, tcegrp->grp);
} }
......
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