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Commit 496a2e36 authored by Grant Likely's avatar Grant Likely
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Merge branch 'for-grant' of git://arago-project.org/git/projects/linux-davinci into spi/next 

* 'for-grant' of git://arago-project.org/git/projects/linux-davinci into spi/next
   spi: davinci: fix checkpatch errors
   spi: davinci: whitespace cleanup
   spi: davinci: remove unused variable 'pdata'
   spi: davinci: set chip-select mode in SPIDEF only once
   spi: davinci: enable both activation and deactivation of chip-selects
   spi: davinci: remove unnecessary data transmit on CS disable
   spi: davinci: enable GPIO lines to be used as chip selects
   spi: davinci: simplify prescalar calculation
   spi: davinci: remove 'wait_enable' platform data member
   spi: davinci: make chip-slect specific parameters really chip-select specific
   spi: davinci: consolidate setup of SPIFMTn in one function
   spi: davinci: setup chip-select timers values only if timer enabled
   spi: davinci: add support for wait enable timeouts
   spi: davinci: remove unused members of davinci_spi_slave
   spi: davinci: eliminate the single member structure davinci_spi_slave
   spi: davinci: eliminate unnecessary update of davinci_spi->count
   spi: davinci: simplify calculation of edma acount value
   spi: davinci: check for NULL buffer pointer before using it
   spi: davinci: remove unnecessary disable of SPI
   spi: davinci: remove unnecessary 'count' variable in driver private data
   spi: davinci: remove unnecessary completion variable initialization
   spi: davinci: remove non-useful interrupt mode support
   spi: davinci: simplify poll mode transfers
   spi: davinci: add support for interrupt mode
   spi: davinci: configure the invariable bits in spipc0 only once
   spi: davinci: remove unnecessary function davinci_spi_bufs_prep()
   spi: davinci: remove unnecessary call to davinci_spi_setup_transfer()
   spi: davinci: do not store DMA channel information per chip select
   spi: davinci: always start transmit DMA
   spi: davinci: do not use temporary buffer if no transmit data provided
   spi: davinci: always start receive DMA
   spi: davinci: use edma_write_slot() to setup EDMA PaRAM slot
   spi: davinci: fix DMA event generation stoppage
   spi: davinci: fix EDMA CC errors at end of transfers
   spi: davinci: handle DMA completion errors correctly
   spi: davinci: remove usage of additional completion variables for DMA
   spi: davinci: let DMA operation be specified on per-device basis
   spi: davinci: remove non-useful "clk_internal" platform data
   spi: davinci: enable and power-up SPI only when required
   spi: davinci: setup the driver owner
   spi: davinci: add additional comments
   spi: davinci: add EF Johnson Technologies copyright
   spi: davinci: removed unused #defines
   spi: davinci: remove unnecessary typecast
   spi: davinci: do not treat Tx interrupt being set as error
   spi: davinci: do not allocate DMA channels during SPI device setup
   spi: davinci: remove unnecessary private data member 'region_size'
   spi: davinci: shorten variable names
   spi: davinci: kconfig: add manufacturer name to prompt string
parents 5aa68b85 23ce17ad
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arch/arm/mach-davinci/dm355.c
View file @ 496a2e36
......@@ -412,12 +412,7 @@ static struct resource dm355_spi0_resources[] = {
static struct davinci_spi_platform_data dm355_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.clk_internal = 1,
.cs_hold = 1,
.intr_level = 0,
.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
.c2tdelay = 0,
.t2cdelay = 0,
.cshold_bug = true,
};
static struct platform_device dm355_spi0_device = {
.name = "spi_davinci",
......
arch/arm/mach-davinci/dm365.c
View file @ 496a2e36
......@@ -625,12 +625,6 @@ static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
static struct davinci_spi_platform_data dm365_spi0_pdata = {
.version = SPI_VERSION_1,
.num_chipselect = 2,
.clk_internal = 1,
.cs_hold = 1,
.intr_level = 0,
.poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
.c2tdelay = 0,
.t2cdelay = 0,
};
static struct resource dm365_spi0_resources[] = {
......
arch/arm/mach-davinci/include/mach/spi.h
View file @ 496a2e36
......@@ -19,26 +19,66 @@
#ifndef __ARCH_ARM_DAVINCI_SPI_H
#define __ARCH_ARM_DAVINCI_SPI_H
#define SPI_INTERN_CS 0xFF
enum {
SPI_VERSION_1, /* For DM355/DM365/DM6467 */
SPI_VERSION_2, /* For DA8xx */
};
/**
* davinci_spi_platform_data - Platform data for SPI master device on DaVinci
*
* @version: version of the SPI IP. Different DaVinci devices have slightly
* varying versions of the same IP.
* @num_chipselect: number of chipselects supported by this SPI master
* @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
* controller withn the SoC. Possible values are 0 and 1.
* @chip_sel: list of GPIOs which can act as chip-selects for the SPI.
* SPI_INTERN_CS denotes internal SPI chip-select. Not necessary
* to populate if all chip-selects are internal.
* @cshold_bug: set this to true if the SPI controller on your chip requires
* a write to CSHOLD bit in between transfers (like in DM355).
*/
struct davinci_spi_platform_data {
u8 version;
u8 num_chipselect;
u8 intr_line;
u8 *chip_sel;
bool cshold_bug;
};
/**
* davinci_spi_config - Per-chip-select configuration for SPI slave devices
*
* @wdelay: amount of delay between transmissions. Measured in number of
* SPI module clocks.
* @odd_parity: polarity of parity flag at the end of transmit data stream.
* 0 - odd parity, 1 - even parity.
* @parity_enable: enable transmission of parity at end of each transmit
* data stream.
* @io_type: type of IO transfer. Choose between polled, interrupt and DMA.
* @timer_disable: disable chip-select timers (setup and hold)
* @c2tdelay: chip-select setup time. Measured in number of SPI module clocks.
* @t2cdelay: chip-select hold time. Measured in number of SPI module clocks.
* @t2edelay: transmit data finished to SPI ENAn pin inactive time. Measured
* in number of SPI clocks.
* @c2edelay: chip-select active to SPI ENAn signal active time. Measured in
* number of SPI clocks.
*/
struct davinci_spi_config {
u8 wdelay;
u8 odd_parity;
u8 parity_enable;
u8 wait_enable;
#define SPI_IO_TYPE_INTR 0
#define SPI_IO_TYPE_POLL 1
#define SPI_IO_TYPE_DMA 2
u8 io_type;
u8 timer_disable;
u8 clk_internal;
u8 cs_hold;
u8 intr_level;
u8 poll_mode;
u8 use_dma;
u8 c2tdelay;
u8 t2cdelay;
u8 t2edelay;
u8 c2edelay;
};
#endif /* __ARCH_ARM_DAVINCI_SPI_H */
drivers/spi/Kconfig
View file @ 496a2e36
......@@ -111,11 +111,14 @@ config SPI_COLDFIRE_QSPI
will be called coldfire_qspi.
config SPI_DAVINCI
tristate "SPI controller driver for DaVinci/DA8xx SoC's"
tristate "Texas Instruments DaVinci/DA8x/OMAP-L/AM1x SoC SPI controller"
depends on SPI_MASTER && ARCH_DAVINCI
select SPI_BITBANG
help
SPI master controller for DaVinci and DA8xx SPI modules.
SPI master controller for DaVinci/DA8x/OMAP-L/AM1x SPI modules.
This driver can also be built as a module. The module will be called
davinci_spi.
config SPI_EP93XX
tristate "Cirrus Logic EP93xx SPI controller"
......
drivers/spi/davinci_spi.c
View file @ 496a2e36
/*
* Copyright (C) 2009 Texas Instruments.
* Copyright (C) 2010 EF Johnson Technologies
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -38,11 +39,6 @@
#define CS_DEFAULT 0xFF
#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
#define DAVINCI_DMA_DATA_TYPE_S8 0x01
#define DAVINCI_DMA_DATA_TYPE_S16 0x02
#define DAVINCI_DMA_DATA_TYPE_S32 0x04
#define SPIFMT_PHASE_MASK BIT(16)
#define SPIFMT_POLARITY_MASK BIT(17)
#define SPIFMT_DISTIMER_MASK BIT(18)
......@@ -52,34 +48,43 @@
#define SPIFMT_ODD_PARITY_MASK BIT(23)
#define SPIFMT_WDELAY_MASK 0x3f000000u
#define SPIFMT_WDELAY_SHIFT 24
#define SPIFMT_CHARLEN_MASK 0x0000001Fu
/* SPIGCR1 */
#define SPIGCR1_SPIENA_MASK 0x01000000u
#define SPIFMT_PRESCALE_SHIFT 8
/* SPIPC0 */
#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
#define SPIPC0_EN1FUN_MASK BIT(1)
#define SPIPC0_EN0FUN_MASK BIT(0)
#define SPIINT_MASKALL 0x0101035F
#define SPI_INTLVL_1 0x000001FFu
#define SPI_INTLVL_0 0x00000000u
#define SPIINT_MASKINT 0x0000015F
#define SPI_INTLVL_1 0x000001FF
#define SPI_INTLVL_0 0x00000000
/* SPIDAT1 */
#define SPIDAT1_CSHOLD_SHIFT 28
#define SPIDAT1_CSNR_SHIFT 16
/* SPIDAT1 (upper 16 bit defines) */
#define SPIDAT1_CSHOLD_MASK BIT(12)
/* SPIGCR1 */
#define SPIGCR1_CLKMOD_MASK BIT(1)
#define SPIGCR1_MASTER_MASK BIT(0)
#define SPIGCR1_POWERDOWN_MASK BIT(8)
#define SPIGCR1_LOOPBACK_MASK BIT(16)
#define SPIGCR1_SPIENA_MASK BIT(24)
/* SPIBUF */
#define SPIBUF_TXFULL_MASK BIT(29)
#define SPIBUF_RXEMPTY_MASK BIT(31)
/* SPIDELAY */
#define SPIDELAY_C2TDELAY_SHIFT 24
#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
#define SPIDELAY_T2CDELAY_SHIFT 16
#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
#define SPIDELAY_T2EDELAY_SHIFT 8
#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
#define SPIDELAY_C2EDELAY_SHIFT 0
#define SPIDELAY_C2EDELAY_MASK 0xFF
/* Error Masks */
#define SPIFLG_DLEN_ERR_MASK BIT(0)
#define SPIFLG_TIMEOUT_MASK BIT(1)
......@@ -87,29 +92,13 @@
#define SPIFLG_DESYNC_MASK BIT(3)
#define SPIFLG_BITERR_MASK BIT(4)
#define SPIFLG_OVRRUN_MASK BIT(6)
#define SPIFLG_RX_INTR_MASK BIT(8)
#define SPIFLG_TX_INTR_MASK BIT(9)
#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
| SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
| SPIFLG_TX_INTR_MASK \
| SPIFLG_BUF_INIT_ACTIVE_MASK)
#define SPIINT_DLEN_ERR_INTR BIT(0)
#define SPIINT_TIMEOUT_INTR BIT(1)
#define SPIINT_PARERR_INTR BIT(2)
#define SPIINT_DESYNC_INTR BIT(3)
#define SPIINT_BITERR_INTR BIT(4)
#define SPIINT_OVRRUN_INTR BIT(6)
#define SPIINT_RX_INTR BIT(8)
#define SPIINT_TX_INTR BIT(9)
#define SPIINT_DMA_REQ_EN BIT(16)
#define SPIINT_ENABLE_HIGHZ BIT(24)
| SPIFLG_OVRRUN_MASK)
#define SPI_T2CDELAY_SHIFT 16
#define SPI_C2TDELAY_SHIFT 24
#define SPIINT_DMA_REQ_EN BIT(16)
/* SPI Controller registers */
#define SPIGCR0 0x00
......@@ -118,44 +107,18 @@
#define SPILVL 0x0c
#define SPIFLG 0x10
#define SPIPC0 0x14
#define SPIPC1 0x18
#define SPIPC2 0x1c
#define SPIPC3 0x20
#define SPIPC4 0x24
#define SPIPC5 0x28
#define SPIPC6 0x2c
#define SPIPC7 0x30
#define SPIPC8 0x34
#define SPIDAT0 0x38
#define SPIDAT1 0x3c
#define SPIBUF 0x40
#define SPIEMU 0x44
#define SPIDELAY 0x48
#define SPIDEF 0x4c
#define SPIFMT0 0x50
#define SPIFMT1 0x54
#define SPIFMT2 0x58
#define SPIFMT3 0x5c
#define TGINTVEC0 0x60
#define TGINTVEC1 0x64
struct davinci_spi_slave {
u32 cmd_to_write;
u32 clk_ctrl_to_write;
u32 bytes_per_word;
u8 active_cs;
};
/* We have 2 DMA channels per CS, one for RX and one for TX */
struct davinci_spi_dma {
int dma_tx_channel;
int dma_rx_channel;
int dma_tx_sync_dev;
int dma_rx_sync_dev;
int tx_channel;
int rx_channel;
int dummy_param_slot;
enum dma_event_q eventq;
struct completion dma_tx_completion;
struct completion dma_rx_completion;
};
/* SPI Controller driver's private data. */
......@@ -166,58 +129,63 @@ struct davinci_spi {
u8 version;
resource_size_t pbase;
void __iomem *base;
size_t region_size;
u32 irq;
struct completion done;
const void *tx;
void *rx;
u8 *tmp_buf;
int count;
struct davinci_spi_dma *dma_channels;
struct davinci_spi_platform_data *pdata;
#define SPI_TMP_BUFSZ (SMP_CACHE_BYTES + 1)
u8 rx_tmp_buf[SPI_TMP_BUFSZ];
int rcount;
int wcount;
struct davinci_spi_dma dma;
struct davinci_spi_platform_data *pdata;
void (*get_rx)(u32 rx_data, struct davinci_spi *);
u32 (*get_tx)(struct davinci_spi *);
struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
u8 bytes_per_word[SPI_MAX_CHIPSELECT];
};
static unsigned use_dma;
static struct davinci_spi_config davinci_spi_default_cfg;
static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
{
u8 *rx = davinci_spi->rx;
*rx++ = (u8)data;
davinci_spi->rx = rx;
if (dspi->rx) {
u8 *rx = dspi->rx;
*rx++ = (u8)data;
dspi->rx = rx;
}
}
static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
{
u16 *rx = davinci_spi->rx;
*rx++ = (u16)data;
davinci_spi->rx = rx;
if (dspi->rx) {
u16 *rx = dspi->rx;
*rx++ = (u16)data;
dspi->rx = rx;
}
}
static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
{
u32 data;
const u8 *tx = davinci_spi->tx;
data = *tx++;
davinci_spi->tx = tx;
u32 data = 0;
if (dspi->tx) {
const u8 *tx = dspi->tx;
data = *tx++;
dspi->tx = tx;
}
return data;
}
static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
{
u32 data;
const u16 *tx = davinci_spi->tx;
data = *tx++;
davinci_spi->tx = tx;
u32 data = 0;
if (dspi->tx) {
const u16 *tx = dspi->tx;
data = *tx++;
dspi->tx = tx;
}
return data;
}
......@@ -237,54 +205,66 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits)
iowrite32(v, addr);
}
static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
{
set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
}
static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
{
clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
}
static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
{
struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
if (enable)
set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
else
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
}
/*
* Interface to control the chip select signal
*/
static void davinci_spi_chipselect(struct spi_device *spi, int value)
{
struct davinci_spi *davinci_spi;
struct davinci_spi *dspi;
struct davinci_spi_platform_data *pdata;
u32 data1_reg_val = 0;
u8 chip_sel = spi->chip_select;
u16 spidat1 = CS_DEFAULT;
bool gpio_chipsel = false;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
dspi = spi_master_get_devdata(spi->master);
pdata = dspi->pdata;
if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
gpio_chipsel = true;
/*
* Board specific chip select logic decides the polarity and cs
* line for the controller
*/
if (value == BITBANG_CS_INACTIVE) {
set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
if (gpio_chipsel) {
if (value == BITBANG_CS_ACTIVE)
gpio_set_value(pdata->chip_sel[chip_sel], 0);
else
gpio_set_value(pdata->chip_sel[chip_sel], 1);
} else {
if (value == BITBANG_CS_ACTIVE) {
spidat1 |= SPIDAT1_CSHOLD_MASK;
spidat1 &= ~(0x1 << chip_sel);
}
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
}
}
/**
* davinci_spi_get_prescale - Calculates the correct prescale value
* @maxspeed_hz: the maximum rate the SPI clock can run at
*
* This function calculates the prescale value that generates a clock rate
* less than or equal to the specified maximum.
*
* Returns: calculated prescale - 1 for easy programming into SPI registers
* or negative error number if valid prescalar cannot be updated.
*/
static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
u32 max_speed_hz)
{
int ret;
ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
if (ret < 3 || ret > 256)
return -EINVAL;
return ret - 1;
}
/**
* davinci_spi_setup_transfer - This functions will determine transfer method
* @spi: spi device on which data transfer to be done
......@@ -298,13 +278,15 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
struct spi_transfer *t)
{
struct davinci_spi *davinci_spi;
struct davinci_spi_platform_data *pdata;
struct davinci_spi *dspi;
struct davinci_spi_config *spicfg;
u8 bits_per_word = 0;
u32 hz = 0, prescale = 0, clkspeed;
u32 hz = 0, spifmt = 0, prescale = 0;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
dspi = spi_master_get_devdata(spi->master);
spicfg = (struct davinci_spi_config *)spi->controller_data;
if (!spicfg)
spicfg = &davinci_spi_default_cfg;
if (t) {
bits_per_word = t->bits_per_word;
......@@ -320,111 +302,83 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
* 8bit, 16bit or 32bit transfer
*/
if (bits_per_word <= 8 && bits_per_word >= 2) {
davinci_spi->get_rx = davinci_spi_rx_buf_u8;
davinci_spi->get_tx = davinci_spi_tx_buf_u8;
davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
dspi->get_rx = davinci_spi_rx_buf_u8;
dspi->get_tx = davinci_spi_tx_buf_u8;
dspi->bytes_per_word[spi->chip_select] = 1;
} else if (bits_per_word <= 16 && bits_per_word >= 2) {
davinci_spi->get_rx = davinci_spi_rx_buf_u16;
davinci_spi->get_tx = davinci_spi_tx_buf_u16;
davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
dspi->get_rx = davinci_spi_rx_buf_u16;
dspi->get_tx = davinci_spi_tx_buf_u16;
dspi->bytes_per_word[spi->chip_select] = 2;
} else
return -EINVAL;
if (!hz)
hz = spi->max_speed_hz;
clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
spi->chip_select);
set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
spi->chip_select);
/* Set up SPIFMTn register, unique to this chipselect. */
clkspeed = clk_get_rate(davinci_spi->clk);
if (hz > clkspeed / 2)
prescale = 1 << 8;
if (hz < clkspeed / 256)
prescale = 255 << 8;
if (!prescale)
prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
prescale = davinci_spi_get_prescale(dspi, hz);
if (prescale < 0)
return prescale;
clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
return 0;
}
if (spi->mode & SPI_LSB_FIRST)
spifmt |= SPIFMT_SHIFTDIR_MASK;
static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
{
struct spi_device *spi = (struct spi_device *)data;
struct davinci_spi *davinci_spi;
struct davinci_spi_dma *davinci_spi_dma;
struct davinci_spi_platform_data *pdata;
if (spi->mode & SPI_CPOL)
spifmt |= SPIFMT_POLARITY_MASK;
davinci_spi = spi_master_get_devdata(spi->master);
davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
pdata = davinci_spi->pdata;
if (!(spi->mode & SPI_CPHA))
spifmt |= SPIFMT_PHASE_MASK;
if (ch_status == DMA_COMPLETE)
edma_stop(davinci_spi_dma->dma_rx_channel);
else
edma_clean_channel(davinci_spi_dma->dma_rx_channel);
/*
* Version 1 hardware supports two basic SPI modes:
* - Standard SPI mode uses 4 pins, with chipselect
* - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
* (distinct from SPI_3WIRE, with just one data wire;
* or similar variants without MOSI or without MISO)
*
* Version 2 hardware supports an optional handshaking signal,
* so it can support two more modes:
* - 5 pin SPI variant is standard SPI plus SPI_READY
* - 4 pin with enable is (SPI_READY | SPI_NO_CS)
*/
complete(&davinci_spi_dma->dma_rx_completion);
/* We must disable the DMA RX request */
davinci_spi_set_dma_req(spi, 0);
}
if (dspi->version == SPI_VERSION_2) {
static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
{
struct spi_device *spi = (struct spi_device *)data;
struct davinci_spi *davinci_spi;
struct davinci_spi_dma *davinci_spi_dma;
struct davinci_spi_platform_data *pdata;
u32 delay = 0;
davinci_spi = spi_master_get_devdata(spi->master);
davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
pdata = davinci_spi->pdata;
spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
& SPIFMT_WDELAY_MASK);
if (ch_status == DMA_COMPLETE)
edma_stop(davinci_spi_dma->dma_tx_channel);
else
edma_clean_channel(davinci_spi_dma->dma_tx_channel);
if (spicfg->odd_parity)
spifmt |= SPIFMT_ODD_PARITY_MASK;
complete(&davinci_spi_dma->dma_tx_completion);
/* We must disable the DMA TX request */
davinci_spi_set_dma_req(spi, 0);
}
if (spicfg->parity_enable)
spifmt |= SPIFMT_PARITYENA_MASK;
static int davinci_spi_request_dma(struct spi_device *spi)
{
struct davinci_spi *davinci_spi;
struct davinci_spi_dma *davinci_spi_dma;
struct davinci_spi_platform_data *pdata;
struct device *sdev;
int r;
if (spicfg->timer_disable) {
spifmt |= SPIFMT_DISTIMER_MASK;
} else {
delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
& SPIDELAY_C2TDELAY_MASK;
delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
& SPIDELAY_T2CDELAY_MASK;
}
davinci_spi = spi_master_get_devdata(spi->master);
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
pdata = davinci_spi->pdata;
sdev = davinci_spi->bitbang.master->dev.parent;
if (spi->mode & SPI_READY) {
spifmt |= SPIFMT_WAITENA_MASK;
delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
& SPIDELAY_T2EDELAY_MASK;
delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
& SPIDELAY_C2EDELAY_MASK;
}
r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
davinci_spi_dma_rx_callback, spi,
davinci_spi_dma->eventq);
if (r < 0) {
dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
return -EAGAIN;
iowrite32(delay, dspi->base + SPIDELAY);
}
davinci_spi_dma->dma_rx_channel = r;
r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
davinci_spi_dma_tx_callback, spi,
davinci_spi_dma->eventq);
if (r < 0) {
edma_free_channel(davinci_spi_dma->dma_rx_channel);
davinci_spi_dma->dma_rx_channel = -1;
dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
return -EAGAIN;
}
davinci_spi_dma->dma_tx_channel = r;
iowrite32(spifmt, dspi->base + SPIFMT0);
return 0;
}
......@@ -435,190 +389,40 @@ static int davinci_spi_request_dma(struct spi_device *spi)
*
* This functions sets the default transfer method.
*/
static int davinci_spi_setup(struct spi_device *spi)
{
int retval;
struct davinci_spi *davinci_spi;
struct davinci_spi_dma *davinci_spi_dma;
struct device *sdev;
int retval = 0;
struct davinci_spi *dspi;
struct davinci_spi_platform_data *pdata;
davinci_spi = spi_master_get_devdata(spi->master);
sdev = davinci_spi->bitbang.master->dev.parent;
dspi = spi_master_get_devdata(spi->master);
pdata = dspi->pdata;
/* if bits per word length is zero then set it default 8 */
if (!spi->bits_per_word)
spi->bits_per_word = 8;
davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
if (use_dma && davinci_spi->dma_channels) {
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
if ((davinci_spi_dma->dma_rx_channel == -1)
|| (davinci_spi_dma->dma_tx_channel == -1)) {
retval = davinci_spi_request_dma(spi);
if (retval < 0)
return retval;
}
}
/*
* SPI in DaVinci and DA8xx operate between
* 600 KHz and 50 MHz
*/
if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
dev_dbg(sdev, "Operating frequency is not in acceptable "
"range\n");
return -EINVAL;
}
/*
* Set up SPIFMTn register, unique to this chipselect.
*
* NOTE: we could do all of these with one write. Also, some
* of the "version 2" features are found in chips that don't
* support all of them...
*/
if (spi->mode & SPI_LSB_FIRST)
set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
spi->chip_select);
if (spi->mode & SPI_CPOL)
set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
spi->chip_select);
if (!(spi->mode & SPI_NO_CS)) {
if ((pdata->chip_sel == NULL) ||
(pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
if (!(spi->mode & SPI_CPHA))
set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
spi->chip_select);
/*
* Version 1 hardware supports two basic SPI modes:
* - Standard SPI mode uses 4 pins, with chipselect
* - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
* (distinct from SPI_3WIRE, with just one data wire;
* or similar variants without MOSI or without MISO)
*
* Version 2 hardware supports an optional handshaking signal,
* so it can support two more modes:
* - 5 pin SPI variant is standard SPI plus SPI_READY
* - 4 pin with enable is (SPI_READY | SPI_NO_CS)
*/
if (davinci_spi->version == SPI_VERSION_2) {
clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
spi->chip_select);
set_fmt_bits(davinci_spi->base,
(davinci_spi->pdata->wdelay
<< SPIFMT_WDELAY_SHIFT)
& SPIFMT_WDELAY_MASK,
spi->chip_select);
if (davinci_spi->pdata->odd_parity)
set_fmt_bits(davinci_spi->base,
SPIFMT_ODD_PARITY_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base,
SPIFMT_ODD_PARITY_MASK,
spi->chip_select);
if (davinci_spi->pdata->parity_enable)
set_fmt_bits(davinci_spi->base,
SPIFMT_PARITYENA_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base,
SPIFMT_PARITYENA_MASK,
spi->chip_select);
if (davinci_spi->pdata->wait_enable)
set_fmt_bits(davinci_spi->base,
SPIFMT_WAITENA_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base,
SPIFMT_WAITENA_MASK,
spi->chip_select);
if (davinci_spi->pdata->timer_disable)
set_fmt_bits(davinci_spi->base,
SPIFMT_DISTIMER_MASK,
spi->chip_select);
else
clear_fmt_bits(davinci_spi->base,
SPIFMT_DISTIMER_MASK,
spi->chip_select);
}
retval = davinci_spi_setup_transfer(spi, NULL);
return retval;
}
static void davinci_spi_cleanup(struct spi_device *spi)
{
struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
struct davinci_spi_dma *davinci_spi_dma;
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
if (use_dma && davinci_spi->dma_channels) {
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
if ((davinci_spi_dma->dma_rx_channel != -1)
&& (davinci_spi_dma->dma_tx_channel != -1)) {
edma_free_channel(davinci_spi_dma->dma_tx_channel);
edma_free_channel(davinci_spi_dma->dma_rx_channel);
}
}
}
static int davinci_spi_bufs_prep(struct spi_device *spi,
struct davinci_spi *davinci_spi)
{
int op_mode = 0;
/*
* REVISIT unless devices disagree about SPI_LOOP or
* SPI_READY (SPI_NO_CS only allows one device!), this
* should not need to be done before each message...
* optimize for both flags staying cleared.
*/
op_mode = SPIPC0_DIFUN_MASK
| SPIPC0_DOFUN_MASK
| SPIPC0_CLKFUN_MASK;
if (!(spi->mode & SPI_NO_CS))
op_mode |= 1 << spi->chip_select;
if (spi->mode & SPI_READY)
op_mode |= SPIPC0_SPIENA_MASK;
iowrite32(op_mode, davinci_spi->base + SPIPC0);
set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
if (spi->mode & SPI_LOOP)
set_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_LOOPBACK_MASK);
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
else
clear_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_LOOPBACK_MASK);
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
return 0;
return retval;
}
static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
int int_status)
static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
{
struct device *sdev = davinci_spi->bitbang.master->dev.parent;
struct device *sdev = dspi->bitbang.master->dev.parent;
if (int_status & SPIFLG_TIMEOUT_MASK) {
dev_dbg(sdev, "SPI Time-out Error\n");
......@@ -633,7 +437,7 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
return -EIO;
}
if (davinci_spi->version == SPI_VERSION_2) {
if (dspi->version == SPI_VERSION_2) {
if (int_status & SPIFLG_DLEN_ERR_MASK) {
dev_dbg(sdev, "SPI Data Length Error\n");
return -EIO;
......@@ -646,10 +450,6 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
dev_dbg(sdev, "SPI Data Overrun error\n");
return -EIO;
}
if (int_status & SPIFLG_TX_INTR_MASK) {
dev_dbg(sdev, "SPI TX intr bit set\n");
return -EIO;
}
if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
dev_dbg(sdev, "SPI Buffer Init Active\n");
return -EBUSY;
......@@ -660,366 +460,339 @@ static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
}
/**
* davinci_spi_bufs - functions which will handle transfer data
* @spi: spi device on which data transfer to be done
* @t: spi transfer in which transfer info is filled
* davinci_spi_process_events - check for and handle any SPI controller events
* @dspi: the controller data
*
* This function will put data to be transferred into data register
* of SPI controller and then wait until the completion will be marked
* by the IRQ Handler.
* This function will check the SPIFLG register and handle any events that are
* detected there
*/
static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
static int davinci_spi_process_events(struct davinci_spi *dspi)
{
struct davinci_spi *davinci_spi;
int int_status, count, ret;
u8 conv, tmp;
u32 tx_data, data1_reg_val;
u32 buf_val, flg_val;
struct davinci_spi_platform_data *pdata;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf;
/* convert len to words based on bits_per_word */
conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
davinci_spi->count = t->len / conv;
INIT_COMPLETION(davinci_spi->done);
ret = davinci_spi_bufs_prep(spi, davinci_spi);
if (ret)
return ret;
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
count = davinci_spi->count;
data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
tmp = ~(0x1 << spi->chip_select);
clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
u32 buf, status, errors = 0, spidat1;
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
buf = ioread32(dspi->base + SPIBUF);
/* Determine the command to execute READ or WRITE */
if (t->tx_buf) {
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
dspi->get_rx(buf & 0xFFFF, dspi);
dspi->rcount--;
}
while (1) {
tx_data = davinci_spi->get_tx(davinci_spi);
status = ioread32(dspi->base + SPIFLG);
data1_reg_val &= ~(0xFFFF);
data1_reg_val |= (0xFFFF & tx_data);
if (unlikely(status & SPIFLG_ERROR_MASK)) {
errors = status & SPIFLG_ERROR_MASK;
goto out;
}
buf_val = ioread32(davinci_spi->base + SPIBUF);
if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
spidat1 = ioread32(dspi->base + SPIDAT1);
dspi->wcount--;
spidat1 &= ~0xFFFF;
spidat1 |= 0xFFFF & dspi->get_tx(dspi);
iowrite32(spidat1, dspi->base + SPIDAT1);
}
count--;
}
while (ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK)
cpu_relax();
/* getting the returned byte */
if (t->rx_buf) {
buf_val = ioread32(davinci_spi->base + SPIBUF);
davinci_spi->get_rx(buf_val, davinci_spi);
}
if (count <= 0)
break;
}
} else {
if (pdata->poll_mode) {
while (1) {
/* keeps the serial clock going */
if ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_TXFULL_MASK) == 0)
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
while (ioread32(davinci_spi->base + SPIBUF) &
SPIBUF_RXEMPTY_MASK)
cpu_relax();
flg_val = ioread32(davinci_spi->base + SPIFLG);
buf_val = ioread32(davinci_spi->base + SPIBUF);
davinci_spi->get_rx(buf_val, davinci_spi);
count--;
if (count <= 0)
break;
}
} else { /* Receive in Interrupt mode */
int i;
out:
return errors;
}
for (i = 0; i < davinci_spi->count; i++) {
set_io_bits(davinci_spi->base + SPIINT,
SPIINT_BITERR_INTR
| SPIINT_OVRRUN_INTR
| SPIINT_RX_INTR);
static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
{
struct davinci_spi *dspi = data;
struct davinci_spi_dma *dma = &dspi->dma;
iowrite32(data1_reg_val,
davinci_spi->base + SPIDAT1);
edma_stop(lch);
while (ioread32(davinci_spi->base + SPIINT) &
SPIINT_RX_INTR)
cpu_relax();
}
iowrite32((data1_reg_val & 0x0ffcffff),
davinci_spi->base + SPIDAT1);
}
if (status == DMA_COMPLETE) {
if (lch == dma->rx_channel)
dspi->rcount = 0;
if (lch == dma->tx_channel)
dspi->wcount = 0;
}
/*
* Check for bit error, desync error,parity error,timeout error and
* receive overflow errors
*/
int_status = ioread32(davinci_spi->base + SPIFLG);
ret = davinci_spi_check_error(davinci_spi, int_status);
if (ret != 0)
return ret;
/* SPI Framework maintains the count only in bytes so convert back */
davinci_spi->count *= conv;
return t->len;
if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
complete(&dspi->done);
}
#define DAVINCI_DMA_DATA_TYPE_S8 0x01
#define DAVINCI_DMA_DATA_TYPE_S16 0x02
#define DAVINCI_DMA_DATA_TYPE_S32 0x04
static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
/**
* davinci_spi_bufs - functions which will handle transfer data
* @spi: spi device on which data transfer to be done
* @t: spi transfer in which transfer info is filled
*
* This function will put data to be transferred into data register
* of SPI controller and then wait until the completion will be marked
* by the IRQ Handler.
*/
static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
struct davinci_spi *davinci_spi;
int int_status = 0;
int count, temp_count;
u8 conv = 1;
u8 tmp;
u32 data1_reg_val;
struct davinci_spi_dma *davinci_spi_dma;
int word_len, data_type, ret;
unsigned long tx_reg, rx_reg;
struct davinci_spi *dspi;
int data_type, ret;
u32 tx_data, spidat1;
u32 errors = 0;
struct davinci_spi_config *spicfg;
struct davinci_spi_platform_data *pdata;
unsigned uninitialized_var(rx_buf_count);
struct device *sdev;
davinci_spi = spi_master_get_devdata(spi->master);
pdata = davinci_spi->pdata;
sdev = davinci_spi->bitbang.master->dev.parent;
davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
davinci_spi->tx = t->tx_buf;
davinci_spi->rx = t->rx_buf;
dspi = spi_master_get_devdata(spi->master);
pdata = dspi->pdata;
spicfg = (struct davinci_spi_config *)spi->controller_data;
if (!spicfg)
spicfg = &davinci_spi_default_cfg;
sdev = dspi->bitbang.master->dev.parent;
/* convert len to words based on bits_per_word */
conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
davinci_spi->count = t->len / conv;
INIT_COMPLETION(davinci_spi->done);
data_type = dspi->bytes_per_word[spi->chip_select];
init_completion(&davinci_spi_dma->dma_rx_completion);
init_completion(&davinci_spi_dma->dma_tx_completion);
dspi->tx = t->tx_buf;
dspi->rx = t->rx_buf;
dspi->wcount = t->len / data_type;
dspi->rcount = dspi->wcount;
word_len = conv * 8;
if (word_len <= 8)
data_type = DAVINCI_DMA_DATA_TYPE_S8;
else if (word_len <= 16)
data_type = DAVINCI_DMA_DATA_TYPE_S16;
else if (word_len <= 32)
data_type = DAVINCI_DMA_DATA_TYPE_S32;
else
return -EINVAL;
ret = davinci_spi_bufs_prep(spi, davinci_spi);
if (ret)
return ret;
spidat1 = ioread32(dspi->base + SPIDAT1);
/* Put delay val if required */
iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
(pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
davinci_spi->base + SPIDELAY);
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
count = davinci_spi->count; /* the number of elements */
data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
INIT_COMPLETION(dspi->done);
/* CS default = 0xFF */
tmp = ~(0x1 << spi->chip_select);
if (spicfg->io_type == SPI_IO_TYPE_INTR)
set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
/* disable all interrupts for dma transfers */
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
/* Disable SPI to write configuration bits in SPIDAT */
clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
while ((ioread32(davinci_spi->base + SPIBUF)
& SPIBUF_RXEMPTY_MASK) == 0)
cpu_relax();
if (t->tx_buf) {
t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX buffer\n", count);
return -ENOMEM;
}
temp_count = count;
if (spicfg->io_type != SPI_IO_TYPE_DMA) {
/* start the transfer */
dspi->wcount--;
tx_data = dspi->get_tx(dspi);
spidat1 &= 0xFFFF0000;
spidat1 |= tx_data & 0xFFFF;
iowrite32(spidat1, dspi->base + SPIDAT1);
} else {
/* We need TX clocking for RX transaction */
t->tx_dma = dma_map_single(&spi->dev,
(void *)davinci_spi->tmp_buf, count + 1,
DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map a %d bytes"
" TX tmp buffer\n", count);
return -ENOMEM;
struct davinci_spi_dma *dma;
unsigned long tx_reg, rx_reg;
struct edmacc_param param;
void *rx_buf;
dma = &dspi->dma;
tx_reg = (unsigned long)dspi->pbase + SPIDAT1;
rx_reg = (unsigned long)dspi->pbase + SPIBUF;
/*
* Transmit DMA setup
*
* If there is transmit data, map the transmit buffer, set it
* as the source of data and set the source B index to data
* size. If there is no transmit data, set the transmit register
* as the source of data, and set the source B index to zero.
*
* The destination is always the transmit register itself. And
* the destination never increments.
*/
if (t->tx_buf) {
t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf,
dspi->wcount, DMA_TO_DEVICE);
if (dma_mapping_error(&spi->dev, t->tx_dma)) {
dev_dbg(sdev, "Unable to DMA map %d bytes"
"TX buffer\n", dspi->wcount);
return -ENOMEM;
}
}
temp_count = count + 1;
}
edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
data_type, temp_count, 1, 0, ASYNC);
edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
if (t->rx_buf) {
/* initiate transaction */
iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
param.src = t->tx_buf ? t->tx_dma : tx_reg;
param.a_b_cnt = dspi->wcount << 16 | data_type;
param.dst = tx_reg;
param.src_dst_bidx = t->tx_buf ? data_type : 0;
param.link_bcntrld = 0xffff;
param.src_dst_cidx = 0;
param.ccnt = 1;
edma_write_slot(dma->tx_channel, &param);
edma_link(dma->tx_channel, dma->dummy_param_slot);
/*
* Receive DMA setup
*
* If there is receive buffer, use it to receive data. If there
* is none provided, use a temporary receive buffer. Set the
* destination B index to 0 so effectively only one byte is used
* in the temporary buffer (address does not increment).
*
* The source of receive data is the receive data register. The
* source address never increments.
*/
if (t->rx_buf) {
rx_buf = t->rx_buf;
rx_buf_count = dspi->rcount;
} else {
rx_buf = dspi->rx_tmp_buf;
rx_buf_count = sizeof(dspi->rx_tmp_buf);
}
t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
DMA_FROM_DEVICE);
t->rx_dma = dma_map_single(&spi->dev, rx_buf, rx_buf_count,
DMA_FROM_DEVICE);
if (dma_mapping_error(&spi->dev, t->rx_dma)) {
dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
count);
if (t->tx_buf != NULL)
dma_unmap_single(NULL, t->tx_dma,
count, DMA_TO_DEVICE);
rx_buf_count);
if (t->tx_buf)
dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
DMA_TO_DEVICE);
return -ENOMEM;
}
edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
data_type, count, 1, 0, ASYNC);
edma_set_src(davinci_spi_dma->dma_rx_channel,
rx_reg, INCR, W8BIT);
edma_set_dest(davinci_spi_dma->dma_rx_channel,
t->rx_dma, INCR, W8BIT);
edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
data_type, 0);
}
if ((t->tx_buf) || (t->rx_buf))
edma_start(davinci_spi_dma->dma_tx_channel);
param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
param.src = rx_reg;
param.a_b_cnt = dspi->rcount << 16 | data_type;
param.dst = t->rx_dma;
param.src_dst_bidx = (t->rx_buf ? data_type : 0) << 16;
param.link_bcntrld = 0xffff;
param.src_dst_cidx = 0;
param.ccnt = 1;
edma_write_slot(dma->rx_channel, &param);
if (pdata->cshold_bug)
iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
edma_start(dma->rx_channel);
edma_start(dma->tx_channel);
set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
}
if (t->rx_buf)
edma_start(davinci_spi_dma->dma_rx_channel);
/* Wait for the transfer to complete */
if (spicfg->io_type != SPI_IO_TYPE_POLL) {
wait_for_completion_interruptible(&(dspi->done));
} else {
while (dspi->rcount > 0 || dspi->wcount > 0) {
errors = davinci_spi_process_events(dspi);
if (errors)
break;
cpu_relax();
}
}
if ((t->rx_buf) || (t->tx_buf))
davinci_spi_set_dma_req(spi, 1);
clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
if (spicfg->io_type == SPI_IO_TYPE_DMA) {
if (t->tx_buf)
wait_for_completion_interruptible(
&davinci_spi_dma->dma_tx_completion);
if (t->tx_buf)
dma_unmap_single(NULL, t->tx_dma, dspi->wcount,
DMA_TO_DEVICE);
if (t->rx_buf)
wait_for_completion_interruptible(
&davinci_spi_dma->dma_rx_completion);
dma_unmap_single(NULL, t->rx_dma, rx_buf_count,
DMA_FROM_DEVICE);
dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
}
if (t->rx_buf)
dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
/*
* Check for bit error, desync error,parity error,timeout error and
* receive overflow errors
*/
int_status = ioread32(davinci_spi->base + SPIFLG);
ret = davinci_spi_check_error(davinci_spi, int_status);
if (ret != 0)
if (errors) {
ret = davinci_spi_check_error(dspi, errors);
WARN(!ret, "%s: error reported but no error found!\n",
dev_name(&spi->dev));
return ret;
}
/* SPI Framework maintains the count only in bytes so convert back */
davinci_spi->count *= conv;
if (dspi->rcount != 0 || dspi->wcount != 0) {
dev_err(sdev, "SPI data transfer error\n");
return -EIO;
}
return t->len;
}
/**
* davinci_spi_irq - IRQ handler for DaVinci SPI
* davinci_spi_irq - Interrupt handler for SPI Master Controller
* @irq: IRQ number for this SPI Master
* @context_data: structure for SPI Master controller davinci_spi
*
* ISR will determine that interrupt arrives either for READ or WRITE command.
* According to command it will do the appropriate action. It will check
* transfer length and if it is not zero then dispatch transfer command again.
* If transfer length is zero then it will indicate the COMPLETION so that
* davinci_spi_bufs function can go ahead.
*/
static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
static irqreturn_t davinci_spi_irq(s32 irq, void *data)
{
struct davinci_spi *davinci_spi = context_data;
u32 int_status, rx_data = 0;
irqreturn_t ret = IRQ_NONE;
struct davinci_spi *dspi = data;
int status;
int_status = ioread32(davinci_spi->base + SPIFLG);
status = davinci_spi_process_events(dspi);
if (unlikely(status != 0))
clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
while ((int_status & SPIFLG_RX_INTR_MASK)) {
if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
ret = IRQ_HANDLED;
if ((!dspi->rcount && !dspi->wcount) || status)
complete(&dspi->done);
rx_data = ioread32(davinci_spi->base + SPIBUF);
davinci_spi->get_rx(rx_data, davinci_spi);
return IRQ_HANDLED;
}
/* Disable Receive Interrupt */
iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
davinci_spi->base + SPIINT);
} else
(void)davinci_spi_check_error(davinci_spi, int_status);
static int davinci_spi_request_dma(struct davinci_spi *dspi)
{
int r;
struct davinci_spi_dma *dma = &dspi->dma;
int_status = ioread32(davinci_spi->base + SPIFLG);
r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
dma->eventq);
if (r < 0) {
pr_err("Unable to request DMA channel for SPI RX\n");
r = -EAGAIN;
goto rx_dma_failed;
}
return ret;
r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
dma->eventq);
if (r < 0) {
pr_err("Unable to request DMA channel for SPI TX\n");
r = -EAGAIN;
goto tx_dma_failed;
}
r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
if (r < 0) {
pr_err("Unable to request SPI TX DMA param slot\n");
r = -EAGAIN;
goto param_failed;
}
dma->dummy_param_slot = r;
edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
return 0;
param_failed:
edma_free_channel(dma->tx_channel);
tx_dma_failed:
edma_free_channel(dma->rx_channel);
rx_dma_failed:
return r;
}
/**
* davinci_spi_probe - probe function for SPI Master Controller
* @pdev: platform_device structure which contains plateform specific data
*
* According to Linux Device Model this function will be invoked by Linux
* with platform_device struct which contains the device specific info.
* This function will map the SPI controller's memory, register IRQ,
* Reset SPI controller and setting its registers to default value.
* It will invoke spi_bitbang_start to create work queue so that client driver
* can register transfer method to work queue.
*/
static int davinci_spi_probe(struct platform_device *pdev)
{
struct spi_master *master;
struct davinci_spi *davinci_spi;
struct davinci_spi *dspi;
struct davinci_spi_platform_data *pdata;
struct resource *r, *mem;
resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
resource_size_t dma_eventq = SPI_NO_RESOURCE;
int i = 0, ret = 0;
u32 spipc0;
pdata = pdev->dev.platform_data;
if (pdata == NULL) {
......@@ -1035,8 +808,8 @@ static int davinci_spi_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, master);
davinci_spi = spi_master_get_devdata(master);
if (davinci_spi == NULL) {
dspi = spi_master_get_devdata(master);
if (dspi == NULL) {
ret = -ENOENT;
goto free_master;
}
......@@ -1047,164 +820,143 @@ static int davinci_spi_probe(struct platform_device *pdev)
goto free_master;
}
davinci_spi->pbase = r->start;
davinci_spi->region_size = resource_size(r);
davinci_spi->pdata = pdata;
dspi->pbase = r->start;
dspi->pdata = pdata;
mem = request_mem_region(r->start, davinci_spi->region_size,
pdev->name);
mem = request_mem_region(r->start, resource_size(r), pdev->name);
if (mem == NULL) {
ret = -EBUSY;
goto free_master;
}
davinci_spi->base = (struct davinci_spi_reg __iomem *)
ioremap(r->start, davinci_spi->region_size);
if (davinci_spi->base == NULL) {
dspi->base = ioremap(r->start, resource_size(r));
if (dspi->base == NULL) {
ret = -ENOMEM;
goto release_region;
}
davinci_spi->irq = platform_get_irq(pdev, 0);
if (davinci_spi->irq <= 0) {
dspi->irq = platform_get_irq(pdev, 0);
if (dspi->irq <= 0) {
ret = -EINVAL;
goto unmap_io;
}
ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
dev_name(&pdev->dev), davinci_spi);
ret = request_irq(dspi->irq, davinci_spi_irq, 0, dev_name(&pdev->dev),
dspi);
if (ret)
goto unmap_io;
/* Allocate tmp_buf for tx_buf */
davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
if (davinci_spi->tmp_buf == NULL) {
ret = -ENOMEM;
goto irq_free;
}
davinci_spi->bitbang.master = spi_master_get(master);
if (davinci_spi->bitbang.master == NULL) {
dspi->bitbang.master = spi_master_get(master);
if (dspi->bitbang.master == NULL) {
ret = -ENODEV;
goto free_tmp_buf;
goto irq_free;
}
davinci_spi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(davinci_spi->clk)) {
dspi->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(dspi->clk)) {
ret = -ENODEV;
goto put_master;
}
clk_enable(davinci_spi->clk);
clk_enable(dspi->clk);
master->bus_num = pdev->id;
master->num_chipselect = pdata->num_chipselect;
master->setup = davinci_spi_setup;
master->cleanup = davinci_spi_cleanup;
davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
davinci_spi->version = pdata->version;
use_dma = pdata->use_dma;
davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
if (davinci_spi->version == SPI_VERSION_2)
davinci_spi->bitbang.flags |= SPI_READY;
if (use_dma) {
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (r)
dma_rx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (r)
dma_tx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
if (r)
dma_eventq = r->start;
}
if (!use_dma ||
dma_rx_chan == SPI_NO_RESOURCE ||
dma_tx_chan == SPI_NO_RESOURCE ||
dma_eventq == SPI_NO_RESOURCE) {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
use_dma = 0;
} else {
davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
davinci_spi->dma_channels = kzalloc(master->num_chipselect
* sizeof(struct davinci_spi_dma), GFP_KERNEL);
if (davinci_spi->dma_channels == NULL) {
ret = -ENOMEM;
dspi->bitbang.chipselect = davinci_spi_chipselect;
dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
dspi->version = pdata->version;
dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
if (dspi->version == SPI_VERSION_2)
dspi->bitbang.flags |= SPI_READY;
r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (r)
dma_rx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
if (r)
dma_tx_chan = r->start;
r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
if (r)
dma_eventq = r->start;
dspi->bitbang.txrx_bufs = davinci_spi_bufs;
if (dma_rx_chan != SPI_NO_RESOURCE &&
dma_tx_chan != SPI_NO_RESOURCE &&
dma_eventq != SPI_NO_RESOURCE) {
dspi->dma.rx_channel = dma_rx_chan;
dspi->dma.tx_channel = dma_tx_chan;
dspi->dma.eventq = dma_eventq;
ret = davinci_spi_request_dma(dspi);
if (ret)
goto free_clk;
}
for (i = 0; i < master->num_chipselect; i++) {
davinci_spi->dma_channels[i].dma_rx_channel = -1;
davinci_spi->dma_channels[i].dma_rx_sync_dev =
dma_rx_chan;
davinci_spi->dma_channels[i].dma_tx_channel = -1;
davinci_spi->dma_channels[i].dma_tx_sync_dev =
dma_tx_chan;
davinci_spi->dma_channels[i].eventq = dma_eventq;
}
dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
"Using RX channel = %d , TX channel = %d and "
"event queue = %d", dma_rx_chan, dma_tx_chan,
dev_info(&pdev->dev, "DMA: supported\n");
dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
"event queue: %d\n", dma_rx_chan, dma_tx_chan,
dma_eventq);
}
davinci_spi->get_rx = davinci_spi_rx_buf_u8;
davinci_spi->get_tx = davinci_spi_tx_buf_u8;
dspi->get_rx = davinci_spi_rx_buf_u8;
dspi->get_tx = davinci_spi_tx_buf_u8;
init_completion(&davinci_spi->done);
init_completion(&dspi->done);
/* Reset In/OUT SPI module */
iowrite32(0, davinci_spi->base + SPIGCR0);
iowrite32(0, dspi->base + SPIGCR0);
udelay(100);
iowrite32(1, davinci_spi->base + SPIGCR0);
iowrite32(1, dspi->base + SPIGCR0);
/* Clock internal */
if (davinci_spi->pdata->clk_internal)
set_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
else
clear_io_bits(davinci_spi->base + SPIGCR1,
SPIGCR1_CLKMOD_MASK);
/* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
iowrite32(spipc0, dspi->base + SPIPC0);
/* master mode default */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
/* initialize chip selects */
if (pdata->chip_sel) {
for (i = 0; i < pdata->num_chipselect; i++) {
if (pdata->chip_sel[i] != SPI_INTERN_CS)
gpio_direction_output(pdata->chip_sel[i], 1);
}
}
if (davinci_spi->pdata->intr_level)
iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
if (pdata->intr_line)
iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
else
iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
ret = spi_bitbang_start(&davinci_spi->bitbang);
if (ret)
goto free_clk;
iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
/* master mode default */
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
ret = spi_bitbang_start(&dspi->bitbang);
if (ret)
goto free_dma;
if (!pdata->poll_mode)
dev_info(&pdev->dev, "Operating in interrupt mode"
" using IRQ %d\n", davinci_spi->irq);
dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
return ret;
free_dma:
edma_free_channel(dspi->dma.tx_channel);
edma_free_channel(dspi->dma.rx_channel);
edma_free_slot(dspi->dma.dummy_param_slot);
free_clk:
clk_disable(davinci_spi->clk);
clk_put(davinci_spi->clk);
clk_disable(dspi->clk);
clk_put(dspi->clk);
put_master:
spi_master_put(master);
free_tmp_buf:
kfree(davinci_spi->tmp_buf);
irq_free:
free_irq(davinci_spi->irq, davinci_spi);
free_irq(dspi->irq, dspi);
unmap_io:
iounmap(davinci_spi->base);
iounmap(dspi->base);
release_region:
release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
release_mem_region(dspi->pbase, resource_size(r));
free_master:
kfree(master);
err:
......@@ -1222,27 +974,31 @@ static int davinci_spi_probe(struct platform_device *pdev)
*/
static int __exit davinci_spi_remove(struct platform_device *pdev)
{
struct davinci_spi *davinci_spi;
struct davinci_spi *dspi;
struct spi_master *master;
struct resource *r;
master = dev_get_drvdata(&pdev->dev);
davinci_spi = spi_master_get_devdata(master);
dspi = spi_master_get_devdata(master);
spi_bitbang_stop(&davinci_spi->bitbang);
spi_bitbang_stop(&dspi->bitbang);
clk_disable(davinci_spi->clk);
clk_put(davinci_spi->clk);
clk_disable(dspi->clk);
clk_put(dspi->clk);
spi_master_put(master);
kfree(davinci_spi->tmp_buf);
free_irq(davinci_spi->irq, davinci_spi);
iounmap(davinci_spi->base);
release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
free_irq(dspi->irq, dspi);
iounmap(dspi->base);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(dspi->pbase, resource_size(r));
return 0;
}
static struct platform_driver davinci_spi_driver = {
.driver.name = "spi_davinci",
.driver = {
.name = "spi_davinci",
.owner = THIS_MODULE,
},
.remove = __exit_p(davinci_spi_remove),
};
......
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