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Commit 4af46b7b authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
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arm64: dts: qcom: x1e80100: Add USB nodes 

Add nodes for all USB controllers and their PHYs for X1E80100 platform.
Co-developed-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: default avatarSibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarRajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240129-x1e80100-dts-missing-nodes-v6-6-2c0e691cfa3b@linaro.orgSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8b6e2bf9
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Showing with 450 additions and 3 deletions
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View file @ 4af46b7b
......@@ -5,11 +5,13 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
......@@ -742,9 +744,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
......@@ -2500,6 +2502,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
usb_1_ss0_hsphy: phy@fd3000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
reg = <0 0x00fd3000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
status = "disabled";
};
usb_1_ss0_qmpphy: phy@fd5000 {
compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
reg = <0 0x00fd5000 0 0x4000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
reset-names = "phy",
"common";
#clock-cells = <1>;
#phy-cells = <1>;
status = "disabled";
};
usb_1_ss1_hsphy: phy@fd9000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
reg = <0 0x00fd9000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
status = "disabled";
};
usb_1_ss1_qmpphy: phy@fda000 {
compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
reg = <0 0x00fda000 0 0x4000>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
reset-names = "phy",
"common";
#clock-cells = <1>;
#phy-cells = <1>;
status = "disabled";
};
usb_1_ss2_hsphy: phy@fde000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
reg = <0 0x00fde000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
status = "disabled";
};
usb_1_ss2_qmpphy: phy@fdf000 {
compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
reg = <0 0x00fdf000 0 0x4000>;
clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
clock-names = "aux",
"ref",
"com_aux",
"usb3_pipe";
power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
<&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
reset-names = "phy",
"common";
#clock-cells = <1>;
#phy-cells = <1>;
status = "disabled";
};
cnoc_main: interconnect@1500000 {
compatible = "qcom,x1e80100-cnoc-main";
reg = <0 0x1500000 0 0x14400>;
......@@ -2667,6 +2789,331 @@ lpass_lpicx_noc: interconnect@7430000 {
#interconnect-cells = <2>;
};
usb_2_hsphy: phy@88e0000 {
compatible = "qcom,x1e80100-snps-eusb2-phy",
"qcom,sm8550-snps-eusb2-phy";
reg = <0 0x088e0000 0 0x154>;
#phy-cells = <0>;
clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
status = "disabled";
};
usb_1_ss2: usb@a0f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a0f8800 0 0x400>;
clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
<&gcc GCC_USB30_TERT_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
<&gcc GCC_USB30_TERT_SLEEP_CLK>,
<&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr",
"noc_aggr_north",
"noc_aggr_south",
"noc_sys";
assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_TERT_MASTER_CLK>;
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 58 IRQ_TYPE_EDGE_BOTH>,
<&pdc 57 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_TERT_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_TERT_BCR>;
interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "usb-ddr",
"apps-usb";
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_1_ss2_dwc3: usb@a000000 {
compatible = "snps,dwc3";
reg = <0 0x0a000000 0 0xcd00>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x14a0 0x0>;
phys = <&usb_1_ss2_hsphy>,
<&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
dma-coherent;
port {
usb_1_ss2_role_switch: endpoint {
};
};
};
};
usb_2: usb@a2f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a2f8800 0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_USB20_SLEEP_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr",
"noc_aggr_north",
"noc_aggr_south",
"noc_sys";
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 50 IRQ_TYPE_EDGE_BOTH>,
<&pdc 49 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq";
power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB20_PRIM_BCR>;
interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "usb-ddr",
"apps-usb";
wakeup-source;
status = "disabled";
usb_2_dwc3: usb@a200000 {
compatible = "snps,dwc3";
reg = <0 0x0a200000 0 0xcd00>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x14e0 0x0>;
phys = <&usb_2_hsphy>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
port {
usb_2_role_switch: endpoint {
};
};
};
};
usb_1_ss0: usb@a6f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
<&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr",
"noc_aggr_north",
"noc_aggr_south",
"noc_sys";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 61 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_1_ss0_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x1420 0x0>;
phys = <&usb_1_ss0_hsphy>,
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
dma-coherent;
port {
usb_1_ss0_role_switch: endpoint {
};
};
};
};
usb_1_ss1: usb@a8f8800 {
compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400>;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
<&gcc GCC_SYS_NOC_USB_AXI_CLK>;
clock-names = "cfg_noc",
"core",
"iface",
"sleep",
"mock_utmi",
"noc_aggr",
"noc_aggr_north",
"noc_aggr_south",
"noc_sys";
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>,
<200000000>;
interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 60 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event",
"dp_hs_phy_irq",
"dm_hs_phy_irq",
"ss_phy_irq";
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
resets = <&gcc GCC_USB30_SEC_BCR>;
interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "usb-ddr",
"apps-usb";
wakeup-source;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_1_ss1_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x1460 0x0>;
phys = <&usb_1_ss1_hsphy>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy",
"usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,usb3_lpm_capable;
dma-coherent;
port {
usb_1_ss1_role_switch: endpoint {
};
};
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
......
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