Commit 4b36daf9 authored by Dinh Nguyen's avatar Dinh Nguyen

arm64: dts: agilex: Add initial support for Intel's Agilex SoCFPGA

Add the initial device tree files for Intel's Agilex SoCFPGA platform.
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
parent 5fc670a8
......@@ -7,6 +7,11 @@ config ARCH_ACTIONS
help
This enables support for the Actions Semiconductor S900 SoC family.
config ARCH_AGILEX
bool "Intel's Agilex SoCFPGA Family"
help
This enables support for Intel's Agilex SoCFPGA Family.
config ARCH_SUNXI
bool "Allwinner sunxi 64-bit SoC Family"
select ARCH_HAS_RESET_CONTROLLER
......
......@@ -13,6 +13,7 @@ subdir-y += cavium
subdir-y += exynos
subdir-y += freescale
subdir-y += hisilicon
subdir-y += intel
subdir-y += lg
subdir-y += marvell
subdir-y += mediatek
......
dtb-$(CONFIG_ARCH_AGILEX) += socfpga_agilex_socdk.dtb
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
/ {
model = "SoCFPGA Agilex SoCDK";
aliases {
serial0 = &uart0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
ethernet2 = &gmac2;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
};
&gpio1 {
status = "okay";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;
max-frame-size = <9000>;
mdio0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {
reg = <4>;
txd0-skew-ps = <0>; /* -420ps */
txd1-skew-ps = <0>; /* -420ps */
txd2-skew-ps = <0>; /* -420ps */
txd3-skew-ps = <0>; /* -420ps */
rxd0-skew-ps = <420>; /* 0ps */
rxd1-skew-ps = <420>; /* 0ps */
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};
};
};
&mmc {
status = "okay";
cap-sd-highspeed;
broken-cd;
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&watchdog0 {
status = "okay";
};
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