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Commit 4cd4b361 authored by David S. Miller's avatar David S. Miller
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Merge branch 'bnxt_en-Update-for-net-next' 

Michael Chan says:

====================
bnxt_en: Update for net-next.

This patch series adds 2 main features to the bnxt_en driver: 200G
link speed support and FEC support with some refactoring of the
link speed logic.  The firmware interface is updated to have proper
support for these 2 features.  The ethtool preset max channel value
is also adjusted properly to account for XDP and TCs.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e6221295 4301304b
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drivers/net/ethernet/broadcom/bnxt/bnxt.c
View file @ 4cd4b361
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drivers/net/ethernet/broadcom/bnxt/bnxt.h
View file @ 4cd4b361
......@@ -1142,50 +1142,6 @@ struct bnxt_ntuple_filter {
#define BNXT_FLTR_UPDATE 1
};
struct hwrm_port_phy_qcfg_output_compat {
__le16 error_code;
__le16 req_type;
__le16 seq_id;
__le16 resp_len;
u8 link;
u8 link_signal_mode;
__le16 link_speed;
u8 duplex_cfg;
u8 pause;
__le16 support_speeds;
__le16 force_link_speed;
u8 auto_mode;
u8 auto_pause;
__le16 auto_link_speed;
__le16 auto_link_speed_mask;
u8 wirespeed;
u8 lpbk;
u8 force_pause;
u8 module_status;
__le32 preemphasis;
u8 phy_maj;
u8 phy_min;
u8 phy_bld;
u8 phy_type;
u8 media_type;
u8 xcvr_pkg_type;
u8 eee_config_phy_addr;
u8 parallel_detect;
__le16 link_partner_adv_speeds;
u8 link_partner_adv_auto_mode;
u8 link_partner_adv_pause;
__le16 adv_eee_link_speed_mask;
__le16 link_partner_adv_eee_link_speed_mask;
__le32 xcvr_identifier_type_tx_lpi_timer;
__le16 fec_cfg;
u8 duplex_state;
u8 option_flags;
char phy_vendor_name[16];
char phy_vendor_partnumber[16];
u8 unused_0[7];
u8 valid;
};
struct bnxt_link_info {
u8 phy_type;
u8 media_type;
......@@ -1196,7 +1152,10 @@ struct bnxt_link_info {
#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
u8 wire_speed;
u8 loop_back;
u8 phy_state;
#define BNXT_PHY_STATE_ENABLED 0
#define BNXT_PHY_STATE_DISABLED 1
u8 link_up;
u8 duplex;
#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
......@@ -1232,6 +1191,7 @@ struct bnxt_link_info {
#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
u16 support_speeds;
u16 support_pam4_speeds;
u16 auto_link_speeds; /* fw adv setting */
#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
......@@ -1243,24 +1203,51 @@ struct bnxt_link_info {
#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
u16 auto_pam4_link_speeds;
#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G
#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G
#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G
u16 support_auto_speeds;
u16 support_pam4_auto_speeds;
u16 lp_auto_link_speeds;
u16 lp_auto_pam4_link_speeds;
u16 force_link_speed;
u16 force_pam4_link_speed;
u32 preemphasis;
u8 module_status;
u8 active_fec_sig_mode;
u16 fec_cfg;
#define BNXT_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED
#define BNXT_FEC_AUTONEG_CAP PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED
#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
#define BNXT_FEC_ENC_BASE_R_CAP \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED
#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
#define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
#define BNXT_FEC_ENC_RS_CAP \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED
#define BNXT_FEC_ENC_LLRS_CAP \
(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)
#define BNXT_FEC_ENC_RS \
(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)
#define BNXT_FEC_ENC_LLRS \
(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \
PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)
/* copy of requested setting from ethtool cmd */
u8 autoneg;
#define BNXT_AUTONEG_SPEED 1
#define BNXT_AUTONEG_FLOW_CTRL 2
u8 req_signal_mode;
#define BNXT_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ
#define BNXT_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
u8 req_duplex;
u8 req_flow_ctrl;
u16 req_link_speed;
u16 advertising; /* user adv setting */
u16 advertising_pam4;
bool force_link_chng;
bool phy_retry;
......@@ -1272,6 +1259,49 @@ struct bnxt_link_info {
struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
};
#define BNXT_FEC_RS544_ON \
(PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)
#define BNXT_FEC_RS544_OFF \
(PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)
#define BNXT_FEC_RS272_ON \
(PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)
#define BNXT_FEC_RS272_OFF \
(PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)
#define BNXT_PAM4_SUPPORTED(link_info) \
((link_info)->support_pam4_speeds)
#define BNXT_FEC_RS_ON(link_info) \
(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
(BNXT_PAM4_SUPPORTED(link_info) ? \
(BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))
#define BNXT_FEC_LLRS_ON \
(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE | \
PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)
#define BNXT_FEC_RS_OFF(link_info) \
(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE | \
(BNXT_PAM4_SUPPORTED(link_info) ? \
(BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))
#define BNXT_FEC_BASE_R_ON(link_info) \
(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE | \
BNXT_FEC_RS_OFF(link_info))
#define BNXT_FEC_ALL_OFF(link_info) \
(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE | \
BNXT_FEC_RS_OFF(link_info))
#define BNXT_MAX_QUEUE 8
struct bnxt_queue_info {
......@@ -1535,6 +1565,8 @@ struct bnxt {
u8 chip_rev;
#define CHIP_NUM_58818 0xd818
#define BNXT_CHIP_NUM_5730X(chip_num) \
((chip_num) >= CHIP_NUM_57301 && \
(chip_num) <= CHIP_NUM_57304)
......@@ -1613,6 +1645,7 @@ struct bnxt {
BNXT_FLAG_ROCEV2_CAP)
#define BNXT_FLAG_NO_AGG_RINGS 0x20000
#define BNXT_FLAG_RX_PAGE_MODE 0x40000
#define BNXT_FLAG_CHIP_SR2 0x80000
#define BNXT_FLAG_MULTI_HOST 0x100000
#define BNXT_FLAG_DSN_VALID 0x200000
#define BNXT_FLAG_DOUBLE_DB 0x400000
......@@ -1630,20 +1663,27 @@ struct bnxt {
#define BNXT_NPAR(bp) ((bp)->port_partition_type)
#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
#define BNXT_PHY_CFG_ABLE(bp) (BNXT_SINGLE_PF(bp) || \
((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG))
#define BNXT_PHY_CFG_ABLE(bp) ((BNXT_SINGLE_PF(bp) || \
((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \
(bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)
#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
(!((bp)->flags & BNXT_FLAG_CHIP_P5) || \
(bp)->max_tpa_v2) && !is_kdump_kernel())
/* Chip class phase 5 */
#define BNXT_CHIP_P5(bp) \
#define BNXT_CHIP_SR2(bp) \
((bp)->chip_num == CHIP_NUM_58818)
#define BNXT_CHIP_P5_THOR(bp) \
((bp)->chip_num == CHIP_NUM_57508 || \
(bp)->chip_num == CHIP_NUM_57504 || \
(bp)->chip_num == CHIP_NUM_57502)
/* Chip class phase 5 */
#define BNXT_CHIP_P5(bp) \
(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))
/* Chip class phase 4.x */
#define BNXT_CHIP_P4(bp) \
(BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
......@@ -1935,6 +1975,20 @@ struct bnxt {
struct device *hwmon_dev;
};
#define BNXT_NUM_RX_RING_STATS 8
#define BNXT_NUM_TX_RING_STATS 8
#define BNXT_NUM_TPA_RING_STATS 4
#define BNXT_NUM_TPA_RING_STATS_P5 5
#define BNXT_NUM_TPA_RING_STATS_P5_SR2 6
#define BNXT_RING_STATS_SIZE_P5 \
((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
BNXT_NUM_TPA_RING_STATS_P5) * 8)
#define BNXT_RING_STATS_SIZE_P5_SR2 \
((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS + \
BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)
#define BNXT_GET_RING_STATS64(sw, counter) \
(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
......@@ -2114,6 +2168,7 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num);
int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
void bnxt_tx_disable(struct bnxt *bp);
void bnxt_tx_enable(struct bnxt *bp);
int bnxt_update_link(struct bnxt *bp, bool chng_link_state);
int bnxt_hwrm_set_pause(struct bnxt *);
int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
......
drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c
View file @ 4cd4b361
......@@ -1029,7 +1029,7 @@ static int bnxt_vf_set_link(struct bnxt *bp, struct bnxt_vf_info *vf)
rc = bnxt_hwrm_exec_fwd_resp(
bp, vf, sizeof(struct hwrm_port_phy_qcfg_input));
} else {
struct hwrm_port_phy_qcfg_output_compat phy_qcfg_resp = {0};
struct hwrm_port_phy_qcfg_output phy_qcfg_resp = {0};
struct hwrm_port_phy_qcfg_input *phy_qcfg_req;
phy_qcfg_req =
......
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