Commit 4d5ddfa4 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gfx10: per queue reset only on bare metal

It's not supported under SR-IOV at the moment.
Acked-by: default avatarVitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 178ad0e2
...@@ -9426,6 +9426,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) ...@@ -9426,6 +9426,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid)
u64 addr; u64 addr;
int r; int r;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL; return -EINVAL;
...@@ -9489,6 +9492,9 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, ...@@ -9489,6 +9492,9 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring,
unsigned long flags; unsigned long flags;
int i, r; int i, r;
if (amdgpu_sriov_vf(adev))
return -EINVAL;
if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
return -EINVAL; return -EINVAL;
......
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