Commit 4e347bdf authored by Terry Bowman's avatar Terry Bowman Committed by Borislav Petkov (AMD)

tools/x86/kcpuid: Fix avx512bw and avx512lvl fields in Fn00000007

Leaf Fn00000007 contains avx512bw at bit 26 and avx512vl at bit 28. This
is incorrect per the SDM. Correct avx512bw to be bit 30 and avx512lvl to
be bit 31.

Fixes: c6b2f240 ("tools/x86: Add a kcpuid tool to show raw CPU features")
Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarFeng Tang <feng.tang@intel.com>
Link: https://lore.kernel.org/r/20230206141832.4162264-2-terry.bowman@amd.com
parent fe15c26e
...@@ -184,8 +184,8 @@ ...@@ -184,8 +184,8 @@
7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr 7, 0, EBX, 30, avx512bw, AVX512 Byte & Word instr
7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL) 7, 0, EBX, 31, avx512vl, AVX512 Vector Length Extentions (VL)
7, 0, ECX, 0, prefetchwt1, X 7, 0, ECX, 0, prefetchwt1, X
7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
7, 0, ECX, 2, umip, User-mode Instruction Prevention 7, 0, ECX, 2, umip, User-mode Instruction Prevention
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment