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Commit 4e8e7648 authored by Roja Rani Yarubandi's avatar Roja Rani Yarubandi Committed by Bjorn Andersson
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arm64: dts: qcom: sc7280: Add QUPv3 wrapper_1 nodes 

Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
Signed-off-by: default avatarRoja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: default avatarRajesh Patil <rajpat@codeaurora.org>
Reviewed-by: default avatarMatthias Kaehlcke <mka@chromium.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1632399378-12229-8-git-send-email-rajpat@codeaurora.org
parent e3bc6fec
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arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file @ 4e8e7648
...@@ -250,6 +250,10 @@ &qupv3_id_0 { ...@@ -250,6 +250,10 @@ &qupv3_id_0 {
status = "okay"; status = "okay";
}; };
&qupv3_id_1 {
status = "okay";
};
&sdhc_1 { &sdhc_1 {
status = "okay"; status = "okay";
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ 4e8e7648
...@@ -1020,6 +1020,435 @@ uart7: serial@99c000 { ...@@ -1020,6 +1020,435 @@ uart7: serial@99c000 {
}; };
}; };
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x2000>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
status = "disabled";
i2c8: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_data_clk>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart8: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a80000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_data_clk>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart9: serial@a84000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_data_clk>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart10: serial@a88000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a88000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_data_clk>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart11: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a8c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c12: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_data_clk>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart12: serial@a90000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a90000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c13: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_data_clk>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi13: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart13: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a94000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c14: i2c@a98000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_data_clk>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi14: spi@a98000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart14: serial@a98000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a98000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c15: i2c@a9c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_data_clk>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "qup-core", "qup-config",
"qup-memory";
status = "disabled";
};
spi15: spi@a9c000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
uart15: serial@a9c000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a9c000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SC7280_CX>;
operating-points-v2 = <&qup_opp_table>;
interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
cnoc2: interconnect@1500000 { cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>; reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2"; compatible = "qcom,sc7280-cnoc2";
...@@ -2190,6 +2619,46 @@ qup_i2c7_data_clk: qup-i2c7-data-clk { ...@@ -2190,6 +2619,46 @@ qup_i2c7_data_clk: qup-i2c7-data-clk {
function = "qup07"; function = "qup07";
}; };
qup_i2c8_data_clk: qup-i2c8-data-clk {
pins = "gpio32", "gpio33";
function = "qup10";
};
qup_i2c9_data_clk: qup-i2c9-data-clk {
pins = "gpio36", "gpio37";
function = "qup11";
};
qup_i2c10_data_clk: qup-i2c10-data-clk {
pins = "gpio40", "gpio41";
function = "qup12";
};
qup_i2c11_data_clk: qup-i2c11-data-clk {
pins = "gpio44", "gpio45";
function = "qup13";
};
qup_i2c12_data_clk: qup-i2c12-data-clk {
pins = "gpio48", "gpio49";
function = "qup14";
};
qup_i2c13_data_clk: qup-i2c13-data-clk {
pins = "gpio52", "gpio53";
function = "qup15";
};
qup_i2c14_data_clk: qup-i2c14-data-clk {
pins = "gpio56", "gpio57";
function = "qup16";
};
qup_i2c15_data_clk: qup-i2c15-data-clk {
pins = "gpio60", "gpio61";
function = "qup17";
};
qup_spi0_data_clk: qup-spi0-data-clk { qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio0", "gpio1", "gpio2"; pins = "gpio0", "gpio1", "gpio2";
function = "qup00"; function = "qup00";
...@@ -2310,6 +2779,126 @@ qup_spi7_cs_gpio: qup-spi7-cs-gpio { ...@@ -2310,6 +2779,126 @@ qup_spi7_cs_gpio: qup-spi7-cs-gpio {
function = "gpio"; function = "gpio";
}; };
qup_spi8_data_clk: qup-spi8-data-clk {
pins = "gpio32", "gpio33", "gpio34";
function = "qup10";
};
qup_spi8_cs: qup-spi8-cs {
pins = "gpio35";
function = "qup10";
};
qup_spi8_cs_gpio: qup-spi8-cs-gpio {
pins = "gpio35";
function = "gpio";
};
qup_spi9_data_clk: qup-spi9-data-clk {
pins = "gpio36", "gpio37", "gpio38";
function = "qup11";
};
qup_spi9_cs: qup-spi9-cs {
pins = "gpio39";
function = "qup11";
};
qup_spi9_cs_gpio: qup-spi9-cs-gpio {
pins = "gpio39";
function = "gpio";
};
qup_spi10_data_clk: qup-spi10-data-clk {
pins = "gpio40", "gpio41", "gpio42";
function = "qup12";
};
qup_spi10_cs: qup-spi10-cs {
pins = "gpio43";
function = "qup12";
};
qup_spi10_cs_gpio: qup-spi10-cs-gpio {
pins = "gpio43";
function = "gpio";
};
qup_spi11_data_clk: qup-spi11-data-clk {
pins = "gpio44", "gpio45", "gpio46";
function = "qup13";
};
qup_spi11_cs: qup-spi11-cs {
pins = "gpio47";
function = "qup13";
};
qup_spi11_cs_gpio: qup-spi11-cs-gpio {
pins = "gpio47";
function = "gpio";
};
qup_spi12_data_clk: qup-spi12-data-clk {
pins = "gpio48", "gpio49", "gpio50";
function = "qup14";
};
qup_spi12_cs: qup-spi12-cs {
pins = "gpio51";
function = "qup14";
};
qup_spi12_cs_gpio: qup-spi12-cs-gpio {
pins = "gpio51";
function = "gpio";
};
qup_spi13_data_clk: qup-spi13-data-clk {
pins = "gpio52", "gpio53", "gpio54";
function = "qup15";
};
qup_spi13_cs: qup-spi13-cs {
pins = "gpio55";
function = "qup15";
};
qup_spi13_cs_gpio: qup-spi13-cs-gpio {
pins = "gpio55";
function = "gpio";
};
qup_spi14_data_clk: qup-spi14-data-clk {
pins = "gpio56", "gpio57", "gpio58";
function = "qup16";
};
qup_spi14_cs: qup-spi14-cs {
pins = "gpio59";
function = "qup16";
};
qup_spi14_cs_gpio: qup-spi14-cs-gpio {
pins = "gpio59";
function = "gpio";
};
qup_spi15_data_clk: qup-spi15-data-clk {
pins = "gpio60", "gpio61", "gpio62";
function = "qup17";
};
qup_spi15_cs: qup-spi15-cs {
pins = "gpio63";
function = "qup17";
};
qup_spi15_cs_gpio: qup-spi15-cs-gpio {
pins = "gpio63";
function = "gpio";
};
qup_uart0_cts: qup-uart0-cts { qup_uart0_cts: qup-uart0-cts {
pins = "gpio0"; pins = "gpio0";
function = "qup00"; function = "qup00";
...@@ -2546,6 +3135,166 @@ data { ...@@ -2546,6 +3135,166 @@ data {
bias-bus-hold; bias-bus-hold;
}; };
}; };
qup_uart8_cts: qup-uart8-cts {
pins = "gpio32";
function = "qup10";
};
qup_uart8_rts: qup-uart8-rts {
pins = "gpio33";
function = "qup10";
};
qup_uart8_tx: qup-uart8-tx {
pins = "gpio34";
function = "qup10";
};
qup_uart8_rx: qup-uart8-rx {
pins = "gpio35";
function = "qup10";
};
qup_uart9_cts: qup-uart9-cts {
pins = "gpio36";
function = "qup11";
};
qup_uart9_rts: qup-uart9-rts {
pins = "gpio37";
function = "qup11";
};
qup_uart9_tx: qup-uart9-tx {
pins = "gpio38";
function = "qup11";
};
qup_uart9_rx: qup-uart9-rx {
pins = "gpio39";
function = "qup11";
};
qup_uart10_cts: qup-uart10-cts {
pins = "gpio40";
function = "qup12";
};
qup_uart10_rts: qup-uart10-rts {
pins = "gpio41";
function = "qup12";
};
qup_uart10_tx: qup-uart10-tx {
pins = "gpio42";
function = "qup12";
};
qup_uart10_rx: qup-uart10-rx {
pins = "gpio43";
function = "qup12";
};
qup_uart11_cts: qup-uart11-cts {
pins = "gpio44";
function = "qup13";
};
qup_uart11_rts: qup-uart11-rts {
pins = "gpio45";
function = "qup13";
};
qup_uart11_tx: qup-uart11-tx {
pins = "gpio46";
function = "qup13";
};
qup_uart11_rx: qup-uart11-rx {
pins = "gpio47";
function = "qup13";
};
qup_uart12_cts: qup-uart12-cts {
pins = "gpio48";
function = "qup14";
};
qup_uart12_rts: qup-uart12-rts {
pins = "gpio49";
function = "qup14";
};
qup_uart12_tx: qup-uart12-tx {
pins = "gpio50";
function = "qup14";
};
qup_uart12_rx: qup-uart12-rx {
pins = "gpio51";
function = "qup14";
};
qup_uart13_cts: qup-uart13-cts {
pins = "gpio52";
function = "qup15";
};
qup_uart13_rts: qup-uart13-rts {
pins = "gpio53";
function = "qup15";
};
qup_uart13_tx: qup-uart13-tx {
pins = "gpio54";
function = "qup15";
};
qup_uart13_rx: qup-uart13-rx {
pins = "gpio55";
function = "qup15";
};
qup_uart14_cts: qup-uart14-cts {
pins = "gpio56";
function = "qup16";
};
qup_uart14_rts: qup-uart14-rts {
pins = "gpio57";
function = "qup16";
};
qup_uart14_tx: qup-uart14-tx {
pins = "gpio58";
function = "qup16";
};
qup_uart14_rx: qup-uart14-rx {
pins = "gpio59";
function = "qup16";
};
qup_uart15_cts: qup-uart15-cts {
pins = "gpio60";
function = "qup17";
};
qup_uart15_rts: qup-uart15-rts {
pins = "gpio61";
function = "qup17";
};
qup_uart15_tx: qup-uart15-tx {
pins = "gpio62";
function = "qup17";
};
qup_uart15_rx: qup-uart15-rx {
pins = "gpio63";
function = "qup17";
};
}; };
apps_smmu: iommu@15000000 { apps_smmu: iommu@15000000 {
......
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