Commit 4f8d4440 authored by Jon Hunter's avatar Jon Hunter Committed by Thierry Reding

clk: tegra: Fix clock sources for Tegra210 EMC

The EMC clock sources for Tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If Tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.

Also add the additional pll_p clock source for the EMC.
Signed-off-by: default avatarJon Hunter <jonathanh@nvidia.com>
Acked-by: default avatarRhyland Klein <rklein@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 29569941
...@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = { ...@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
}; };
static const char *mux_pllmcp_clkm[] = { static const char *mux_pllmcp_clkm[] = {
"pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3", "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
"pll_p",
}; };
#define mux_pllmcp_clkm_idx NULL #define mux_pllmcp_clkm_idx NULL
......
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