Commit 4feb9d21 authored by Sean Christopherson's avatar Sean Christopherson

KVM: selftests: Convert vmx_pmu_caps_test to use X86_PROPERTY_*

Add X86_PROPERTY_PMU_VERSION and use it in vmx_pmu_caps_test to replace
open coded versions of the same functionality.

No functional change intended.
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221006005125.680782-9-seanjc@google.com
parent 5dc19f1c
...@@ -200,6 +200,8 @@ struct kvm_x86_cpu_property { ...@@ -200,6 +200,8 @@ struct kvm_x86_cpu_property {
}) })
#define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31) #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
#define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
#define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31) #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31)
#define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31) #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31)
#define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31) #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31)
...@@ -848,10 +850,6 @@ static inline void vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, ...@@ -848,10 +850,6 @@ static inline void vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index,
TEST_ASSERT(r == 1, KVM_IOCTL_ERROR(KVM_SET_MSRS, r)); TEST_ASSERT(r == 1, KVM_IOCTL_ERROR(KVM_SET_MSRS, r));
} }
static inline uint32_t kvm_get_cpuid_max_basic(void)
{
return kvm_get_supported_cpuid_entry(0)->eax;
}
void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits); void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
bool vm_is_unrestricted_guest(struct kvm_vm *vm); bool vm_is_unrestricted_guest(struct kvm_vm *vm);
......
...@@ -20,16 +20,6 @@ ...@@ -20,16 +20,6 @@
#define PMU_CAP_FW_WRITES (1ULL << 13) #define PMU_CAP_FW_WRITES (1ULL << 13)
#define PMU_CAP_LBR_FMT 0x3f #define PMU_CAP_LBR_FMT 0x3f
union cpuid10_eax {
struct {
unsigned int version_id:8;
unsigned int num_counters:8;
unsigned int bit_width:8;
unsigned int mask_length:8;
} split;
unsigned int full;
};
union perf_capabilities { union perf_capabilities {
struct { struct {
u64 lbr_format:6; u64 lbr_format:6;
...@@ -53,11 +43,9 @@ static void guest_code(void) ...@@ -53,11 +43,9 @@ static void guest_code(void)
int main(int argc, char *argv[]) int main(int argc, char *argv[])
{ {
const struct kvm_cpuid_entry2 *entry_a_0;
struct kvm_vm *vm; struct kvm_vm *vm;
struct kvm_vcpu *vcpu; struct kvm_vcpu *vcpu;
int ret; int ret;
union cpuid10_eax eax;
union perf_capabilities host_cap; union perf_capabilities host_cap;
uint64_t val; uint64_t val;
...@@ -69,11 +57,8 @@ int main(int argc, char *argv[]) ...@@ -69,11 +57,8 @@ int main(int argc, char *argv[])
TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM)); TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_PDCM));
TEST_REQUIRE(kvm_get_cpuid_max_basic() >= 0xa); TEST_REQUIRE(kvm_cpu_has_p(X86_PROPERTY_PMU_VERSION));
entry_a_0 = kvm_get_supported_cpuid_entry(0xa); TEST_REQUIRE(kvm_cpu_property(X86_PROPERTY_PMU_VERSION) > 0);
eax.full = entry_a_0->eax;
__TEST_REQUIRE(eax.split.version_id, "PMU is not supported by the vCPU");
/* testcase 1, set capabilities when we have PDCM bit */ /* testcase 1, set capabilities when we have PDCM bit */
vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, PMU_CAP_FW_WRITES); vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, PMU_CAP_FW_WRITES);
......
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