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Commit 52367a76 authored by Vipul Pandya's avatar Vipul Pandya Committed by David S. Miller
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cxgb4/cxgb4vf: Code cleanup to enable T4 Configuration File support 

This patch adds new enums and macros to enable T4 configuration file support. It
also removes duplicate macro definitions.

It fixes the build failure in cxgb4vf driver introduced because of old macro
definition removal.

It also performs SGE initialization based on T4 configuration file is provided
or not. If it is provided then it uses the parameters provided in it otherwise
it uses hard coded values.
Signed-off-by: default avatarJay Hernandez <jay@chelsio.com>
Signed-off-by: default avatarVipul Pandya <vipul@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5afc8b84
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Inline Side-by-side
Showing with 365 additions and 71 deletions
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View file @ 52367a76
......@@ -315,6 +315,9 @@ enum { /* adapter flags */
USING_MSI = (1 << 1),
USING_MSIX = (1 << 2),
FW_OK = (1 << 4),
USING_SOFT_PARAMS = (1 << 6),
MASTER_PF = (1 << 7),
FW_OFLD_CONN = (1 << 9),
};
struct rx_sw_desc;
......@@ -467,6 +470,11 @@ struct sge {
u16 rdma_rxq[NCHAN];
u16 timer_val[SGE_NTIMERS];
u8 counter_val[SGE_NCOUNTERS];
u32 fl_pg_order; /* large page allocation size */
u32 stat_len; /* length of status page at ring end */
u32 pktshift; /* padding between CPL & packet data */
u32 fl_align; /* response queue message alignment */
u32 fl_starve_thres; /* Free List starvation threshold */
unsigned int starve_thres;
u8 idma_state[2];
unsigned int egr_start;
......@@ -619,7 +627,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
struct net_device *dev, unsigned int iqid);
irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
void t4_sge_init(struct adapter *adap);
int t4_sge_init(struct adapter *adap);
void t4_sge_start(struct adapter *adap);
void t4_sge_stop(struct adapter *adap);
extern int dbfifo_int_thresh;
......@@ -638,6 +646,14 @@ static inline unsigned int us_to_core_ticks(const struct adapter *adap,
return (us * adap->params.vpd.cclk) / 1000;
}
static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
unsigned int ticks)
{
/* add Core Clock / 2 to round ticks to nearest uS */
return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
adapter->params.vpd.cclk);
}
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
u32 val);
......
drivers/net/ethernet/chelsio/cxgb4/sge.c
View file @ 52367a76
This diff is collapsed.
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View file @ 52367a76
......@@ -86,10 +86,17 @@
#define CIDXINC_SHIFT 0
#define CIDXINC(x) ((x) << CIDXINC_SHIFT)
#define X_RXPKTCPLMODE_SPLIT 1
#define X_INGPADBOUNDARY_SHIFT 5
#define SGE_CONTROL 0x1008
#define DCASYSTYPE 0x00080000U
#define RXPKTCPLMODE 0x00040000U
#define EGRSTATUSPAGESIZE 0x00020000U
#define RXPKTCPLMODE_MASK 0x00040000U
#define RXPKTCPLMODE_SHIFT 18
#define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
#define EGRSTATUSPAGESIZE_MASK 0x00020000U
#define EGRSTATUSPAGESIZE_SHIFT 17
#define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
#define PKTSHIFT_MASK 0x00001c00U
#define PKTSHIFT_SHIFT 10
#define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
......@@ -173,6 +180,12 @@
#define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
#define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
#define SGE_CONM_CTRL 0x1094
#define EGRTHRESHOLD_MASK 0x00003f00U
#define EGRTHRESHOLDshift 8
#define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
#define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
#define SGE_TIMER_VALUE_0_AND_1 0x10b8
#define TIMERVALUE0_MASK 0xffff0000U
#define TIMERVALUE0_SHIFT 16
......@@ -184,7 +197,25 @@
#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
#define SGE_TIMER_VALUE_2_AND_3 0x10bc
#define TIMERVALUE2_MASK 0xffff0000U
#define TIMERVALUE2_SHIFT 16
#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
#define TIMERVALUE3_MASK 0x0000ffffU
#define TIMERVALUE3_SHIFT 0
#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
#define SGE_TIMER_VALUE_4_AND_5 0x10c0
#define TIMERVALUE4_MASK 0xffff0000U
#define TIMERVALUE4_SHIFT 16
#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
#define TIMERVALUE5_MASK 0x0000ffffU
#define TIMERVALUE5_SHIFT 0
#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
#define SGE_DEBUG_INDEX 0x10cc
#define SGE_DEBUG_DATA_HIGH 0x10d0
#define SGE_DEBUG_DATA_LOW 0x10d4
......
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View file @ 52367a76
......@@ -401,6 +401,14 @@ enum fw_caps_config_fcoe {
FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
};
enum fw_memtype_cf {
FW_MEMTYPE_CF_EDC0 = 0x0,
FW_MEMTYPE_CF_EDC1 = 0x1,
FW_MEMTYPE_CF_EXTMEM = 0x2,
FW_MEMTYPE_CF_FLASH = 0x4,
FW_MEMTYPE_CF_INTERNAL = 0x5,
};
struct fw_caps_config_cmd {
__be32 op_to_write;
__be32 retval_len16;
......@@ -416,10 +424,15 @@ struct fw_caps_config_cmd {
__be16 r4;
__be16 iscsicaps;
__be16 fcoecaps;
__be32 r5;
__be64 r6;
__be32 cfcsum;
__be32 finiver;
__be32 finicsum;
};
#define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27)
#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24)
#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
/*
* params command mnemonics
*/
......@@ -451,6 +464,7 @@ enum fw_params_param_dev {
FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
FW_PARAMS_PARAM_DEV_CF = 0x0D,
};
/*
......@@ -492,6 +506,8 @@ enum fw_params_param_pfvf {
FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E
};
/*
......@@ -507,8 +523,16 @@ enum fw_params_param_dmaq {
#define FW_PARAMS_MNEM(x) ((x) << 24)
#define FW_PARAMS_PARAM_X(x) ((x) << 16)
#define FW_PARAMS_PARAM_Y(x) ((x) << 8)
#define FW_PARAMS_PARAM_Z(x) ((x) << 0)
#define FW_PARAMS_PARAM_Y_SHIFT 8
#define FW_PARAMS_PARAM_Y_MASK 0xffU
#define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT)
#define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
FW_PARAMS_PARAM_Y_MASK)
#define FW_PARAMS_PARAM_Z_SHIFT 0
#define FW_PARAMS_PARAM_Z_MASK 0xffu
#define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT)
#define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
FW_PARAMS_PARAM_Z_MASK)
#define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
#define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
......@@ -1599,6 +1623,15 @@ struct fw_debug_cmd {
} u;
};
#define FW_PCIE_FW_ERR (1U << 31)
#define FW_PCIE_FW_INIT (1U << 30)
#define FW_PCIE_FW_MASTER_VLD (1U << 15)
#define FW_PCIE_FW_MASTER_MASK 0x7
#define FW_PCIE_FW_MASTER_SHIFT 12
#define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
#define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
FW_PCIE_FW_MASTER_MASK)
struct fw_hdr {
u8 ver;
u8 reserved1;
......
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
View file @ 52367a76
......@@ -2421,7 +2421,7 @@ int t4vf_sge_init(struct adapter *adapter)
fl0, fl1);
return -EINVAL;
}
if ((sge_params->sge_control & RXPKTCPLMODE) == 0) {
if ((sge_params->sge_control & RXPKTCPLMODE_MASK) == 0) {
dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
return -EINVAL;
}
......@@ -2431,7 +2431,8 @@ int t4vf_sge_init(struct adapter *adapter)
*/
if (fl1)
FL_PG_ORDER = ilog2(fl1) - PAGE_SHIFT;
STAT_LEN = ((sge_params->sge_control & EGRSTATUSPAGESIZE) ? 128 : 64);
STAT_LEN = ((sge_params->sge_control & EGRSTATUSPAGESIZE_MASK)
? 128 : 64);
PKTSHIFT = PKTSHIFT_GET(sge_params->sge_control);
FL_ALIGN = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
SGE_INGPADBOUNDARY_SHIFT);
......
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