Commit 545a112b authored by David S. Miller's avatar David S. Miller

Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next

Jeff Kirsher says:

====================
Intel Wired LAN Driver Updates 2014-06-20

This series contains updates to i40e and i40evf.

Anjali provides an update to the registers to handle the updates from the
hardware.  Also provides a fix so that we do not try to access the rings
through the qvectors at the time of freeing the qvectors.

Jesse provides a workaround for some older NVM versions where the NVM
was not filling in the GLQF_HKEY register, so made sure that the
critical register is initialized.

Michal provides a fix to reset the head and tail on admin queue
initialization where head and tail are not reset by the hardware.

Neerav adds a helper routine that would wait for the Rx/Tx queue to reach
the enable or disable state that is requested.  Also provides a fix
to the debugfs command "lldp get remote" which was dumping the local
LLDPDU instead of the peer's LLDPDU.  Fixed a bug when all the Tx hang
recovery mechanisms have failed and the driver tries to bring down the
interface in the interrupt context.

Shannon provides a patch to clear the Virtual Ethernet Bridge (VEB) stats
when the PF stats are cleared.  Also cleans the service tasks so that
they do not run while a reset is in progress.

Mitch fixes an issue in i40evf_get_rxfh() where only fifteen registers
were being read instead of all sixteen.

Carolyn provides a change to the RSS configuration to set table size and
write to the hardware to confirm the RSS table size being used.

Kamil makes a change to the admin queue debug prints so that they will not
cause segmentation faults in some of our tool applications.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 88729dd1 7974d5e5
...@@ -84,6 +84,7 @@ ...@@ -84,6 +84,7 @@
#define I40E_AQ_WORK_LIMIT 16 #define I40E_AQ_WORK_LIMIT 16
#define I40E_MAX_USER_PRIORITY 8 #define I40E_MAX_USER_PRIORITY 8
#define I40E_DEFAULT_MSG_ENABLE 4 #define I40E_DEFAULT_MSG_ENABLE 4
#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
#define I40E_NVM_VERSION_LO_SHIFT 0 #define I40E_NVM_VERSION_LO_SHIFT 0
#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT) #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
...@@ -134,6 +135,7 @@ enum i40e_state_t { ...@@ -134,6 +135,7 @@ enum i40e_state_t {
__I40E_FILTER_OVERFLOW_PROMISC, __I40E_FILTER_OVERFLOW_PROMISC,
__I40E_SUSPENDED, __I40E_SUSPENDED,
__I40E_BAD_EEPROM, __I40E_BAD_EEPROM,
__I40E_DOWN_REQUESTED,
}; };
enum i40e_interrupt_policy { enum i40e_interrupt_policy {
...@@ -348,6 +350,7 @@ struct i40e_pf { ...@@ -348,6 +350,7 @@ struct i40e_pf {
u32 rx_hwtstamp_cleared; u32 rx_hwtstamp_cleared;
bool ptp_tx; bool ptp_tx;
bool ptp_rx; bool ptp_rx;
u16 rss_table_size;
}; };
struct i40e_mac_filter { struct i40e_mac_filter {
......
...@@ -296,6 +296,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) ...@@ -296,6 +296,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
i40e_status ret_code = 0; i40e_status ret_code = 0;
u32 reg = 0; u32 reg = 0;
/* Clear Head and Tail */
wr32(hw, hw->aq.asq.head, 0);
wr32(hw, hw->aq.asq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_VF_ATQBAH1, wr32(hw, I40E_VF_ATQBAH1,
...@@ -334,6 +338,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) ...@@ -334,6 +338,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
i40e_status ret_code = 0; i40e_status ret_code = 0;
u32 reg = 0; u32 reg = 0;
/* Clear Head and Tail */
wr32(hw, hw->aq.arq.head, 0);
wr32(hw, hw->aq.arq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_VF_ARQBAH1, wr32(hw, I40E_VF_ARQBAH1,
...@@ -677,6 +685,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw) ...@@ -677,6 +685,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)
desc = I40E_ADMINQ_DESC(*asq, ntc); desc = I40E_ADMINQ_DESC(*asq, ntc);
details = I40E_ADMINQ_DETAILS(*asq, ntc); details = I40E_ADMINQ_DETAILS(*asq, ntc);
while (rd32(hw, hw->aq.asq.head) != ntc) { while (rd32(hw, hw->aq.asq.head) != ntc) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"%s: ntc %d head %d.\n", __func__, ntc,
rd32(hw, hw->aq.asq.head));
if (details->callback) { if (details->callback) {
I40E_ADMINQ_CALLBACK cb_func = I40E_ADMINQ_CALLBACK cb_func =
(I40E_ADMINQ_CALLBACK)details->callback; (I40E_ADMINQ_CALLBACK)details->callback;
...@@ -736,6 +748,15 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw, ...@@ -736,6 +748,15 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
struct i40e_aq_desc *desc_on_ring; struct i40e_aq_desc *desc_on_ring;
bool cmd_completed = false; bool cmd_completed = false;
u16 retval = 0; u16 retval = 0;
u32 val = 0;
val = rd32(hw, hw->aq.asq.head);
if (val >= hw->aq.num_asq_entries) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: head overrun at %d\n", val);
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_exit;
}
if (hw->aq.asq.count == 0) { if (hw->aq.asq.count == 0) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
...@@ -829,6 +850,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw, ...@@ -829,6 +850,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
} }
/* bump the tail */ /* bump the tail */
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
(hw->aq.asq.next_to_use)++; (hw->aq.asq.next_to_use)++;
if (hw->aq.asq.next_to_use == hw->aq.asq.count) if (hw->aq.asq.next_to_use == hw->aq.asq.count)
...@@ -866,6 +888,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw, ...@@ -866,6 +888,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
I40E_DEBUG_AQ_MESSAGE, I40E_DEBUG_AQ_MESSAGE,
"AQTX: Command completed with error 0x%X.\n", "AQTX: Command completed with error 0x%X.\n",
retval); retval);
/* strip off FW internal code */ /* strip off FW internal code */
retval &= 0xff; retval &= 0xff;
} }
...@@ -880,6 +903,12 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw, ...@@ -880,6 +903,12 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
if (i40e_is_nvm_update_op(desc)) if (i40e_is_nvm_update_op(desc))
hw->aq.nvm_busy = true; hw->aq.nvm_busy = true;
if (le16_to_cpu(desc->datalen) == buff_size) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: desc and buffer writeback:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
}
/* update the error if time out occurred */ /* update the error if time out occurred */
if ((!cmd_completed) && if ((!cmd_completed) &&
(!details->async && !details->postpone)) { (!details->async && !details->postpone)) {
...@@ -951,10 +980,6 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw, ...@@ -951,10 +980,6 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
/* now clean the next descriptor */ /* now clean the next descriptor */
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
desc_idx = ntc; desc_idx = ntc;
i40e_debug_aq(hw,
I40E_DEBUG_AQ_COMMAND,
(void *)desc,
hw->aq.arq.r.arq_bi[desc_idx].va);
flags = le16_to_cpu(desc->flags); flags = le16_to_cpu(desc->flags);
if (flags & I40E_AQ_FLAG_ERR) { if (flags & I40E_AQ_FLAG_ERR) {
...@@ -977,6 +1002,9 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw, ...@@ -977,6 +1002,9 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
if (i40e_is_nvm_update_op(&e->desc)) if (i40e_is_nvm_update_op(&e->desc))
hw->aq.nvm_busy = false; hw->aq.nvm_busy = false;
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
/* Restore the original datalen and buffer address in the desc, /* Restore the original datalen and buffer address in the desc,
* FW updates datalen to indicate the event message * FW updates datalen to indicate the event message
* size * size
......
...@@ -1839,7 +1839,6 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, ...@@ -1839,7 +1839,6 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
struct i40e_aqc_list_capabilities_element_resp *cap; struct i40e_aqc_list_capabilities_element_resp *cap;
u32 number, logical_id, phys_id; u32 number, logical_id, phys_id;
struct i40e_hw_capabilities *p; struct i40e_hw_capabilities *p;
u32 reg_val;
u32 i = 0; u32 i = 0;
u16 id; u16 id;
...@@ -1910,11 +1909,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, ...@@ -1910,11 +1909,7 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
break; break;
case I40E_DEV_FUNC_CAP_RSS: case I40E_DEV_FUNC_CAP_RSS:
p->rss = true; p->rss = true;
reg_val = rd32(hw, I40E_PFQF_CTL_0);
if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
p->rss_table_size = number; p->rss_table_size = number;
else
p->rss_table_size = 128;
p->rss_table_entry_width = logical_id; p->rss_table_entry_width = logical_id;
break; break;
case I40E_DEV_FUNC_CAP_RX_QUEUES: case I40E_DEV_FUNC_CAP_RX_QUEUES:
......
...@@ -1830,7 +1830,7 @@ static ssize_t i40e_dbg_command_write(struct file *filp, ...@@ -1830,7 +1830,7 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
ret = i40e_aq_get_lldp_mib(&pf->hw, ret = i40e_aq_get_lldp_mib(&pf->hw,
I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
I40E_AQ_LLDP_MIB_LOCAL, I40E_AQ_LLDP_MIB_REMOTE,
buff, I40E_LLDPDU_SIZE, buff, I40E_LLDPDU_SIZE,
&llen, &rlen, NULL); &llen, &rlen, NULL);
if (ret) { if (ret) {
......
This diff is collapsed.
...@@ -50,6 +50,9 @@ ...@@ -50,6 +50,9 @@
(d) == I40E_DEV_ID_QSFP_B || \ (d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C) (d) == I40E_DEV_ID_QSFP_C)
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
#define I40E_MAX_VSI_QP 16 #define I40E_MAX_VSI_QP 16
#define I40E_MAX_VF_VSI 3 #define I40E_MAX_VF_VSI 3
#define I40E_MAX_CHAINED_RX_BUFFERS 5 #define I40E_MAX_CHAINED_RX_BUFFERS 5
...@@ -1162,4 +1165,7 @@ enum i40e_reset_type { ...@@ -1162,4 +1165,7 @@ enum i40e_reset_type {
I40E_RESET_GLOBR = 2, I40E_RESET_GLOBR = 2,
I40E_RESET_EMPR = 3, I40E_RESET_EMPR = 3,
}; };
/* RSS Hash Table Size */
#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
#endif /* _I40E_TYPE_H_ */ #endif /* _I40E_TYPE_H_ */
...@@ -294,6 +294,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw) ...@@ -294,6 +294,10 @@ static i40e_status i40e_config_asq_regs(struct i40e_hw *hw)
i40e_status ret_code = 0; i40e_status ret_code = 0;
u32 reg = 0; u32 reg = 0;
/* Clear Head and Tail */
wr32(hw, hw->aq.asq.head, 0);
wr32(hw, hw->aq.asq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the transmit queue */ /* configure the transmit queue */
wr32(hw, I40E_VF_ATQBAH1, wr32(hw, I40E_VF_ATQBAH1,
...@@ -332,6 +336,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw) ...@@ -332,6 +336,10 @@ static i40e_status i40e_config_arq_regs(struct i40e_hw *hw)
i40e_status ret_code = 0; i40e_status ret_code = 0;
u32 reg = 0; u32 reg = 0;
/* Clear Head and Tail */
wr32(hw, hw->aq.arq.head, 0);
wr32(hw, hw->aq.arq.tail, 0);
if (hw->mac.type == I40E_MAC_VF) { if (hw->mac.type == I40E_MAC_VF) {
/* configure the receive queue */ /* configure the receive queue */
wr32(hw, I40E_VF_ARQBAH1, wr32(hw, I40E_VF_ARQBAH1,
...@@ -630,6 +638,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw) ...@@ -630,6 +638,10 @@ static u16 i40e_clean_asq(struct i40e_hw *hw)
desc = I40E_ADMINQ_DESC(*asq, ntc); desc = I40E_ADMINQ_DESC(*asq, ntc);
details = I40E_ADMINQ_DETAILS(*asq, ntc); details = I40E_ADMINQ_DETAILS(*asq, ntc);
while (rd32(hw, hw->aq.asq.head) != ntc) { while (rd32(hw, hw->aq.asq.head) != ntc) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"%s: ntc %d head %d.\n", __func__, ntc,
rd32(hw, hw->aq.asq.head));
if (details->callback) { if (details->callback) {
I40E_ADMINQ_CALLBACK cb_func = I40E_ADMINQ_CALLBACK cb_func =
(I40E_ADMINQ_CALLBACK)details->callback; (I40E_ADMINQ_CALLBACK)details->callback;
...@@ -690,6 +702,15 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw, ...@@ -690,6 +702,15 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
struct i40e_aq_desc *desc_on_ring; struct i40e_aq_desc *desc_on_ring;
bool cmd_completed = false; bool cmd_completed = false;
u16 retval = 0; u16 retval = 0;
u32 val = 0;
val = rd32(hw, hw->aq.asq.head);
if (val >= hw->aq.num_asq_entries) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: head overrun at %d\n", val);
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_exit;
}
if (hw->aq.asq.count == 0) { if (hw->aq.asq.count == 0) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
...@@ -783,6 +804,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw, ...@@ -783,6 +804,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
} }
/* bump the tail */ /* bump the tail */
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff); i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
(hw->aq.asq.next_to_use)++; (hw->aq.asq.next_to_use)++;
if (hw->aq.asq.next_to_use == hw->aq.asq.count) if (hw->aq.asq.next_to_use == hw->aq.asq.count)
...@@ -820,6 +842,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw, ...@@ -820,6 +842,7 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
I40E_DEBUG_AQ_MESSAGE, I40E_DEBUG_AQ_MESSAGE,
"AQTX: Command completed with error 0x%X.\n", "AQTX: Command completed with error 0x%X.\n",
retval); retval);
/* strip off FW internal code */ /* strip off FW internal code */
retval &= 0xff; retval &= 0xff;
} }
...@@ -834,6 +857,12 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw, ...@@ -834,6 +857,12 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
if (i40e_is_nvm_update_op(desc)) if (i40e_is_nvm_update_op(desc))
hw->aq.nvm_busy = true; hw->aq.nvm_busy = true;
if (le16_to_cpu(desc->datalen) == buff_size) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: desc and buffer writeback:\n");
i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
}
/* update the error if time out occurred */ /* update the error if time out occurred */
if ((!cmd_completed) && if ((!cmd_completed) &&
(!details->async && !details->postpone)) { (!details->async && !details->postpone)) {
...@@ -905,10 +934,6 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, ...@@ -905,10 +934,6 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
/* now clean the next descriptor */ /* now clean the next descriptor */
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
desc_idx = ntc; desc_idx = ntc;
i40evf_debug_aq(hw,
I40E_DEBUG_AQ_COMMAND,
(void *)desc,
hw->aq.arq.r.arq_bi[desc_idx].va);
flags = le16_to_cpu(desc->flags); flags = le16_to_cpu(desc->flags);
if (flags & I40E_AQ_FLAG_ERR) { if (flags & I40E_AQ_FLAG_ERR) {
...@@ -931,6 +956,9 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, ...@@ -931,6 +956,9 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
if (i40e_is_nvm_update_op(&e->desc)) if (i40e_is_nvm_update_op(&e->desc))
hw->aq.nvm_busy = false; hw->aq.nvm_busy = false;
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
/* Restore the original datalen and buffer address in the desc, /* Restore the original datalen and buffer address in the desc,
* FW updates datalen to indicate the event message * FW updates datalen to indicate the event message
* size * size
......
...@@ -50,6 +50,9 @@ ...@@ -50,6 +50,9 @@
(d) == I40E_DEV_ID_QSFP_B || \ (d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C) (d) == I40E_DEV_ID_QSFP_C)
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
#define I40E_MAX_VSI_QP 16 #define I40E_MAX_VSI_QP 16
#define I40E_MAX_VF_VSI 3 #define I40E_MAX_VF_VSI 3
#define I40E_MAX_CHAINED_RX_BUFFERS 5 #define I40E_MAX_CHAINED_RX_BUFFERS 5
...@@ -1162,4 +1165,7 @@ enum i40e_reset_type { ...@@ -1162,4 +1165,7 @@ enum i40e_reset_type {
I40E_RESET_GLOBR = 2, I40E_RESET_GLOBR = 2,
I40E_RESET_EMPR = 3, I40E_RESET_EMPR = 3,
}; };
/* RSS Hash Table Size */
#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
#endif /* _I40E_TYPE_H_ */ #endif /* _I40E_TYPE_H_ */
...@@ -632,7 +632,7 @@ static int i40evf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key) ...@@ -632,7 +632,7 @@ static int i40evf_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key)
u32 hlut_val; u32 hlut_val;
int i, j; int i, j;
for (i = 0, j = 0; i < I40E_VFQF_HLUT_MAX_INDEX; i++) { for (i = 0, j = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {
hlut_val = rd32(hw, I40E_VFQF_HLUT(i)); hlut_val = rd32(hw, I40E_VFQF_HLUT(i));
indir[j++] = hlut_val & 0xff; indir[j++] = hlut_val & 0xff;
indir[j++] = (hlut_val >> 8) & 0xff; indir[j++] = (hlut_val >> 8) & 0xff;
...@@ -659,7 +659,7 @@ static int i40evf_set_rxfh(struct net_device *netdev, const u32 *indir, ...@@ -659,7 +659,7 @@ static int i40evf_set_rxfh(struct net_device *netdev, const u32 *indir,
u32 hlut_val; u32 hlut_val;
int i, j; int i, j;
for (i = 0, j = 0; i < I40E_VFQF_HLUT_MAX_INDEX + 1; i++) { for (i = 0, j = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) {
hlut_val = indir[j++]; hlut_val = indir[j++];
hlut_val |= indir[j++] << 8; hlut_val |= indir[j++] << 8;
hlut_val |= indir[j++] << 16; hlut_val |= indir[j++] << 16;
......
...@@ -36,7 +36,7 @@ char i40evf_driver_name[] = "i40evf"; ...@@ -36,7 +36,7 @@ char i40evf_driver_name[] = "i40evf";
static const char i40evf_driver_string[] = static const char i40evf_driver_string[] =
"Intel(R) XL710 X710 Virtual Function Network Driver"; "Intel(R) XL710 X710 Virtual Function Network Driver";
#define DRV_VERSION "0.9.34" #define DRV_VERSION "0.9.35"
const char i40evf_driver_version[] = DRV_VERSION; const char i40evf_driver_version[] = DRV_VERSION;
static const char i40evf_copyright[] = static const char i40evf_copyright[] =
"Copyright (c) 2013 - 2014 Intel Corporation."; "Copyright (c) 2013 - 2014 Intel Corporation.";
......
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