Skip to content

L
linux
Commit 545aabcb authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'drm-fixes-2019-02-15-1' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Usual pull request, little larger than I'd like but nothing too
  strange in it. Willy found an bug in the lease ioctl calculations, but
  it's a drm master only ioctl which makes it harder to mess with.

 i915:
   - combo phy programming fix
   - opregion version check fix for VBT RVDA lookup
   - gem mmap ioctl race fix
   - fbdev hpd during suspend fix
   - array size bounds check fix in pmu

  amdgpu:
   - Vega20 psp fix
   - Add vrr range to debugfs for freesync debugging

  sched:
   - Scheduler race fix

  vkms:
   - license header fixups

  imx:
   - Fix CSI register offsets for i.MX51 and i.MX53.
   - Fix delayed page flip completion events on i.MX6QP due to
     unexpected behaviour of the PRE when issuing NOP buffer updates to
     the same buffer address.
   - Stop throwing errors for plane updates on disabled CRTCs when a
     userspace process is killed while a plane update is pending.
   - Add missing of_node_put cleanup in imx_ldb_bind"

* tag 'drm-fixes-2019-02-15-1' of git://anongit.freedesktop.org/drm/drm:
  drm: Use array_size() when creating lease
  drm/amdgpu/psp11: TA firmware is optional (v3)
  drm/i915/opregion: rvda is relative from opregion base in opregion 2.1+
  drm/i915/opregion: fix version check
  drm/i915: Prevent a race during I915_GEM_MMAP ioctl with WC set
  drm/i915: Block fbdev HPD processing during suspend
  drm/i915/pmu: Fix enable count array size and bounds checking
  drm/i915/cnl: Fix CNL macros for Voltage Swing programming
  drm/i915/icl: combo port vswing programming changes per BSPEC
  drm/vkms: Fix license inconsistent
  drm/amd/display: Expose connector VRR range via debugfs
  drm/sched: Always trace the dependencies we wait on, to fix a race.
  gpu: ipu-v3: pre: don't trigger update if buffer address doesn't change
  gpu: ipu-v3: Fix CSI offsets for imx53
  drm/imx: imx-ldb: add missing of_node_puts
  gpu: ipu-v3: Fix i.MX51 CSI control registers offset
  drm/imx: ignore plane updates on disabled crtcs
parents 2aba3220 69ef943d
Show whitespace changes
Inline Side-by-side
Showing with 294 additions and 248 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View file @ 545aabcb
...@@ -90,8 +90,10 @@ static int psp_sw_fini(void *handle) ...@@ -90,8 +90,10 @@ static int psp_sw_fini(void *handle)
adev->psp.sos_fw = NULL; adev->psp.sos_fw = NULL;
release_firmware(adev->psp.asd_fw); release_firmware(adev->psp.asd_fw);
adev->psp.asd_fw = NULL; adev->psp.asd_fw = NULL;
if (adev->psp.ta_fw) {
release_firmware(adev->psp.ta_fw); release_firmware(adev->psp.ta_fw);
adev->psp.ta_fw = NULL; adev->psp.ta_fw = NULL;
}
return 0; return 0;
} }
...@@ -435,6 +437,9 @@ static int psp_xgmi_initialize(struct psp_context *psp) ...@@ -435,6 +437,9 @@ static int psp_xgmi_initialize(struct psp_context *psp)
struct ta_xgmi_shared_memory *xgmi_cmd; struct ta_xgmi_shared_memory *xgmi_cmd;
int ret; int ret;
if (!psp->adev->psp.ta_fw)
return -ENOENT;
if (!psp->xgmi_context.initialized) { if (!psp->xgmi_context.initialized) {
ret = psp_xgmi_init_shared_buf(psp); ret = psp_xgmi_init_shared_buf(psp);
if (ret) if (ret)
......
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
View file @ 545aabcb
...@@ -152,9 +152,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) ...@@ -152,9 +152,12 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev); err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
if (err) if (err) {
goto out2; release_firmware(adev->psp.ta_fw);
adev->psp.ta_fw = NULL;
dev_info(adev->dev,
"psp v11.0: Failed to load firmware \"%s\"\n", fw_name);
} else {
err = amdgpu_ucode_validate(adev->psp.ta_fw); err = amdgpu_ucode_validate(adev->psp.ta_fw);
if (err) if (err)
goto out2; goto out2;
...@@ -164,6 +167,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp) ...@@ -164,6 +167,7 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes); adev->psp.ta_xgmi_ucode_size = le32_to_cpu(ta_hdr->ta_xgmi_size_bytes);
adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr + adev->psp.ta_xgmi_start_addr = (uint8_t *)ta_hdr +
le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes); le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
}
return 0; return 0;
......
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View file @ 545aabcb
...@@ -671,6 +671,25 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us ...@@ -671,6 +671,25 @@ static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __us
return bytes_from_user; return bytes_from_user;
} }
/*
* Returns the min and max vrr vfreq through the connector's debugfs file.
* Example usage: cat /sys/kernel/debug/dri/0/DP-1/vrr_range
*/
static int vrr_range_show(struct seq_file *m, void *data)
{
struct drm_connector *connector = m->private;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
if (connector->status != connector_status_connected)
return -ENODEV;
seq_printf(m, "Min: %u\n", (unsigned int)aconnector->min_vfreq);
seq_printf(m, "Max: %u\n", (unsigned int)aconnector->max_vfreq);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(vrr_range);
static const struct file_operations dp_link_settings_debugfs_fops = { static const struct file_operations dp_link_settings_debugfs_fops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.read = dp_link_settings_read, .read = dp_link_settings_read,
...@@ -697,7 +716,8 @@ static const struct { ...@@ -697,7 +716,8 @@ static const struct {
} dp_debugfs_entries[] = { } dp_debugfs_entries[] = {
{"link_settings", &dp_link_settings_debugfs_fops}, {"link_settings", &dp_link_settings_debugfs_fops},
{"phy_settings", &dp_phy_settings_debugfs_fop}, {"phy_settings", &dp_phy_settings_debugfs_fop},
{"test_pattern", &dp_phy_test_pattern_fops} {"test_pattern", &dp_phy_test_pattern_fops},
{"vrr_range", &vrr_range_fops}
}; };
int connector_debugfs_init(struct amdgpu_dm_connector *connector) int connector_debugfs_init(struct amdgpu_dm_connector *connector)
......
drivers/gpu/drm/drm_lease.c
View file @ 545aabcb
...@@ -528,7 +528,8 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev, ...@@ -528,7 +528,8 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
object_count = cl->object_count; object_count = cl->object_count;
object_ids = memdup_user(u64_to_user_ptr(cl->object_ids), object_count * sizeof(__u32)); object_ids = memdup_user(u64_to_user_ptr(cl->object_ids),
array_size(object_count, sizeof(__u32)));
if (IS_ERR(object_ids)) if (IS_ERR(object_ids))
return PTR_ERR(object_ids); return PTR_ERR(object_ids);
......
drivers/gpu/drm/i915/i915_gem.c
View file @ 545aabcb
...@@ -1824,6 +1824,16 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, ...@@ -1824,6 +1824,16 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
return 0; return 0;
} }
static inline bool
__vma_matches(struct vm_area_struct *vma, struct file *filp,
unsigned long addr, unsigned long size)
{
if (vma->vm_file != filp)
return false;
return vma->vm_start == addr && (vma->vm_end - vma->vm_start) == size;
}
/** /**
* i915_gem_mmap_ioctl - Maps the contents of an object, returning the address * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
* it is mapped to. * it is mapped to.
...@@ -1882,7 +1892,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, ...@@ -1882,7 +1892,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
return -EINTR; return -EINTR;
} }
vma = find_vma(mm, addr); vma = find_vma(mm, addr);
if (vma) if (vma && __vma_matches(vma, obj->base.filp, addr, args->size))
vma->vm_page_prot = vma->vm_page_prot =
pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
else else
......
drivers/gpu/drm/i915/i915_pmu.c
View file @ 545aabcb
...@@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event) ...@@ -594,7 +594,8 @@ static void i915_pmu_enable(struct perf_event *event)
* Update the bitmask of enabled events and increment * Update the bitmask of enabled events and increment
* the event reference counter. * the event reference counter.
*/ */
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); BUILD_BUG_ON(ARRAY_SIZE(i915->pmu.enable_count) != I915_PMU_MASK_BITS);
GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0); GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
i915->pmu.enable |= BIT_ULL(bit); i915->pmu.enable |= BIT_ULL(bit);
i915->pmu.enable_count[bit]++; i915->pmu.enable_count[bit]++;
...@@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event) ...@@ -615,11 +616,16 @@ static void i915_pmu_enable(struct perf_event *event)
engine = intel_engine_lookup_user(i915, engine = intel_engine_lookup_user(i915,
engine_event_class(event), engine_event_class(event),
engine_event_instance(event)); engine_event_instance(event));
GEM_BUG_ON(!engine);
engine->pmu.enable |= BIT(sample);
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
I915_ENGINE_SAMPLE_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
I915_ENGINE_SAMPLE_COUNT);
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
engine->pmu.enable |= BIT(sample);
engine->pmu.enable_count[sample]++; engine->pmu.enable_count[sample]++;
} }
...@@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event) ...@@ -649,9 +655,11 @@ static void i915_pmu_disable(struct perf_event *event)
engine = intel_engine_lookup_user(i915, engine = intel_engine_lookup_user(i915,
engine_event_class(event), engine_event_class(event),
engine_event_instance(event)); engine_event_instance(event));
GEM_BUG_ON(!engine);
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS); GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
/* /*
* Decrement the reference count and clear the enabled * Decrement the reference count and clear the enabled
* bitmask when the last listener on an event goes away. * bitmask when the last listener on an event goes away.
...@@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event) ...@@ -660,7 +668,7 @@ static void i915_pmu_disable(struct perf_event *event)
engine->pmu.enable &= ~BIT(sample); engine->pmu.enable &= ~BIT(sample);
} }
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS); GEM_BUG_ON(bit >= ARRAY_SIZE(i915->pmu.enable_count));
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0); GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
/* /*
* Decrement the reference count and clear the enabled * Decrement the reference count and clear the enabled
......
drivers/gpu/drm/i915/i915_pmu.h
View file @ 545aabcb
...@@ -31,6 +31,8 @@ enum { ...@@ -31,6 +31,8 @@ enum {
((1 << I915_PMU_SAMPLE_BITS) + \ ((1 << I915_PMU_SAMPLE_BITS) + \
(I915_PMU_LAST + 1 - __I915_PMU_OTHER(0))) (I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
struct i915_pmu_sample { struct i915_pmu_sample {
u64 cur; u64 cur;
}; };
......
drivers/gpu/drm/i915/i915_reg.h
View file @ 545aabcb
...@@ -1790,7 +1790,7 @@ enum i915_power_well_id { ...@@ -1790,7 +1790,7 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 #define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 #define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 #define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \ #define _CNL_PORT_TX_DW_GRP(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_GRP_OFFSET, \ _CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \ _CNL_PORT_TX_B_GRP_OFFSET, \
_CNL_PORT_TX_B_GRP_OFFSET, \ _CNL_PORT_TX_B_GRP_OFFSET, \
...@@ -1798,7 +1798,7 @@ enum i915_power_well_id { ...@@ -1798,7 +1798,7 @@ enum i915_power_well_id {
_CNL_PORT_TX_AE_GRP_OFFSET, \ _CNL_PORT_TX_AE_GRP_OFFSET, \
_CNL_PORT_TX_F_GRP_OFFSET) + \ _CNL_PORT_TX_F_GRP_OFFSET) + \
4 * (dw)) 4 * (dw))
#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \ #define _CNL_PORT_TX_DW_LN0(dw, port) (_PICK((port), \
_CNL_PORT_TX_AE_LN0_OFFSET, \ _CNL_PORT_TX_AE_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \ _CNL_PORT_TX_B_LN0_OFFSET, \
_CNL_PORT_TX_B_LN0_OFFSET, \ _CNL_PORT_TX_B_LN0_OFFSET, \
...@@ -1834,9 +1834,9 @@ enum i915_power_well_id { ...@@ -1834,9 +1834,9 @@ enum i915_power_well_id {
#define _CNL_PORT_TX_DW4_LN0_AE 0x162450 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450
#define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0
#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4)) #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port)))
#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4)) #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)))
#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ #define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \
((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \
_CNL_PORT_TX_DW4_LN0_AE))) _CNL_PORT_TX_DW4_LN0_AE)))
#define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port))
...@@ -1864,8 +1864,12 @@ enum i915_power_well_id { ...@@ -1864,8 +1864,12 @@ enum i915_power_well_id {
#define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT(x) ((x) << 3)
#define RTERM_SELECT_MASK (0x7 << 3) #define RTERM_SELECT_MASK (0x7 << 3)
#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) #define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(7, (port)))
#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) #define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(7, (port)))
#define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port))
#define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port))
#define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port))
#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port))
#define N_SCALAR(x) ((x) << 24) #define N_SCALAR(x) ((x) << 24)
#define N_SCALAR_MASK (0x7F << 24) #define N_SCALAR_MASK (0x7F << 24)
......
drivers/gpu/drm/i915/intel_ddi.c
View file @ 545aabcb
...@@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = { ...@@ -494,103 +494,58 @@ static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
{ 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */ { 0x2, 0x7F, 0x3F, 0x00, 0x00 }, /* 400 400 0.0 */
}; };
struct icl_combo_phy_ddi_buf_trans { /* icl_combo_phy_ddi_translations */
u32 dw2_swing_select; static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
u32 dw2_swing_scalar; /* NT mV Trans mV db */
u32 dw4_scaling; { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
}; { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
{ 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
/* Voltage Swing Programming for VccIO 0.85V for DP */ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_85V[] = { { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
/* Voltage mV db */ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
{ 0xB, 0x70, 0x0018 }, /* 600 0.0 */
{ 0xB, 0x70, 0x3015 }, /* 600 3.5 */
{ 0xB, 0x70, 0x6012 }, /* 600 6.0 */
{ 0x5, 0x00, 0x0018 }, /* 800 0.0 */
{ 0x5, 0x00, 0x3015 }, /* 800 3.5 */
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
};
/* FIXME - After table is updated in Bspec */
/* Voltage Swing Programming for VccIO 0.85V for eDP */
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_85V[] = {
/* Voltage mV db */
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
};
/* Voltage Swing Programming for VccIO 0.95V for DP */
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_0_95V[] = {
/* Voltage mV db */
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */
{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */
{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */
{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */
{ 0x5, 0x76, 0x0018 }, /* 800 0.0 */
{ 0x5, 0x76, 0x3015 }, /* 800 3.5 */
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
}; };
/* FIXME - After table is updated in Bspec */ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
/* Voltage Swing Programming for VccIO 0.95V for eDP */ /* NT mV Trans mV db */
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_0_95V[] = { { 0x0, 0x7F, 0x3F, 0x00, 0x00 }, /* 200 200 0.0 */
/* Voltage mV db */ { 0x8, 0x7F, 0x38, 0x00, 0x07 }, /* 200 250 1.9 */
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */ { 0x1, 0x7F, 0x33, 0x00, 0x0C }, /* 200 300 3.5 */
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */ { 0x9, 0x7F, 0x31, 0x00, 0x0E }, /* 200 350 4.9 */
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */ { 0x8, 0x7F, 0x3F, 0x00, 0x00 }, /* 250 250 0.0 */
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */ { 0x1, 0x7F, 0x38, 0x00, 0x07 }, /* 250 300 1.6 */
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */ { 0x9, 0x7F, 0x35, 0x00, 0x0A }, /* 250 350 2.9 */
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */ { 0x1, 0x7F, 0x3F, 0x00, 0x00 }, /* 300 300 0.0 */
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */ { 0x9, 0x7F, 0x38, 0x00, 0x07 }, /* 300 350 1.3 */
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */ { 0x9, 0x7F, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
}; };
/* Voltage Swing Programming for VccIO 1.05V for DP */ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hdmi_1_05V[] = { /* NT mV Trans mV db */
/* Voltage mV db */ { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
{ 0x2, 0x98, 0x0018 }, /* 400 0.0 */ { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */
{ 0x2, 0x98, 0x3015 }, /* 400 3.5 */ { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
{ 0x2, 0x98, 0x6012 }, /* 400 6.0 */ { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */
{ 0x2, 0x98, 0x900F }, /* 400 9.5 */ { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
{ 0x4, 0x98, 0x0018 }, /* 600 0.0 */ { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */
{ 0x4, 0x98, 0x3015 }, /* 600 3.5 */ { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */
{ 0x4, 0x98, 0x6012 }, /* 600 6.0 */ { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */
{ 0x5, 0x71, 0x0018 }, /* 800 0.0 */ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
{ 0x5, 0x71, 0x3015 }, /* 800 3.5 */ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
{ 0x6, 0x98, 0x0018 }, /* 1200 0.0 */
}; };
/* FIXME - After table is updated in Bspec */ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
/* Voltage Swing Programming for VccIO 1.05V for eDP */ /* NT mV Trans mV db */
static const struct icl_combo_phy_ddi_buf_trans icl_combo_phy_ddi_translations_edp_1_05V[] = { { 0xA, 0x60, 0x3F, 0x00, 0x00 }, /* 450 450 0.0 */
/* Voltage mV db */ { 0xB, 0x73, 0x36, 0x00, 0x09 }, /* 450 650 3.2 */
{ 0x0, 0x00, 0x00 }, /* 200 0.0 */ { 0x6, 0x7F, 0x31, 0x00, 0x0E }, /* 450 850 5.5 */
{ 0x0, 0x00, 0x00 }, /* 200 1.5 */ { 0xB, 0x73, 0x3F, 0x00, 0x00 }, /* 650 650 0.0 ALS */
{ 0x0, 0x00, 0x00 }, /* 200 4.0 */ { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 650 850 2.3 */
{ 0x0, 0x00, 0x00 }, /* 200 6.0 */ { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 850 850 0.0 */
{ 0x0, 0x00, 0x00 }, /* 250 0.0 */ { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */
{ 0x0, 0x00, 0x00 }, /* 250 1.5 */
{ 0x0, 0x00, 0x00 }, /* 250 4.0 */
{ 0x0, 0x00, 0x00 }, /* 300 0.0 */
{ 0x0, 0x00, 0x00 }, /* 300 1.5 */
{ 0x0, 0x00, 0x00 }, /* 350 0.0 */
}; };
struct icl_mg_phy_ddi_buf_trans { struct icl_mg_phy_ddi_buf_trans {
...@@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) ...@@ -871,43 +826,23 @@ cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
} }
} }
static const struct icl_combo_phy_ddi_buf_trans * static const struct cnl_ddi_buf_trans *
icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port, icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, enum port port,
int type, int *n_entries) int type, int rate, int *n_entries)
{ {
u32 voltage = I915_READ(ICL_PORT_COMP_DW3(port)) & VOLTAGE_INFO_MASK; if (type == INTEL_OUTPUT_HDMI) {
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) { return icl_combo_phy_ddi_translations_hdmi;
switch (voltage) { } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
case VOLTAGE_INFO_0_85V: *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_85V); return icl_combo_phy_ddi_translations_edp_hbr3;
return icl_combo_phy_ddi_translations_edp_0_85V; } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
case VOLTAGE_INFO_0_95V: *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_0_95V); return icl_combo_phy_ddi_translations_edp_hbr2;
return icl_combo_phy_ddi_translations_edp_0_95V;
case VOLTAGE_INFO_1_05V:
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_1_05V);
return icl_combo_phy_ddi_translations_edp_1_05V;
default:
MISSING_CASE(voltage);
return NULL;
}
} else {
switch (voltage) {
case VOLTAGE_INFO_0_85V:
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_85V);
return icl_combo_phy_ddi_translations_dp_hdmi_0_85V;
case VOLTAGE_INFO_0_95V:
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_0_95V);
return icl_combo_phy_ddi_translations_dp_hdmi_0_95V;
case VOLTAGE_INFO_1_05V:
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hdmi_1_05V);
return icl_combo_phy_ddi_translations_dp_hdmi_1_05V;
default:
MISSING_CASE(voltage);
return NULL;
}
} }
*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
return icl_combo_phy_ddi_translations_dp_hbr2;
} }
static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port)
...@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por ...@@ -918,8 +853,8 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por
if (IS_ICELAKE(dev_priv)) { if (IS_ICELAKE(dev_priv)) {
if (intel_port_is_combophy(dev_priv, port)) if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, icl_get_combo_buf_trans(dev_priv, port, INTEL_OUTPUT_HDMI,
INTEL_OUTPUT_HDMI, &n_entries); 0, &n_entries);
else else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
default_entry = n_entries - 1; default_entry = n_entries - 1;
...@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, ...@@ -2275,13 +2210,14 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
enum port port = encoder->port; enum port port = encoder->port;
int n_entries; int n_entries;
if (IS_ICELAKE(dev_priv)) { if (IS_ICELAKE(dev_priv)) {
if (intel_port_is_combophy(dev_priv, port)) if (intel_port_is_combophy(dev_priv, port))
icl_get_combo_buf_trans(dev_priv, port, encoder->type, icl_get_combo_buf_trans(dev_priv, port, encoder->type,
&n_entries); intel_dp->link_rate, &n_entries);
else else
n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations); n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations);
} else if (IS_CANNONLAKE(dev_priv)) { } else if (IS_CANNONLAKE(dev_priv)) {
...@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, ...@@ -2462,14 +2398,15 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
} }
static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
u32 level, enum port port, int type) u32 level, enum port port, int type,
int rate)
{ {
const struct icl_combo_phy_ddi_buf_trans *ddi_translations = NULL; const struct cnl_ddi_buf_trans *ddi_translations = NULL;
u32 n_entries, val; u32 n_entries, val;
int ln; int ln;
ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type, ddi_translations = icl_get_combo_buf_trans(dev_priv, port, type,
&n_entries); rate, &n_entries);
if (!ddi_translations) if (!ddi_translations)
return; return;
...@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, ...@@ -2478,34 +2415,23 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
level = n_entries - 1; level = n_entries - 1;
} }
/* Set PORT_TX_DW5 Rterm Sel to 110b. */ /* Set PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
val &= ~RTERM_SELECT_MASK; val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
TAP2_DISABLE | TAP3_DISABLE);
val |= SCALING_MODE_SEL(0x2);
val |= RTERM_SELECT(0x6); val |= RTERM_SELECT(0x6);
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW5 */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
/* Set DisableTap2 and DisableTap3 if MIPI DSI
* Clear DisableTap2 and DisableTap3 for all other Ports
*/
if (type == INTEL_OUTPUT_DSI) {
val |= TAP2_DISABLE;
val |= TAP3_DISABLE; val |= TAP3_DISABLE;
} else {
val &= ~TAP2_DISABLE;
val &= ~TAP3_DISABLE;
}
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* Program PORT_TX_DW2 */ /* Program PORT_TX_DW2 */
val = I915_READ(ICL_PORT_TX_DW2_LN0(port)); val = I915_READ(ICL_PORT_TX_DW2_LN0(port));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK); RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_select); val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_select); val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
/* Program Rcomp scalar for every table entry */ /* Program Rcomp scalar for every table entry */
val |= RCOMP_SCALAR(ddi_translations[level].dw2_swing_scalar); val |= RCOMP_SCALAR(0x98);
I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val); I915_WRITE(ICL_PORT_TX_DW2_GRP(port), val);
/* Program PORT_TX_DW4 */ /* Program PORT_TX_DW4 */
...@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, ...@@ -2514,9 +2440,17 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv,
val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK); CURSOR_COEFF_MASK);
val |= ddi_translations[level].dw4_scaling; val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val);
} }
/* Program PORT_TX_DW7 */
val = I915_READ(ICL_PORT_TX_DW7_LN0(port));
val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
I915_WRITE(ICL_PORT_TX_DW7_GRP(port), val);
} }
static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
...@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, ...@@ -2581,7 +2515,7 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val); I915_WRITE(ICL_PORT_TX_DW5_GRP(port), val);
/* 5. Program swing and de-emphasis */ /* 5. Program swing and de-emphasis */
icl_ddi_combo_vswing_program(dev_priv, level, port, type); icl_ddi_combo_vswing_program(dev_priv, level, port, type, rate);
/* 6. Set training enable to trigger update */ /* 6. Set training enable to trigger update */
val = I915_READ(ICL_PORT_TX_DW5_LN0(port)); val = I915_READ(ICL_PORT_TX_DW5_LN0(port));
......
drivers/gpu/drm/i915/intel_dp.c
View file @ 545aabcb
...@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp) ...@@ -304,9 +304,11 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp)
static int icl_max_source_rate(struct intel_dp *intel_dp) static int icl_max_source_rate(struct intel_dp *intel_dp)
{ {
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
enum port port = dig_port->base.port; enum port port = dig_port->base.port;
if (port == PORT_B) if (intel_port_is_combophy(dev_priv, port) &&
!intel_dp_is_edp(intel_dp))
return 540000; return 540000;
return 810000; return 810000;
......
drivers/gpu/drm/i915/intel_drv.h
View file @ 545aabcb
...@@ -209,6 +209,16 @@ struct intel_fbdev { ...@@ -209,6 +209,16 @@ struct intel_fbdev {
unsigned long vma_flags; unsigned long vma_flags;
async_cookie_t cookie; async_cookie_t cookie;
int preferred_bpp; int preferred_bpp;
/* Whether or not fbdev hpd processing is temporarily suspended */
bool hpd_suspended : 1;
/* Set when a hotplug was received while HPD processing was
* suspended
*/
bool hpd_waiting : 1;
/* Protects hpd_suspended */
struct mutex hpd_lock;
}; };
struct intel_encoder { struct intel_encoder {
......
drivers/gpu/drm/i915/intel_fbdev.c
View file @ 545aabcb
...@@ -679,6 +679,7 @@ int intel_fbdev_init(struct drm_device *dev) ...@@ -679,6 +679,7 @@ int intel_fbdev_init(struct drm_device *dev)
if (ifbdev == NULL) if (ifbdev == NULL)
return -ENOMEM; return -ENOMEM;
mutex_init(&ifbdev->hpd_lock);
drm_fb_helper_prepare(dev, &ifbdev->helper, &intel_fb_helper_funcs); drm_fb_helper_prepare(dev, &ifbdev->helper, &intel_fb_helper_funcs);
if (!intel_fbdev_init_bios(dev, ifbdev)) if (!intel_fbdev_init_bios(dev, ifbdev))
...@@ -752,6 +753,26 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv) ...@@ -752,6 +753,26 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
intel_fbdev_destroy(ifbdev); intel_fbdev_destroy(ifbdev);
} }
/* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD
* processing, fbdev will perform a full connector reprobe if a hotplug event
* was received while HPD was suspended.
*/
static void intel_fbdev_hpd_set_suspend(struct intel_fbdev *ifbdev, int state)
{
bool send_hpd = false;
mutex_lock(&ifbdev->hpd_lock);
ifbdev->hpd_suspended = state == FBINFO_STATE_SUSPENDED;
send_hpd = !ifbdev->hpd_suspended && ifbdev->hpd_waiting;
ifbdev->hpd_waiting = false;
mutex_unlock(&ifbdev->hpd_lock);
if (send_hpd) {
DRM_DEBUG_KMS("Handling delayed fbcon HPD event\n");
drm_fb_helper_hotplug_event(&ifbdev->helper);
}
}
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous) void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
{ {
struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_private *dev_priv = to_i915(dev);
...@@ -773,6 +794,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous ...@@ -773,6 +794,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
*/ */
if (state != FBINFO_STATE_RUNNING) if (state != FBINFO_STATE_RUNNING)
flush_work(&dev_priv->fbdev_suspend_work); flush_work(&dev_priv->fbdev_suspend_work);
console_lock(); console_lock();
} else { } else {
/* /*
...@@ -800,17 +822,26 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous ...@@ -800,17 +822,26 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
drm_fb_helper_set_suspend(&ifbdev->helper, state); drm_fb_helper_set_suspend(&ifbdev->helper, state);
console_unlock(); console_unlock();
intel_fbdev_hpd_set_suspend(ifbdev, state);
} }
void intel_fbdev_output_poll_changed(struct drm_device *dev) void intel_fbdev_output_poll_changed(struct drm_device *dev)
{ {
struct intel_fbdev *ifbdev = to_i915(dev)->fbdev; struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
bool send_hpd;
if (!ifbdev) if (!ifbdev)
return; return;
intel_fbdev_sync(ifbdev); intel_fbdev_sync(ifbdev);
if (ifbdev->vma || ifbdev->helper.deferred_setup)
mutex_lock(&ifbdev->hpd_lock);
send_hpd = !ifbdev->hpd_suspended;
ifbdev->hpd_waiting = true;
mutex_unlock(&ifbdev->hpd_lock);
if (send_hpd && (ifbdev->vma || ifbdev->helper.deferred_setup))
drm_fb_helper_hotplug_event(&ifbdev->helper); drm_fb_helper_hotplug_event(&ifbdev->helper);
} }
......
drivers/gpu/drm/i915/intel_opregion.c
View file @ 545aabcb
...@@ -55,7 +55,12 @@ ...@@ -55,7 +55,12 @@
struct opregion_header { struct opregion_header {
u8 signature[16]; u8 signature[16];
u32 size; u32 size;
u32 opregion_ver; struct {
u8 rsvd;
u8 revision;
u8 minor;
u8 major;
} __packed over;
u8 bios_ver[32]; u8 bios_ver[32];
u8 vbios_ver[16]; u8 vbios_ver[16];
u8 driver_ver[16]; u8 driver_ver[16];
...@@ -119,7 +124,8 @@ struct opregion_asle { ...@@ -119,7 +124,8 @@ struct opregion_asle {
u64 fdss; u64 fdss;
u32 fdsp; u32 fdsp;
u32 stat; u32 stat;
u64 rvda; /* Physical address of raw vbt data */ u64 rvda; /* Physical (2.0) or relative from opregion (2.1+)
* address of raw VBT data. */
u32 rvds; /* Size of raw vbt data */ u32 rvds; /* Size of raw vbt data */
u8 rsvd[58]; u8 rsvd[58];
} __packed; } __packed;
...@@ -925,6 +931,11 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) ...@@ -925,6 +931,11 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
opregion->header = base; opregion->header = base;
opregion->lid_state = base + ACPI_CLID; opregion->lid_state = base + ACPI_CLID;
DRM_DEBUG_DRIVER("ACPI OpRegion version %u.%u.%u\n",
opregion->header->over.major,
opregion->header->over.minor,
opregion->header->over.revision);
mboxes = opregion->header->mboxes; mboxes = opregion->header->mboxes;
if (mboxes & MBOX_ACPI) { if (mboxes & MBOX_ACPI) {
DRM_DEBUG_DRIVER("Public ACPI methods supported\n"); DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
...@@ -953,11 +964,26 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) ...@@ -953,11 +964,26 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
if (dmi_check_system(intel_no_opregion_vbt)) if (dmi_check_system(intel_no_opregion_vbt))
goto out; goto out;
if (opregion->header->opregion_ver >= 2 && opregion->asle && if (opregion->header->over.major >= 2 && opregion->asle &&
opregion->asle->rvda && opregion->asle->rvds) { opregion->asle->rvda && opregion->asle->rvds) {
opregion->rvda = memremap(opregion->asle->rvda, resource_size_t rvda = opregion->asle->rvda;
opregion->asle->rvds,
/*
* opregion 2.0: rvda is the physical VBT address.
*
* opregion 2.1+: rvda is unsigned, relative offset from
* opregion base, and should never point within opregion.
*/
if (opregion->header->over.major > 2 ||
opregion->header->over.minor >= 1) {
WARN_ON(rvda < OPREGION_SIZE);
rvda += asls;
}
opregion->rvda = memremap(rvda, opregion->asle->rvds,
MEMREMAP_WB); MEMREMAP_WB);
vbt = opregion->rvda; vbt = opregion->rvda;
vbt_size = opregion->asle->rvds; vbt_size = opregion->asle->rvds;
if (intel_bios_is_valid_vbt(vbt, vbt_size)) { if (intel_bios_is_valid_vbt(vbt, vbt_size)) {
...@@ -967,6 +993,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) ...@@ -967,6 +993,8 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv)
goto out; goto out;
} else { } else {
DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n"); DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n");
memunmap(opregion->rvda);
opregion->rvda = NULL;
} }
} }
......
drivers/gpu/drm/i915/intel_ringbuffer.h
View file @ 545aabcb
...@@ -415,16 +415,17 @@ struct intel_engine_cs { ...@@ -415,16 +415,17 @@ struct intel_engine_cs {
/** /**
* @enable_count: Reference count for the enabled samplers. * @enable_count: Reference count for the enabled samplers.
* *
* Index number corresponds to the bit number from @enable. * Index number corresponds to @enum drm_i915_pmu_engine_sample.
*/ */
unsigned int enable_count[I915_PMU_SAMPLE_BITS]; unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT];
/** /**
* @sample: Counter values for sampling events. * @sample: Counter values for sampling events.
* *
* Our internal timer stores the current counters in this field. * Our internal timer stores the current counters in this field.
*
* Index number corresponds to @enum drm_i915_pmu_engine_sample.
*/ */
#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_COUNT];
struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX];
} pmu; } pmu;
/* /*
......
drivers/gpu/drm/imx/imx-ldb.c
View file @ 545aabcb
...@@ -643,8 +643,10 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) ...@@ -643,8 +643,10 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
int bus_format; int bus_format;
ret = of_property_read_u32(child, "reg", &i); ret = of_property_read_u32(child, "reg", &i);
if (ret || i < 0 || i > 1) if (ret || i < 0 || i > 1) {
return -EINVAL; ret = -EINVAL;
goto free_child;
}
if (!of_device_is_available(child)) if (!of_device_is_available(child))
continue; continue;
...@@ -657,7 +659,6 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) ...@@ -657,7 +659,6 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
channel = &imx_ldb->channel[i]; channel = &imx_ldb->channel[i];
channel->ldb = imx_ldb; channel->ldb = imx_ldb;
channel->chno = i; channel->chno = i;
channel->child = child;
/* /*
* The output port is port@4 with an external 4-port mux or * The output port is port@4 with an external 4-port mux or
...@@ -667,13 +668,13 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) ...@@ -667,13 +668,13 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
imx_ldb->lvds_mux ? 4 : 2, 0, imx_ldb->lvds_mux ? 4 : 2, 0,
&channel->panel, &channel->bridge); &channel->panel, &channel->bridge);
if (ret && ret != -ENODEV) if (ret && ret != -ENODEV)
return ret; goto free_child;
/* panel ddc only if there is no bridge */ /* panel ddc only if there is no bridge */
if (!channel->bridge) { if (!channel->bridge) {
ret = imx_ldb_panel_ddc(dev, channel, child); ret = imx_ldb_panel_ddc(dev, channel, child);
if (ret) if (ret)
return ret; goto free_child;
} }
bus_format = of_get_bus_format(dev, child); bus_format = of_get_bus_format(dev, child);
...@@ -689,18 +690,26 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data) ...@@ -689,18 +690,26 @@ static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
if (bus_format < 0) { if (bus_format < 0) {
dev_err(dev, "could not determine data mapping: %d\n", dev_err(dev, "could not determine data mapping: %d\n",
bus_format); bus_format);
return bus_format; ret = bus_format;
goto free_child;
} }
channel->bus_format = bus_format; channel->bus_format = bus_format;
channel->child = child;
ret = imx_ldb_register(drm, channel); ret = imx_ldb_register(drm, channel);
if (ret) if (ret) {
return ret; channel->child = NULL;
goto free_child;
}
} }
dev_set_drvdata(dev, imx_ldb); dev_set_drvdata(dev, imx_ldb);
return 0; return 0;
free_child:
of_node_put(child);
return ret;
} }
static void imx_ldb_unbind(struct device *dev, struct device *master, static void imx_ldb_unbind(struct device *dev, struct device *master,
......
drivers/gpu/drm/imx/ipuv3-plane.c
View file @ 545aabcb
...@@ -370,9 +370,9 @@ static int ipu_plane_atomic_check(struct drm_plane *plane, ...@@ -370,9 +370,9 @@ static int ipu_plane_atomic_check(struct drm_plane *plane,
if (ret) if (ret)
return ret; return ret;
/* CRTC should be enabled */ /* nothing to check when disabling or disabled */
if (!crtc_state->enable) if (!crtc_state->enable)
return -EINVAL; return 0;
switch (plane->type) { switch (plane->type) {
case DRM_PLANE_TYPE_PRIMARY: case DRM_PLANE_TYPE_PRIMARY:
......
drivers/gpu/drm/scheduler/sched_entity.c
View file @ 545aabcb
...@@ -440,14 +440,11 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) ...@@ -440,14 +440,11 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity)
while ((entity->dependency = while ((entity->dependency =
sched->ops->dependency(sched_job, entity))) { sched->ops->dependency(sched_job, entity))) {
trace_drm_sched_job_wait_dep(sched_job, entity->dependency);
if (drm_sched_entity_add_dependency_cb(entity)) { if (drm_sched_entity_add_dependency_cb(entity))
trace_drm_sched_job_wait_dep(sched_job,
entity->dependency);
return NULL; return NULL;
} }
}
/* skip jobs from entity that marked guilty */ /* skip jobs from entity that marked guilty */
if (entity->guilty && atomic_read(entity->guilty)) if (entity->guilty && atomic_read(entity->guilty))
......
drivers/gpu/drm/vkms/vkms_crc.c
View file @ 545aabcb
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0+
#include "vkms_drv.h" #include "vkms_drv.h"
#include <linux/crc32.h> #include <linux/crc32.h>
#include <drm/drm_atomic.h> #include <drm/drm_atomic.h>
......
drivers/gpu/drm/vkms/vkms_crtc.c
View file @ 545aabcb
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0+
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "vkms_drv.h" #include "vkms_drv.h"
#include <drm/drm_atomic_helper.h> #include <drm/drm_atomic_helper.h>
......
drivers/gpu/drm/vkms/vkms_drv.c
View file @ 545aabcb
/* // SPDX-License-Identifier: GPL-2.0+
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/** /**
* DOC: vkms (Virtual Kernel Modesetting) * DOC: vkms (Virtual Kernel Modesetting)
......
drivers/gpu/drm/vkms/vkms_drv.h
View file @ 545aabcb
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef _VKMS_DRV_H_ #ifndef _VKMS_DRV_H_
#define _VKMS_DRV_H_ #define _VKMS_DRV_H_
......
drivers/gpu/drm/vkms/vkms_gem.c
View file @ 545aabcb
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0+
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/shmem_fs.h> #include <linux/shmem_fs.h>
......
drivers/gpu/drm/vkms/vkms_output.c
View file @ 545aabcb
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0+
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "vkms_drv.h" #include "vkms_drv.h"
#include <drm/drm_crtc_helper.h> #include <drm/drm_crtc_helper.h>
......
drivers/gpu/drm/vkms/vkms_plane.c
View file @ 545aabcb
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0+
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "vkms_drv.h" #include "vkms_drv.h"
#include <drm/drm_plane_helper.h> #include <drm/drm_plane_helper.h>
......
drivers/gpu/ipu-v3/ipu-common.c
View file @ 545aabcb
...@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = { ...@@ -898,8 +898,8 @@ static struct ipu_devtype ipu_type_imx51 = {
.cpmem_ofs = 0x1f000000, .cpmem_ofs = 0x1f000000,
.srm_ofs = 0x1f040000, .srm_ofs = 0x1f040000,
.tpm_ofs = 0x1f060000, .tpm_ofs = 0x1f060000,
.csi0_ofs = 0x1f030000, .csi0_ofs = 0x1e030000,
.csi1_ofs = 0x1f038000, .csi1_ofs = 0x1e038000,
.ic_ofs = 0x1e020000, .ic_ofs = 0x1e020000,
.disp0_ofs = 0x1e040000, .disp0_ofs = 0x1e040000,
.disp1_ofs = 0x1e048000, .disp1_ofs = 0x1e048000,
...@@ -914,8 +914,8 @@ static struct ipu_devtype ipu_type_imx53 = { ...@@ -914,8 +914,8 @@ static struct ipu_devtype ipu_type_imx53 = {
.cpmem_ofs = 0x07000000, .cpmem_ofs = 0x07000000,
.srm_ofs = 0x07040000, .srm_ofs = 0x07040000,
.tpm_ofs = 0x07060000, .tpm_ofs = 0x07060000,
.csi0_ofs = 0x07030000, .csi0_ofs = 0x06030000,
.csi1_ofs = 0x07038000, .csi1_ofs = 0x06038000,
.ic_ofs = 0x06020000, .ic_ofs = 0x06020000,
.disp0_ofs = 0x06040000, .disp0_ofs = 0x06040000,
.disp1_ofs = 0x06048000, .disp1_ofs = 0x06048000,
......
drivers/gpu/ipu-v3/ipu-pre.c
View file @ 545aabcb
...@@ -106,6 +106,7 @@ struct ipu_pre { ...@@ -106,6 +106,7 @@ struct ipu_pre {
void *buffer_virt; void *buffer_virt;
bool in_use; bool in_use;
unsigned int safe_window_end; unsigned int safe_window_end;
unsigned int last_bufaddr;
}; };
static DEFINE_MUTEX(ipu_pre_list_mutex); static DEFINE_MUTEX(ipu_pre_list_mutex);
...@@ -185,6 +186,7 @@ void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, ...@@ -185,6 +186,7 @@ void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF);
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
pre->last_bufaddr = bufaddr;
val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) |
IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) |
...@@ -242,7 +244,11 @@ void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr) ...@@ -242,7 +244,11 @@ void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr)
unsigned short current_yblock; unsigned short current_yblock;
u32 val; u32 val;
if (bufaddr == pre->last_bufaddr)
return;
writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF);
pre->last_bufaddr = bufaddr;
do { do {
if (time_after(jiffies, timeout)) { if (time_after(jiffies, timeout)) {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7