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Commit 55d42d27 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events: Add KnightsLanding V9 event file 

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-3x2we5evro8uhwmergz1mbd7@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 902ea4ee
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tools/perf/pmu-events/arch/x86/knightslanding/cache.json 0 → 100644
View file @ 55d42d27
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tools/perf/pmu-events/arch/x86/knightslanding/frontend.json 0 → 100644
View file @ 55d42d27
[
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches, including uncacheable fetches."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "ICACHE.HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that hit the instruction cache."
},
{
"EventCode": "0x80",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "ICACHE.MISSES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding."
},
{
"EventCode": "0xE7",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MS_DECODED.MS_ENTRY",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the MSROM starts a flow of uops."
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/knightslanding/memory.json 0 → 100644
View file @ 55d42d27
[
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the machine clears due to memory ordering hazards"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400070 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200070 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000070 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800070 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Prefetch requests that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x01004032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x00802032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x01010032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x00808032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100403091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080203091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101003091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080803091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100408000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080208000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101008000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080808000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100402000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080202000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101002000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080802000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L1 data HW prefetches that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100401000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080201000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101001000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080801000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400100 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR",
"MSRIndex": "0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200100 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR",
"MSRIndex": "0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000100 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR",
"MSRIndex": "0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800100 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR",
"MSRIndex": "0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x2000020080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400040 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200040 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000040 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800040 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 code HW prefetches that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x2000020020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from any NON_DRAM system address. This includes MMIO transactions",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0100400001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Far or Other tile L2 hit far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080200001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from MCDRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0101000001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Far. ",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0080800001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for data responses from DRAM Local.",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600100 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM",
"MSRIndex": "0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial writes (UC or WT or WP and should be programmed on PMC1) that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180601000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180608000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180603091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x01806032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0180600070 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Prefetch requests that accounts for responses from MCDRAM (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800001 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800002 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data writes that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800004 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand code reads and prefetch code reads that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800020 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800040 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L2 code HW prefetches that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800080 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800200 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800400 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Bus locks and split lock requests that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181801000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Software Prefetches that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181802000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts L1 data HW prefetches that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181808000 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any request that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181803091 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800022 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand cacheable data write requests that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x0181800044 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts Demand code reads and prefetch code read requests that accounts for responses from DDR (local and far)",
"Offcore": "1"
},
{
"EventCode": "0xB7",
"MSRValue": "0x01818032f7 ",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.DDR",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any Read request that accounts for responses from DDR (local and far)",
"Offcore": "1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json 0 → 100644
View file @ 55d42d27
[
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired"
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0x7e",
"EventName": "BR_INST_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfe",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xf9",
"EventName": "BR_INST_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfd",
"EventName": "BR_INST_RETIRED.REL_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near relative CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xfb",
"EventName": "BR_INST_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near indirect CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xf7",
"EventName": "BR_INST_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of near RET branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xeb",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP."
},
{
"PEBS": "1",
"EventCode": "0xC4",
"Counter": "0,1",
"UMask": "0xbf",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of far branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired"
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0x7e",
"EventName": "BR_MISP_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfe",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfb",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xf7",
"EventName": "BR_MISP_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xeb",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP."
},
{
"PublicDescription": "This event counts the number of micro-ops retired that were supplied from MSROM.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "UOPS_RETIRED.MS",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of micro-ops retired that are from the complex flows issued by the micro-sequencer (MS)."
},
{
"PublicDescription": "This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. ",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of micro-ops retired"
},
{
"PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "UOPS_RETIRED.SCALAR_SIMD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt."
},
{
"PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
"EventCode": "0xC2",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "UOPS_RETIRED.PACKED_SIMD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies."
},
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "MACHINE_CLEARS.SMC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page"
},
{
"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of floating operations retired that required microcode assists"
},
{
"EventCode": "0xC3",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "MACHINE_CLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all nukes"
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "NO_ALLOC_CYCLES.ROB_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the ROB is full"
},
{
"PublicDescription": "This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire.",
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "NO_ALLOC_CYCLES.MISPREDICTS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "NO_ALLOC_CYCLES.RAT_STALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted. "
},
{
"PublicDescription": "This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched.",
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x90",
"EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when no micro-ops are allocated, the IQ is empty, and no other condition is blocking allocation."
},
{
"EventCode": "0xCA",
"Counter": "0,1",
"UMask": "0x7f",
"EventName": "NO_ALLOC_CYCLES.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles when no micro-ops are allocated for any reason."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "RS_FULL_STALL.MEC",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry."
},
{
"EventCode": "0xCB",
"Counter": "0,1",
"UMask": "0x1f",
"EventName": "RS_FULL_STALL.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full. "
},
{
"EventCode": "0xC0",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the total number of instructions retired"
},
{
"PublicDescription": "This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides.",
"EventCode": "0xCD",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CYCLES_DIV_BUSY.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles the number of core cycles when divider is busy. Does not imply a stall waiting for the divider. "
},
{
"PublicDescription": "This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps.",
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of instructions retired"
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.THREAD_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted core clock cycles"
},
{
"EventCode": "0x3C",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
"BriefDescription": "Counts the number of unhalted reference clock cycles"
},
{
"PublicDescription": "This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter\r\n",
"EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.THREAD",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles"
},
{
"EventCode": "0x00",
"Counter": "Fixed counter 3",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles"
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end."
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end."
},
{
"EventCode": "0xE6",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end."
},
{
"PEBS": "1",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address partially overlaps with a store ",
"Data_LA": "1"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load gets blocked because its address overlaps with a store whose data is not ready"
},
{
"PublicDescription": "This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once.",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x4",
"EventName": "RECYCLEQ.ST_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired store that is a cache line split. Each split should be counted only once."
},
{
"PEBS": "1",
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "RECYCLEQ.LD_SPLITS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of occurences a retired load that is a cache line split. Each split should be counted only once.",
"Data_LA": "1"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x10",
"EventName": "RECYCLEQ.LOCK",
"SampleAfterValue": "200003",
"BriefDescription": "Counts all the retired locked loads. It does not include stores because we would double count if we count stores"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "RECYCLEQ.STA_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full"
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x40",
"EventName": "RECYCLEQ.ANY_LD",
"SampleAfterValue": "200003",
"BriefDescription": "Counts any retired load that was pushed into the recycle queue for any reason."
},
{
"EventCode": "0x03",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "RECYCLEQ.ANY_ST",
"SampleAfterValue": "200003",
"BriefDescription": "Counts any retired store that was pushed into the recycle queue for any reason."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xf9",
"EventName": "BR_MISP_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xfd",
"EventName": "BR_MISP_RETIRED.REL_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired."
},
{
"PEBS": "1",
"EventCode": "0xC5",
"Counter": "0,1",
"UMask": "0xbf",
"EventName": "BR_MISP_RETIRED.FAR_BRANCH",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of mispredicted far branch instructions retired."
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json 0 → 100644
View file @ 55d42d27
[
{
"PEBS": "1",
"EventCode": "0x04",
"Counter": "0,1",
"UMask": "0x8",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
"Data_LA": "1"
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted",
"EdgeDetect": "1"
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included."
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total I-side page walks that are completed.",
"EdgeDetect": "1"
},
{
"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress. ",
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cycles for page walks started in speculative path will also be included."
},
{
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "100003",
"BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
"EdgeDetect": "1"
},
{
"PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Counts the total number of core cycles for all the page walks. The cycles for page walks started in speculative path will also be included."
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/mapfile.csv
View file @ 55d42d27
......@@ -16,3 +16,4 @@ GenuineIntel-6-3F,v17,haswellx,core
GenuineIntel-6-3A,v18,ivybridge,core
GenuineIntel-6-3E,v19,ivytown,core
GenuineIntel-6-2D,v20,jaketown,core
GenuineIntel-6-57,v9,knightslanding,core
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