Commit 55da9c08 authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64

Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs device tree changes:

- Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI
  (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog

- Anup also adds a binding documentation for the ARM SP805 watchdog since there
  was not one in tree before

- Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using
  the iProc-compatible binding

- Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and
  reference platforms

* tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  dt-bindings: Add documentation for Broadcom Vulcan
  arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2
  arm64: dts: Add ARM SP805 watchdog DT node for NS2
  dt-bindings: watchdog: Add ARM SP805 DT bindings
  arm64: dts: Add ARM SP804 timer DT nodes for NS2
  arm64: dts: Add SDHCI DT node for NS2
parents 29de0e39 f008decc
Broadcom Vulcan device tree bindings
------------------------------------
Boards with Broadcom Vulcan shall have the following root property:
Broadcom Vulcan Evaluation Board:
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
Generic Vulcan board:
compatible = "brcm,vulcan-soc";
...@@ -167,6 +167,7 @@ nodes to be present and contain the properties described below. ...@@ -167,6 +167,7 @@ nodes to be present and contain the properties described below.
"arm,cortex-r5" "arm,cortex-r5"
"arm,cortex-r7" "arm,cortex-r7"
"brcm,brahma-b15" "brcm,brahma-b15"
"brcm,vulcan"
"cavium,thunder" "cavium,thunder"
"faraday,fa526" "faraday,fa526"
"intel,sa110" "intel,sa110"
......
ARM AMBA Primecell SP805 Watchdog
Required properties:
- compatible: Should be "arm,sp805" & "arm,primecell"
- reg: Should contain location and length for watchdog timer register.
- interrupts: Should contain the list of watchdog timer interrupts.
- clocks: clocks driving the watchdog timer hardware. This list should be 2
clocks. With 2 clocks, the order is wdogclk clock, apb_pclk.
Example:
watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb_pclk>,<&apb_pclk>;
clock-names = "wdogclk", "apb_pclk";
};
...@@ -52,6 +52,14 @@ memory { ...@@ -52,6 +52,14 @@ memory {
}; };
}; };
&pcie0 {
status = "ok";
};
&pcie4 {
status = "ok";
};
&i2c0 { &i2c0 {
status = "ok"; status = "ok";
}; };
...@@ -64,6 +72,10 @@ &uart3 { ...@@ -64,6 +72,10 @@ &uart3 {
status = "ok"; status = "ok";
}; };
&sdio0 {
status = "ok";
};
&nand { &nand {
nandcs@0 { nandcs@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
......
...@@ -137,6 +137,80 @@ iprocslow: iprocslow { ...@@ -137,6 +137,80 @@ iprocslow: iprocslow {
}; };
}; };
pcie0: pcie@20020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x20020000 0 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
brcm,pcie-ob;
brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x00000000>;
brcm,pcie-ob-window-size = <256>;
status = "disabled";
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
<GIC_SPI 278 IRQ_TYPE_NONE>,
<GIC_SPI 279 IRQ_TYPE_NONE>,
<GIC_SPI 280 IRQ_TYPE_NONE>;
brcm,num-eq-region = <1>;
brcm,num-msi-msg-region = <1>;
};
};
pcie4: pcie@50020000 {
compatible = "brcm,iproc-pcie";
reg = <0 0x50020000 0 0x1000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
linux,pci-domain = <4>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
brcm,pcie-ob;
brcm,pcie-ob-oarr-size;
brcm,pcie-ob-axi-offset = <0x30000000>;
brcm,pcie-ob-window-size = <256>;
status = "disabled";
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
<GIC_SPI 302 IRQ_TYPE_NONE>,
<GIC_SPI 303 IRQ_TYPE_NONE>,
<GIC_SPI 304 IRQ_TYPE_NONE>;
};
};
soc: soc { soc: soc {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
...@@ -256,6 +330,46 @@ gic: interrupt-controller@65210000 { ...@@ -256,6 +330,46 @@ gic: interrupt-controller@65210000 {
<0x65260000 0x1000>; <0x65260000 0x1000>;
}; };
timer0: timer@66030000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66030000 0x1000>;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer1: timer@66040000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66040000 0x1000>;
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer2: timer@66050000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66050000 0x1000>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
timer3: timer@66060000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x66060000 0x1000>;
interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>,
<&iprocslow>,
<&iprocslow>;
clock-names = "timer1", "timer2", "apb_pclk";
};
i2c0: i2c@66080000 { i2c0: i2c@66080000 {
compatible = "brcm,iproc-i2c"; compatible = "brcm,iproc-i2c";
reg = <0x66080000 0x100>; reg = <0x66080000 0x100>;
...@@ -266,6 +380,14 @@ i2c0: i2c@66080000 { ...@@ -266,6 +380,14 @@ i2c0: i2c@66080000 {
status = "disabled"; status = "disabled";
}; };
wdt0: watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
clock-names = "wdogclk", "apb_pclk";
};
i2c1: i2c@660b0000 { i2c1: i2c@660b0000 {
compatible = "brcm,iproc-i2c"; compatible = "brcm,iproc-i2c";
reg = <0x660b0000 0x100>; reg = <0x660b0000 0x100>;
...@@ -291,6 +413,24 @@ hwrng: hwrng@66220000 { ...@@ -291,6 +413,24 @@ hwrng: hwrng@66220000 {
reg = <0x66220000 0x28>; reg = <0x66220000 0x28>;
}; };
sdio0: sdhci@66420000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66420000 0x100>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
status = "disabled";
};
sdio1: sdhci@66430000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x66430000 0x100>;
interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
status = "disabled";
};
nand: nand@66460000 { nand: nand@66460000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x66460000 0x600>, reg = <0x66460000 0x600>,
......
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