Commit 5703ddb0 authored by Don Fry's avatar Don Fry Committed by John W. Linville

iwlagn: move ucode_write_complete from priv to trans structure

ucode_write_complete is used for ucode loading.  Move it as part of
restructuring work out of the priv structure.
Signed-off-by: default avatarDon Fry <donald.h.fry@intel.com>
Signed-off-by: default avatarWey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent b6cb406a
...@@ -75,48 +75,49 @@ static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = { ...@@ -75,48 +75,49 @@ static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
/* /*
* ucode * ucode
*/ */
static int iwlagn_load_section(struct iwl_priv *priv, const char *name, static int iwlagn_load_section(struct iwl_trans *trans, const char *name,
struct fw_desc *image, u32 dst_addr) struct fw_desc *image, u32 dst_addr)
{ {
struct iwl_bus *bus = bus(trans);
dma_addr_t phy_addr = image->p_addr; dma_addr_t phy_addr = image->p_addr;
u32 byte_cnt = image->len; u32 byte_cnt = image->len;
int ret; int ret;
priv->ucode_write_complete = 0; trans->ucode_write_complete = 0;
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
(iwl_get_dma_hi_addr(phy_addr) (iwl_get_dma_hi_addr(phy_addr)
<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
iwl_write_direct32(bus(priv), iwl_write_direct32(bus,
FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name); IWL_DEBUG_FW(bus, "%s uCode section being loaded...\n", name);
ret = wait_event_timeout(priv->shrd->wait_command_queue, ret = wait_event_timeout(trans->shrd->wait_command_queue,
priv->ucode_write_complete, 5 * HZ); trans->ucode_write_complete, 5 * HZ);
if (!ret) { if (!ret) {
IWL_ERR(priv, "Could not load the %s uCode section\n", IWL_ERR(trans, "Could not load the %s uCode section\n",
name); name);
return -ETIMEDOUT; return -ETIMEDOUT;
} }
...@@ -129,12 +130,12 @@ static int iwlagn_load_given_ucode(struct iwl_priv *priv, ...@@ -129,12 +130,12 @@ static int iwlagn_load_given_ucode(struct iwl_priv *priv,
{ {
int ret = 0; int ret = 0;
ret = iwlagn_load_section(priv, "INST", &image->code, ret = iwlagn_load_section(trans(priv), "INST", &image->code,
IWLAGN_RTC_INST_LOWER_BOUND); IWLAGN_RTC_INST_LOWER_BOUND);
if (ret) if (ret)
return ret; return ret;
return iwlagn_load_section(priv, "DATA", &image->data, return iwlagn_load_section(trans(priv), "DATA", &image->data,
IWLAGN_RTC_DATA_LOWER_BOUND); IWLAGN_RTC_DATA_LOWER_BOUND);
} }
......
...@@ -920,7 +920,6 @@ struct iwl_priv { ...@@ -920,7 +920,6 @@ struct iwl_priv {
struct fw_img ucode_wowlan; struct fw_img ucode_wowlan;
enum iwlagn_ucode_type ucode_type; enum iwlagn_ucode_type ucode_type;
u8 ucode_write_complete; /* the image write is complete */
char firmware_name[25]; char firmware_name[25];
struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX]; struct iwl_rxon_context contexts[NUM_IWL_RXON_CTX];
......
...@@ -1108,7 +1108,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans) ...@@ -1108,7 +1108,7 @@ void iwl_irq_tasklet(struct iwl_trans *trans)
isr_stats->tx++; isr_stats->tx++;
handled |= CSR_INT_BIT_FH_TX; handled |= CSR_INT_BIT_FH_TX;
/* Wake up uCode load routine, now that load is complete */ /* Wake up uCode load routine, now that load is complete */
priv(trans)->ucode_write_complete = 1; trans->ucode_write_complete = 1;
wake_up(&trans->shrd->wait_command_queue); wake_up(&trans->shrd->wait_command_queue);
} }
......
...@@ -212,12 +212,15 @@ struct iwl_trans_ops { ...@@ -212,12 +212,15 @@ struct iwl_trans_ops {
* @ops - pointer to iwl_trans_ops * @ops - pointer to iwl_trans_ops
* @shrd - pointer to iwl_shared which holds shared data from the upper layer * @shrd - pointer to iwl_shared which holds shared data from the upper layer
* @hcmd_lock: protects HCMD * @hcmd_lock: protects HCMD
* @ucode_write_complete: indicates that the ucode has been copied.
*/ */
struct iwl_trans { struct iwl_trans {
const struct iwl_trans_ops *ops; const struct iwl_trans_ops *ops;
struct iwl_shared *shrd; struct iwl_shared *shrd;
spinlock_t hcmd_lock; spinlock_t hcmd_lock;
u8 ucode_write_complete; /* the image write is complete */
/* pointer to trans specific struct */ /* pointer to trans specific struct */
/*Ensure that this pointer will always be aligned to sizeof pointer */ /*Ensure that this pointer will always be aligned to sizeof pointer */
char trans_specific[0] __attribute__((__aligned__(sizeof(void *)))); char trans_specific[0] __attribute__((__aligned__(sizeof(void *))));
......
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