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Commit 57afe2f0 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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[media] drx-j: Don't use CamelCase 

There's no reason at all to use CamelCase here. Convert all of
them to normal case.
Acked-by: default avatarDevin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 7ef66759
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Showing with 6844 additions and 6844 deletions
drivers/media/dvb-frontends/drx39xyj/bsp_i2c.h
View file @ 57afe2f0
......@@ -48,13 +48,13 @@
#include "bsp_types.h"
/*
* This structure contains the I2C address, the device ID and a userData pointer.
* The userData pointer can be used for application specific purposes.
* This structure contains the I2C address, the device ID and a user_data pointer.
* The user_data pointer can be used for application specific purposes.
*/
struct i2c_device_addr {
u16 i2cAddr; /* The I2C address of the device. */
u16 i2cDevId; /* The device identifier. */
void *userData; /* User data pointer */
u16 i2c_addr; /* The I2C address of the device. */
u16 i2c_dev_id; /* The device identifier. */
void *user_data; /* User data pointer */
};
......@@ -74,44 +74,44 @@ Exported FUNCTIONS
------------------------------------------------------------------------------*/
/**
* \fn DRXBSP_I2C_Init()
* \fn drxbsp_i2c_init()
* \brief Initialize I2C communication module.
* \return DRXStatus_t Return status.
* \return drx_status_t Return status.
* \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed.
*/
DRXStatus_t DRXBSP_I2C_Init(void);
drx_status_t drxbsp_i2c_init(void);
/**
* \fn DRXBSP_I2C_Term()
* \fn drxbsp_i2c_term()
* \brief Terminate I2C communication module.
* \return DRXStatus_t Return status.
* \return drx_status_t Return status.
* \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed.
*/
DRXStatus_t DRXBSP_I2C_Term(void);
drx_status_t drxbsp_i2c_term(void);
/**
* \fn DRXStatus_t DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr,
* u16 wCount,
* \fn drx_status_t drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
* u16 w_count,
* u8 *wData,
* struct i2c_device_addr *rDevAddr,
* u16 rCount,
* u8 *rData)
* struct i2c_device_addr *r_dev_addr,
* u16 r_count,
* u8 *r_data)
* \brief Read and/or write count bytes from I2C bus, store them in data[].
* \param wDevAddr The device i2c address and the device ID to write to
* \param wCount The number of bytes to write
* \param w_dev_addr The device i2c address and the device ID to write to
* \param w_count The number of bytes to write
* \param wData The array to write the data to
* \param rDevAddr The device i2c address and the device ID to read from
* \param rCount The number of bytes to read
* \param rData The array to read the data from
* \return DRXStatus_t Return status.
* \param r_dev_addr The device i2c address and the device ID to read from
* \param r_count The number of bytes to read
* \param r_data The array to read the data from
* \return drx_status_t Return status.
* \retval DRX_STS_OK Succes.
* \retval DRX_STS_ERROR Failure.
* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
* 'wdata' contains NULL.
* Idem for 'rcount' and 'rdata'.
* Both wDevAddr and rDevAddr are NULL.
* Both w_dev_addr and r_dev_addr are NULL.
*
* This function must implement an atomic write and/or read action on the I2C bus
* No other process may use the I2C bus when this function is executing.
......@@ -121,25 +121,25 @@ Exported FUNCTIONS
* The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device.
*/
DRXStatus_t DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
u16 wCount,
drx_status_t drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *rDevAddr,
u16 rCount, u8 *rData);
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data);
/**
* \fn DRXBSP_I2C_ErrorText()
* \fn drxbsp_i2c_error_text()
* \brief Returns a human readable error.
* Counter part of numerical DRX_I2C_Error_g.
* Counter part of numerical drx_i2c_error_g.
*
* \return char* Pointer to human readable error text.
*/
char *DRXBSP_I2C_ErrorText(void);
char *drxbsp_i2c_error_text(void);
/**
* \var DRX_I2C_Error_g;
* \var drx_i2c_error_g;
* \brief I2C specific error codes, platform dependent.
*/
extern int DRX_I2C_Error_g;
extern int drx_i2c_error_g;
#endif /* __BSPI2C_H__ */
drivers/media/dvb-frontends/drx39xyj/bsp_tuner.h
View file @ 57afe2f0
......@@ -79,90 +79,90 @@ DEFINES
TYPEDEFS
------------------------------------------------------------------------------*/
typedef u32 TUNERMode_t;
typedef u32 *pTUNERMode_t;
typedef u32 tuner_mode_t;
typedef u32 *ptuner_mode_t;
typedef char *TUNERSubMode_t; /* description of submode */
typedef TUNERSubMode_t *pTUNERSubMode_t;
typedef char *tuner_sub_mode_t; /* description of submode */
typedef tuner_sub_mode_t *ptuner_sub_mode_t;
typedef enum {
TUNER_LOCKED,
TUNER_NOT_LOCKED
} TUNERLockStatus_t, *pTUNERLockStatus_t;
} tuner_lock_status_t, *ptuner_lock_status_t;
typedef struct {
char *name; /* Tuner brand & type name */
s32 minFreqRF; /* Lowest RF input frequency, in kHz */
s32 maxFreqRF; /* Highest RF input frequency, in kHz */
s32 min_freq_rf; /* Lowest RF input frequency, in kHz */
s32 max_freq_rf; /* Highest RF input frequency, in kHz */
u8 subMode; /* Index to sub-mode in use */
pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes */
u8 subModes; /* Number of available sub-modes */
u8 sub_mode; /* Index to sub-mode in use */
ptuner_sub_mode_t sub_modeDescriptions; /* Pointer to description of sub-modes */
u8 sub_modes; /* Number of available sub-modes */
/* The following fields will be either 0, NULL or false and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
bool programmed; /* only valid if selfCheck is OK */
s32 RFfrequency; /* only valid if programmed */
s32 IFfrequency; /* only valid if programmed */
void *self_check; /* gives proof of initialization */
bool programmed; /* only valid if self_check is OK */
s32 r_ffrequency; /* only valid if programmed */
s32 i_ffrequency; /* only valid if programmed */
void *myUserData; /* pointer to associated demod instance */
u16 myCapabilities; /* value for storing application flags */
void *myUser_data; /* pointer to associated demod instance */
u16 my_capabilities; /* value for storing application flags */
} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
} tuner_common_attr_t, *ptuner_common_attr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct TUNERInstance_s *pTUNERInstance_t;
typedef struct tuner_instance_s *p_tuner_instance_t;
typedef DRXStatus_t(*TUNEROpenFunc_t) (pTUNERInstance_t tuner);
typedef DRXStatus_t(*TUNERCloseFunc_t) (pTUNERInstance_t tuner);
typedef drx_status_t(*tuner_open_func_t) (p_tuner_instance_t tuner);
typedef drx_status_t(*tuner_close_func_t) (p_tuner_instance_t tuner);
typedef DRXStatus_t(*TUNERSetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
typedef drx_status_t(*tuner_set_frequency_func_t) (p_tuner_instance_t tuner,
tuner_mode_t mode,
s32
frequency);
typedef DRXStatus_t(*TUNERGetFrequencyFunc_t) (pTUNERInstance_t tuner,
TUNERMode_t mode,
typedef drx_status_t(*tuner_get_frequency_func_t) (p_tuner_instance_t tuner,
tuner_mode_t mode,
s32 *
RFfrequency,
r_ffrequency,
s32 *
IFfrequency);
i_ffrequency);
typedef DRXStatus_t(*TUNERLockStatusFunc_t) (pTUNERInstance_t tuner,
pTUNERLockStatus_t
lockStat);
typedef drx_status_t(*tuner_lock_status_func_t) (p_tuner_instance_t tuner,
ptuner_lock_status_t
lock_stat);
typedef DRXStatus_t(*TUNERi2cWriteReadFunc_t) (pTUNERInstance_t tuner,
typedef drx_status_t(*tune_ri2c_write_read_func_t) (p_tuner_instance_t tuner,
struct i2c_device_addr *
wDevAddr, u16 wCount,
w_dev_addr, u16 w_count,
u8 *wData,
struct i2c_device_addr *
rDevAddr, u16 rCount,
u8 *rData);
r_dev_addr, u16 r_count,
u8 *r_data);
typedef struct {
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
tuner_open_func_t open_func;
tuner_close_func_t close_func;
tuner_set_frequency_func_t set_frequency_func;
tuner_get_frequency_func_t get_frequency_func;
tuner_lock_status_func_t lock_statusFunc;
tune_ri2c_write_read_func_t i2c_write_read_func;
} TUNERFunc_t, *pTUNERFunc_t;
} tuner_func_t, *ptuner_func_t;
typedef struct TUNERInstance_s {
typedef struct tuner_instance_s {
struct i2c_device_addr myI2CDevAddr;
pTUNERCommonAttr_t myCommonAttr;
void *myExtAttr;
pTUNERFunc_t myFunct;
struct i2c_device_addr my_i2c_dev_addr;
ptuner_common_attr_t my_common_attr;
void *my_ext_attr;
ptuner_func_t my_funct;
} TUNERInstance_t;
} tuner_instance_t;
/*------------------------------------------------------------------------------
ENUM
......@@ -176,28 +176,28 @@ STRUCTS
Exported FUNCTIONS
------------------------------------------------------------------------------*/
DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner);
drx_status_t drxbsp_tuner_open(p_tuner_instance_t tuner);
DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner);
drx_status_t drxbsp_tuner_close(p_tuner_instance_t tuner);
DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
drx_status_t drxbsp_tuner_set_frequency(p_tuner_instance_t tuner,
tuner_mode_t mode,
s32 frequency);
DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
TUNERMode_t mode,
s32 *RFfrequency,
s32 *IFfrequency);
drx_status_t drxbsp_tuner_get_frequency(p_tuner_instance_t tuner,
tuner_mode_t mode,
s32 *r_ffrequency,
s32 *i_ffrequency);
DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner,
pTUNERLockStatus_t lockStat);
drx_status_t drxbsp_tuner_lock_status(p_tuner_instance_t tuner,
ptuner_lock_status_t lock_stat);
DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner,
struct i2c_device_addr *wDevAddr,
u16 wCount,
drx_status_t drxbsp_tuner_default_i2c_write_read(p_tuner_instance_t tuner,
struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *rDevAddr,
u16 rCount, u8 *rData);
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data);
/*------------------------------------------------------------------------------
THE END
......
drivers/media/dvb-frontends/drx39xyj/drx39xxj.c
View file @ 57afe2f0
......@@ -33,16 +33,16 @@
static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXPowerMode_t powerMode;
drx_power_mode_t power_mode;
if (enable)
powerMode = DRX_POWER_UP;
power_mode = DRX_POWER_UP;
else
powerMode = DRX_POWER_DOWN;
power_mode = DRX_POWER_DOWN;
result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode);
result = drx_ctrl(demod, DRX_CTRL_POWER_MODE, &power_mode);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Power state change failed\n");
return 0;
......@@ -55,13 +55,13 @@ static int drx39xxj_set_powerstate(struct dvb_frontend *fe, int enable)
static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXLockStatus_t lock_status;
drx_lock_status_t lock_status;
*status = 0;
result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status);
result = drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get lock status!\n");
*status = 0;
......@@ -102,18 +102,18 @@ static int drx39xxj_read_status(struct dvb_frontend *fe, fe_status_t *status)
static int drx39xxj_read_ber(struct dvb_frontend *fe, u32 *ber)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXSigQuality_t sig_quality;
drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get ber!\n");
*ber = 0;
return 0;
}
*ber = sig_quality.postReedSolomonBER;
*ber = sig_quality.post_reed_solomon_ber;
return 0;
}
......@@ -121,11 +121,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
u16 *strength)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXSigQuality_t sig_quality;
drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get signal strength!\n");
*strength = 0;
......@@ -140,11 +140,11 @@ static int drx39xxj_read_signal_strength(struct dvb_frontend *fe,
static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXSigQuality_t sig_quality;
drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not read snr!\n");
*snr = 0;
......@@ -158,18 +158,18 @@ static int drx39xxj_read_snr(struct dvb_frontend *fe, u16 *snr)
static int drx39xxj_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
int result;
DRXSigQuality_t sig_quality;
drx_sig_quality_t sig_quality;
result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
result = drx_ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not get uc blocks!\n");
*ucblocks = 0;
return 0;
}
*ucblocks = sig_quality.packetError;
*ucblocks = sig_quality.packet_error;
return 0;
}
......@@ -180,12 +180,12 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
#endif
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
enum drx_standard standard = DRX_STANDARD_8VSB;
DRXChannel_t channel;
drx_channel_t channel;
int result;
DRXUIOData_t uioData;
DRXChannel_t defChannel = { /* frequency */ 0,
drxuio_data_t uio_data;
drx_channel_t def_channel = { /* frequency */ 0,
/* bandwidth */ DRX_BANDWIDTH_6MHZ,
/* mirror */ DRX_MIRROR_NO,
/* constellation */ DRX_CONSTELLATION_AUTO,
......@@ -216,7 +216,7 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
if (standard != state->current_standard || state->powered_up == 0) {
/* Set the standard (will be powered up if necessary */
result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard);
result = drx_ctrl(demod, DRX_CTRL_SET_STANDARD, &standard);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to set standard! result=%02x\n",
result);
......@@ -227,21 +227,21 @@ static int drx39xxj_set_frontend(struct dvb_frontend *fe)
}
/* set channel parameters */
channel = defChannel;
channel = def_channel;
channel.frequency = p->frequency / 1000;
channel.bandwidth = DRX_BANDWIDTH_6MHZ;
channel.constellation = DRX_CONSTELLATION_AUTO;
/* program channel */
result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
result = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to set channel!\n");
return -EINVAL;
}
/* Just for giggles, let's shut off the LNA again.... */
uioData.uio = DRX_UIO1;
uioData.value = false;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
uio_data.uio = DRX_UIO1;
uio_data.value = false;
result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to disable LNA!\n");
return 0;
......@@ -268,7 +268,7 @@ static int drx39xxj_sleep(struct dvb_frontend *fe)
static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
{
struct drx39xxj_state *state = fe->demodulator_priv;
DRXDemodInstance_t *demod = state->demod;
drx_demod_instance_t *demod = state->demod;
bool i2c_gate_state;
int result;
......@@ -287,7 +287,7 @@ static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
return 0;
}
result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state);
result = drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state);
if (result != DRX_STS_OK) {
printk(KERN_ERR "drx39xxj: could not open i2c gate [%d]\n",
result);
......@@ -325,12 +325,12 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
{
struct drx39xxj_state *state = NULL;
struct i2c_device_addr *demodAddr = NULL;
DRXCommonAttr_t *demodCommAttr = NULL;
DRXJData_t *demodExtAttr = NULL;
DRXDemodInstance_t *demod = NULL;
DRXUIOCfg_t uioCfg;
DRXUIOData_t uioData;
struct i2c_device_addr *demod_addr = NULL;
drx_common_attr_t *demod_comm_attr = NULL;
drxj_data_t *demod_ext_attr = NULL;
drx_demod_instance_t *demod = NULL;
drxuio_cfg_t uio_cfg;
drxuio_data_t uio_data;
int result;
/* allocate memory for the internal state */
......@@ -338,50 +338,50 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
if (state == NULL)
goto error;
demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL);
demod = kmalloc(sizeof(drx_demod_instance_t), GFP_KERNEL);
if (demod == NULL)
goto error;
demodAddr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL);
if (demodAddr == NULL)
demod_addr = kmalloc(sizeof(struct i2c_device_addr), GFP_KERNEL);
if (demod_addr == NULL)
goto error;
demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL);
if (demodCommAttr == NULL)
demod_comm_attr = kmalloc(sizeof(drx_common_attr_t), GFP_KERNEL);
if (demod_comm_attr == NULL)
goto error;
demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL);
if (demodExtAttr == NULL)
demod_ext_attr = kmalloc(sizeof(drxj_data_t), GFP_KERNEL);
if (demod_ext_attr == NULL)
goto error;
/* setup the state */
state->i2c = i2c;
state->demod = demod;
memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t));
memcpy(demod, &drxj_default_demod_g, sizeof(drx_demod_instance_t));
demod->myI2CDevAddr = demodAddr;
memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g,
demod->my_i2c_dev_addr = demod_addr;
memcpy(demod->my_i2c_dev_addr, &drxj_default_addr_g,
sizeof(struct i2c_device_addr));
demod->myI2CDevAddr->userData = state;
demod->myCommonAttr = demodCommAttr;
memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g,
sizeof(DRXCommonAttr_t));
demod->myCommonAttr->microcode = DRXJ_MC_MAIN;
demod->my_i2c_dev_addr->user_data = state;
demod->my_common_attr = demod_comm_attr;
memcpy(demod->my_common_attr, &drxj_default_comm_attr_g,
sizeof(drx_common_attr_t));
demod->my_common_attr->microcode = DRXJ_MC_MAIN;
#if 0
demod->myCommonAttr->verifyMicrocode = false;
demod->my_common_attr->verify_microcode = false;
#endif
demod->myCommonAttr->verifyMicrocode = true;
demod->myCommonAttr->intermediateFreq = 5000;
demod->my_common_attr->verify_microcode = true;
demod->my_common_attr->intermediate_freq = 5000;
demod->myExtAttr = demodExtAttr;
memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t));
((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode =
demod->my_ext_attr = demod_ext_attr;
memcpy(demod->my_ext_attr, &drxj_data_g, sizeof(drxj_data_t));
((drxj_data_t *) demod->my_ext_attr)->uio_sma_tx_mode =
DRX_UIO_MODE_READWRITE;
demod->myTuner = NULL;
demod->my_tuner = NULL;
result = DRX_Open(demod);
result = drx_open(demod);
if (result != DRX_STS_OK) {
printk(KERN_ERR "DRX open failed! Aborting\n");
kfree(state);
......@@ -389,18 +389,18 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
}
/* Turn off the LNA */
uioCfg.uio = DRX_UIO1;
uioCfg.mode = DRX_UIO_MODE_READWRITE;
uio_cfg.uio = DRX_UIO1;
uio_cfg.mode = DRX_UIO_MODE_READWRITE;
/* Configure user-I/O #3: enable read/write */
result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg);
result = drx_ctrl(demod, DRX_CTRL_UIO_CFG, &uio_cfg);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to setup LNA GPIO!\n");
return NULL;
}
uioData.uio = DRX_UIO1;
uioData.value = false;
result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
uio_data.uio = DRX_UIO1;
uio_data.value = false;
result = drx_ctrl(demod, DRX_CTRL_UIO_WRITE, &uio_data);
if (result != DRX_STS_OK) {
printk(KERN_ERR "Failed to disable LNA!\n");
return NULL;
......
drivers/media/dvb-frontends/drx39xyj/drx39xxj.h
View file @ 57afe2f0
......@@ -28,7 +28,7 @@
struct drx39xxj_state {
struct i2c_adapter *i2c;
DRXDemodInstance_t *demod;
drx_demod_instance_t *demod;
enum drx_standard current_standard;
struct dvb_frontend frontend;
int powered_up:1;
......
drivers/media/dvb-frontends/drx39xyj/drx39xxj_dummy.c
View file @ 57afe2f0
......@@ -11,90 +11,90 @@
#include "drx39xxj.h"
/* Dummy function to satisfy drxj.c */
int DRXBSP_TUNER_Open(struct tuner_instance *tuner)
int drxbsp_tuner_open(struct tuner_instance *tuner)
{
return DRX_STS_OK;
}
int DRXBSP_TUNER_Close(struct tuner_instance *tuner)
int drxbsp_tuner_close(struct tuner_instance *tuner)
{
return DRX_STS_OK;
}
int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner,
int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
u32 mode,
s32 centerFrequency)
s32 center_frequency)
{
return DRX_STS_OK;
}
int
DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner,
drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
u32 mode,
s32 *RFfrequency,
s32 *IFfrequency)
s32 *r_ffrequency,
s32 *i_ffrequency)
{
return DRX_STS_OK;
}
int DRXBSP_HST_Sleep(u32 n)
int drxbsp_hst_sleep(u32 n)
{
msleep(n);
return DRX_STS_OK;
}
u32 DRXBSP_HST_Clock(void)
u32 drxbsp_hst_clock(void)
{
return jiffies_to_msecs(jiffies);
}
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n)
int drxbsp_hst_memcmp(void *s1, void *s2, u32 n)
{
return (memcmp(s1, s2, (size_t) n));
}
void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n)
void *drxbsp_hst_memcpy(void *to, void *from, u32 n)
{
return (memcpy(to, from, (size_t) n));
}
int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
u16 wCount,
int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *rDevAddr,
u16 rCount, u8 *rData)
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data)
{
struct drx39xxj_state *state;
struct i2c_msg msg[2];
unsigned int num_msgs;
if (wDevAddr == NULL) {
if (w_dev_addr == NULL) {
/* Read only */
state = rDevAddr->userData;
msg[0].addr = rDevAddr->i2cAddr >> 1;
state = r_dev_addr->user_data;
msg[0].addr = r_dev_addr->i2c_addr >> 1;
msg[0].flags = I2C_M_RD;
msg[0].buf = rData;
msg[0].len = rCount;
msg[0].buf = r_data;
msg[0].len = r_count;
num_msgs = 1;
} else if (rDevAddr == NULL) {
} else if (r_dev_addr == NULL) {
/* Write only */
state = wDevAddr->userData;
msg[0].addr = wDevAddr->i2cAddr >> 1;
state = w_dev_addr->user_data;
msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = wCount;
msg[0].len = w_count;
num_msgs = 1;
} else {
/* Both write and read */
state = wDevAddr->userData;
msg[0].addr = wDevAddr->i2cAddr >> 1;
state = w_dev_addr->user_data;
msg[0].addr = w_dev_addr->i2c_addr >> 1;
msg[0].flags = 0;
msg[0].buf = wData;
msg[0].len = wCount;
msg[1].addr = rDevAddr->i2cAddr >> 1;
msg[0].len = w_count;
msg[1].addr = r_dev_addr->i2c_addr >> 1;
msg[1].flags = I2C_M_RD;
msg[1].buf = rData;
msg[1].len = rCount;
msg[1].buf = r_data;
msg[1].len = r_count;
num_msgs = 2;
}
......@@ -110,17 +110,17 @@ int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
return DRX_STS_OK;
#ifdef DJH_DEBUG
struct drx39xxj_state *state = wDevAddr->userData;
struct drx39xxj_state *state = w_dev_addr->user_data;
struct i2c_msg msg[2] = {
{.addr = wDevAddr->i2cAddr,
.flags = 0, .buf = wData, .len = wCount},
{.addr = rDevAddr->i2cAddr,
.flags = I2C_M_RD, .buf = rData, .len = rCount},
{.addr = w_dev_addr->i2c_addr,
.flags = 0, .buf = wData, .len = w_count},
{.addr = r_dev_addr->i2c_addr,
.flags = I2C_M_RD, .buf = r_data, .len = r_count},
};
printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
wDevAddr->i2cAddr, state->i2c, wCount, rCount);
w_dev_addr->i2c_addr, state->i2c, w_count, r_count);
if (i2c_transfer(state->i2c, msg, 2) != 2) {
printk(KERN_WARNING "drx3933: I2C write/read failed\n");
......
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.c
View file @ 57afe2f0
......@@ -50,133 +50,133 @@
*******************************************************************************/
#include "drx_dap_fasi.h"
#include "drx_driver.h" /* for DRXBSP_HST_Memcpy() */
#include "drx_driver.h" /* for drxbsp_hst_memcpy() */
/*============================================================================*/
/* Function prototypes */
static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data */
u8 *data, /* data to send */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data */
u8 *data, /* data to send */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u8 data, /* data to write */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u8 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* address of register */
dr_xaddr_t raddr, /* address to read back from */
u8 datain, /* data to send */
u8 *dataout); /* data to receive back */
static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u16 data, /* data to write */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u16 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* address of register */
dr_xaddr_t raddr, /* address to read back from */
u16 datain, /* data to send */
u16 *dataout); /* data to receive back */
static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u32 data, /* data to write */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u32 *data, /* buffer to receive data */
DRXflags_t flags); /* special device flags */
dr_xflags_t flags); /* special device flags */
static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* address of register */
dr_xaddr_t raddr, /* address to read back from */
u32 datain, /* data to send */
u32 *dataout); /* data to receive back */
/* The version structure of this protocol implementation */
char drxDapFASIModuleName[] = "FASI Data Access Protocol";
char drxDapFASIVersionText[] = "";
char drx_dap_fasi_module_name[] = "FASI Data Access Protocol";
char drx_dap_fasi_version_text[] = "";
DRXVersion_t drxDapFASIVersion = {
drx_version_t drx_dap_fasi_version = {
DRX_MODULE_DAP, /**< type identifier of the module */
drxDapFASIModuleName, /**< name or description of module */
drx_dap_fasi_module_name, /**< name or description of module */
0, /**< major version number */
0, /**< minor version number */
0, /**< patch version number */
drxDapFASIVersionText /**< version as text string */
drx_dap_fasi_version_text /**< version as text string */
};
/* The structure containing the protocol interface */
DRXAccessFunc_t drxDapFASIFunct_g = {
&drxDapFASIVersion,
DRXDAP_FASI_WriteBlock, /* Supported */
DRXDAP_FASI_ReadBlock, /* Supported */
DRXDAP_FASI_WriteReg8, /* Not supported */
DRXDAP_FASI_ReadReg8, /* Not supported */
DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
DRXDAP_FASI_WriteReg16, /* Supported */
DRXDAP_FASI_ReadReg16, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
DRXDAP_FASI_WriteReg32, /* Supported */
DRXDAP_FASI_ReadReg32, /* Supported */
DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
drx_access_func_t drx_dap_fasi_funct_g = {
&drx_dap_fasi_version,
drxdap_fasi_write_block, /* Supported */
drxdap_fasi_read_block, /* Supported */
drxdap_fasi_write_reg8, /* Not supported */
drxdap_fasi_read_reg8, /* Not supported */
drxdap_fasi_read_modify_write_reg8, /* Not supported */
drxdap_fasi_write_reg16, /* Supported */
drxdap_fasi_read_reg16, /* Supported */
drxdap_fasi_read_modify_write_reg16, /* Supported */
drxdap_fasi_write_reg32, /* Supported */
drxdap_fasi_read_reg32, /* Supported */
drxdap_fasi_read_modify_write_reg32 /* Not supported */
};
/*============================================================================*/
/* Functions not supported by protocol*/
static int DRXDAP_FASI_WriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u8 data, /* data to write */
DRXflags_t flags)
dr_xflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static int DRXDAP_FASI_ReadReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register */
static int drxdap_fasi_read_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register */
u8 *data, /* buffer to receive data */
DRXflags_t flags)
dr_xflags_t flags)
{ /* special device flags */
return DRX_STS_ERROR;
}
static int DRXDAP_FASI_ReadModifyWriteReg8(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
static int drxdap_fasi_read_modify_write_reg8(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* address of register */
dr_xaddr_t raddr, /* address to read back from */
u8 datain, /* data to send */
u8 *dataout)
{ /* data to receive back */
return DRX_STS_ERROR;
}
static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* address of register */
DRXaddr_t raddr, /* address to read back from */
static int drxdap_fasi_read_modify_write_reg32(struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* address of register */
dr_xaddr_t raddr, /* address to read back from */
u32 datain, /* data to send */
u32 *dataout)
{ /* data to receive back */
......@@ -187,12 +187,12 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /*
/******************************
*
* int DRXDAP_FASI_ReadBlock (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_read_block (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Read block data from chip address. Because the chip is word oriented,
* the number of bytes to read must be even.
......@@ -210,28 +210,28 @@ static int DRXDAP_FASI_ReadModifyWriteReg32(struct i2c_device_addr *devAddr, /*
*
******************************/
static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
static int drxdap_fasi_read_block(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u16 datasize,
u8 *data, DRXflags_t flags)
u8 *data, dr_xflags_t flags)
{
u8 buf[4];
u16 bufx;
int rc;
u16 overheadSize = 0;
u16 overhead_size = 0;
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
if (dev_addr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
(overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
......@@ -283,13 +283,13 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
* In single master mode, split the read and write actions.
* No special action is needed for write chunks here.
*/
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, 0, 0, 0);
rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, 0, 0, 0);
if (rc == DRX_STS_OK) {
rc = DRXBSP_I2C_WriteRead(0, 0, 0, devAddr, todo, data);
rc = drxbsp_i2c_write_read(0, 0, 0, dev_addr, todo, data);
}
#else
/* In multi master mode, do everything in one RW action */
rc = DRXBSP_I2C_WriteRead(devAddr, bufx, buf, devAddr, todo,
rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo,
data);
#endif
data += todo;
......@@ -302,10 +302,10 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
/******************************
*
* int DRXDAP_FASI_ReadModifyWriteReg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t waddr, -- address of chip register/memory
* DRXaddr_t raddr, -- chip address to read back from
* int drxdap_fasi_read_modify_write_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t waddr, -- address of chip register/memory
* dr_xaddr_t raddr, -- chip address to read back from
* u16 wdata, -- data to send
* u16 *rdata) -- data to receive back
*
......@@ -325,9 +325,9 @@ static int DRXDAP_FASI_ReadBlock(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
DRXaddr_t waddr,
DRXaddr_t raddr,
static int drxdap_fasi_read_modify_write_reg16(struct i2c_device_addr *dev_addr,
dr_xaddr_t waddr,
dr_xaddr_t raddr,
u16 wdata, u16 *rdata)
{
int rc = DRX_STS_ERROR;
......@@ -337,9 +337,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_WriteReg16(devAddr, waddr, wdata, DRXDAP_FASI_RMW);
rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW);
if (rc == DRX_STS_OK) {
rc = DRXDAP_FASI_ReadReg16(devAddr, raddr, rdata, 0);
rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0);
}
#endif
......@@ -348,11 +348,11 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
/******************************
*
* int DRXDAP_FASI_ReadReg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_read_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u16 *data, -- data to receive
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Read one 16-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
......@@ -364,9 +364,9 @@ static int DRXDAP_FASI_ReadModifyWriteReg16(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
u16 *data, DRXflags_t flags)
static int drxdap_fasi_read_reg16(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u16 *data, dr_xflags_t flags)
{
u8 buf[sizeof(*data)];
int rc;
......@@ -374,18 +374,18 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr,
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = buf[0] + (((u16) buf[1]) << 8);
return rc;
}
/******************************
*
* int DRXDAP_FASI_ReadReg32 (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_read_reg32 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u32 *data, -- data to receive
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Read one 32-bit register or memory location. The data received back is
* converted back to the target platform's endianness.
......@@ -397,9 +397,9 @@ static int DRXDAP_FASI_ReadReg16(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
u32 *data, DRXflags_t flags)
static int drxdap_fasi_read_reg32(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u32 *data, dr_xflags_t flags)
{
u8 buf[sizeof(*data)];
int rc;
......@@ -407,7 +407,7 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
if (!data) {
return DRX_STS_INVALID_ARG;
}
rc = DRXDAP_FASI_ReadBlock(devAddr, addr, sizeof(*data), buf, flags);
rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
*data = (((u32) buf[0]) << 0) +
(((u32) buf[1]) << 8) +
(((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
......@@ -416,12 +416,12 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
/******************************
*
* int DRXDAP_FASI_WriteBlock (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_write_block (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u16 datasize, -- number of bytes to read
* u8 *data, -- data to receive
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Write block data to chip address. Because the chip is word oriented,
* the number of bytes to write must be even.
......@@ -436,29 +436,29 @@ static int DRXDAP_FASI_ReadReg32(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
static int drxdap_fasi_write_block(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u16 datasize,
u8 *data, DRXflags_t flags)
u8 *data, dr_xflags_t flags)
{
u8 buf[DRXDAP_MAX_WCHUNKSIZE];
int st = DRX_STS_ERROR;
int firstErr = DRX_STS_OK;
u16 overheadSize = 0;
u16 blockSize = 0;
int first_err = DRX_STS_OK;
u16 overhead_size = 0;
u16 block_size = 0;
/* Check parameters ******************************************************* */
if (devAddr == NULL) {
if (dev_addr == NULL) {
return DRX_STS_INVALID_ARG;
}
overheadSize = (IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1) +
overhead_size = (IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1) +
(DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
DRXDAP_FASI_LONG_FORMAT(addr)) ||
(overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
(overhead_size > (DRXDAP_MAX_WCHUNKSIZE)) ||
((datasize != 0) && (data == NULL)) || ((datasize & 1) == 1)) {
return DRX_STS_INVALID_ARG;
}
......@@ -470,7 +470,7 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
#endif
/* Write block to I2C ***************************************************** */
blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
block_size = ((DRXDAP_MAX_WCHUNKSIZE) - overhead_size) & ~1;
do {
u16 todo = 0;
u16 bufx = 0;
......@@ -505,66 +505,66 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
#endif
/*
In single master mode blockSize can be 0. In such a case this I2C
In single master mode block_size can be 0. In such a case this I2C
sequense will be visible: (1) write address {i2c addr,
4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
(3) write address (4) write data etc...
Addres must be rewriten because HI is reset after data transport and
expects an address.
*/
todo = (blockSize < datasize ? blockSize : datasize);
todo = (block_size < datasize ? block_size : datasize);
if (todo == 0) {
u16 overheadSizeI2cAddr = 0;
u16 dataBlockSize = 0;
u16 overhead_sizeI2cAddr = 0;
u16 data_block_size = 0;
overheadSizeI2cAddr =
(IS_I2C_10BIT(devAddr->i2cAddr) ? 2 : 1);
dataBlockSize =
(DRXDAP_MAX_WCHUNKSIZE - overheadSizeI2cAddr) & ~1;
overhead_sizeI2cAddr =
(IS_I2C_10BIT(dev_addr->i2c_addr) ? 2 : 1);
data_block_size =
(DRXDAP_MAX_WCHUNKSIZE - overhead_sizeI2cAddr) & ~1;
/* write device address */
st = DRXBSP_I2C_WriteRead(devAddr,
st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx),
buf,
(struct i2c_device_addr *) (NULL),
0, (u8 *) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
first_err = st;
}
bufx = 0;
todo =
(dataBlockSize <
datasize ? dataBlockSize : datasize);
(data_block_size <
datasize ? data_block_size : datasize);
}
DRXBSP_HST_Memcpy(&buf[bufx], data, todo);
drxbsp_hst_memcpy(&buf[bufx], data, todo);
/* write (address if can do and) data */
st = DRXBSP_I2C_WriteRead(devAddr,
st = drxbsp_i2c_write_read(dev_addr,
(u16) (bufx + todo),
buf,
(struct i2c_device_addr *) (NULL),
0, (u8 *) (NULL));
if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
if ((st != DRX_STS_OK) && (first_err == DRX_STS_OK)) {
/* at the end, return the first error encountered */
firstErr = st;
first_err = st;
}
datasize -= todo;
data += todo;
addr += (todo >> 1);
} while (datasize);
return firstErr;
return first_err;
}
/******************************
*
* int DRXDAP_FASI_WriteReg16 (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_write_reg16 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u16 data, -- data to send
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Write one 16-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
......@@ -575,25 +575,25 @@ static int DRXDAP_FASI_WriteBlock(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
u16 data, DRXflags_t flags)
static int drxdap_fasi_write_reg16(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u16 data, dr_xflags_t flags)
{
u8 buf[sizeof(data)];
buf[0] = (u8) ((data >> 0) & 0xFF);
buf[1] = (u8) ((data >> 8) & 0xFF);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
}
/******************************
*
* int DRXDAP_FASI_WriteReg32 (
* struct i2c_device_addr *devAddr, -- address of I2C device
* DRXaddr_t addr, -- address of chip register/memory
* int drxdap_fasi_write_reg32 (
* struct i2c_device_addr *dev_addr, -- address of I2C device
* dr_xaddr_t addr, -- address of chip register/memory
* u32 data, -- data to send
* DRXflags_t flags) -- special device flags
* dr_xflags_t flags) -- special device flags
*
* Write one 32-bit register or memory location. The data being written is
* converted from the target platform's endianness to little endian.
......@@ -604,9 +604,9 @@ static int DRXDAP_FASI_WriteReg16(struct i2c_device_addr *devAddr,
*
******************************/
static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr,
DRXaddr_t addr,
u32 data, DRXflags_t flags)
static int drxdap_fasi_write_reg32(struct i2c_device_addr *dev_addr,
dr_xaddr_t addr,
u32 data, dr_xflags_t flags)
{
u8 buf[sizeof(data)];
......@@ -615,5 +615,5 @@ static int DRXDAP_FASI_WriteReg32(struct i2c_device_addr *devAddr,
buf[2] = (u8) ((data >> 16) & 0xFF);
buf[3] = (u8) ((data >> 24) & 0xFF);
return DRXDAP_FASI_WriteBlock(devAddr, addr, sizeof(data), buf, flags);
return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
}
drivers/media/dvb-frontends/drx39xyj/drx_dap_fasi.h
View file @ 57afe2f0
......@@ -238,7 +238,7 @@
extern "C" {
#endif
extern DRXAccessFunc_t drxDapFASIFunct_g;
extern drx_access_func_t drx_dap_fasi_funct_g;
#define DRXDAP_FASI_RMW 0x10000000
#define DRXDAP_FASI_BROADCAST 0x20000000
......
drivers/media/dvb-frontends/drx39xyj/drx_driver.c
View file @ 57afe2f0
......@@ -130,7 +130,7 @@ typedef struct {
- bit[15..2]=reserved */
u16 CRC;/**< CRC value of the data block, only valid if CRC flag is
set. */
} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t;
} drxu_code_block_hdr_t, *pdrxu_code_block_hdr_t;
/*------------------------------------------------------------------------------
FUNCTIONS
......@@ -146,57 +146,57 @@ FUNCTIONS
/* Prototype of default scanning function */
static int
ScanFunctionDefault(void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel, bool *getNextChannel);
scan_function_default(void *scan_context,
drx_scan_command_t scan_command,
pdrx_channel_t scan_channel, bool *get_next_channel);
/**
* \brief Get pointer to scanning function.
* \param demod: Pointer to demodulator instance.
* \return DRXScanFunc_t.
* \return drx_scan_func_t.
*/
static DRXScanFunc_t GetScanFunction(pDRXDemodInstance_t demod)
static drx_scan_func_t get_scan_function(pdrx_demod_instance_t demod)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
DRXScanFunc_t scanFunc = (DRXScanFunc_t) (NULL);
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
drx_scan_func_t scan_func = (drx_scan_func_t) (NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanFunc = commonAttr->scanFunction;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
scan_func = common_attr->scan_function;
if (scanFunc != NULL) {
if (scan_func != NULL) {
/* return device-specific scan function if it's not NULL */
return scanFunc;
return scan_func;
}
/* otherwise return default scan function in core driver */
return &ScanFunctionDefault;
return &scan_function_default;
}
/**
* \brief Get Context pointer.
* \param demod: Pointer to demodulator instance.
* \param scanContext: Context Pointer.
* \return DRXScanFunc_t.
* \param scan_context: Context Pointer.
* \return drx_scan_func_t.
*/
void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext)
void *get_scan_context(pdrx_demod_instance_t demod, void *scan_context)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
/* get scan function from common attributes */
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
scanContext = commonAttr->scanContext;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
scan_context = common_attr->scan_context;
if (scanContext == NULL) {
scanContext = (void *)demod;
if (scan_context == NULL) {
scan_context = (void *)demod;
}
return scanContext;
return scan_context;
}
/**
* \brief Wait for lock while scanning.
* \param demod: Pointer to demodulator instance.
* \param lockStat: Pointer to bool indicating if end result is lock or not.
* \param lock_stat: Pointer to bool indicating if end result is lock or not.
* \return int.
* \retval DRX_STS_OK: Success
* \retval DRX_STS_ERROR: I2C failure or bsp function failure.
......@@ -211,46 +211,46 @@ void *GetScanContext(pDRXDemodInstance_t demod, void *scanContext)
* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted.
*
*/
static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked)
static int scan_wait_for_lock(pdrx_demod_instance_t demod, bool *is_locked)
{
bool doneWaiting = false;
DRXLockStatus_t lockState = DRX_NOT_LOCKED;
DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED;
u32 timeoutValue = 0;
u32 startTimeLockStage = 0;
u32 currentTime = 0;
u32 timerValue = 0;
*isLocked = false;
timeoutValue = (u32) demod->myCommonAttr->scanDemodLockTimeout;
desiredLockState = demod->myCommonAttr->scanDesiredLock;
startTimeLockStage = DRXBSP_HST_Clock();
bool done_waiting = false;
drx_lock_status_t lock_state = DRX_NOT_LOCKED;
drx_lock_status_t desired_lock_state = DRX_NOT_LOCKED;
u32 timeout_value = 0;
u32 start_time_lock_stage = 0;
u32 current_time = 0;
u32 timer_value = 0;
*is_locked = false;
timeout_value = (u32) demod->my_common_attr->scan_demod_lock_timeout;
desired_lock_state = demod->my_common_attr->scan_desired_lock;
start_time_lock_stage = drxbsp_hst_clock();
/* Start polling loop, checking for lock & timeout */
while (doneWaiting == false) {
while (done_waiting == false) {
if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) !=
if (drx_ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_state) !=
DRX_STS_OK) {
return DRX_STS_ERROR;
}
currentTime = DRXBSP_HST_Clock();
timerValue = currentTime - startTimeLockStage;
if (lockState >= desiredLockState) {
*isLocked = true;
doneWaiting = true;
} /* if ( lockState >= desiredLockState ) .. */
else if (lockState == DRX_NEVER_LOCK) {
doneWaiting = true;
} /* if ( lockState == DRX_NEVER_LOCK ) .. */
else if (timerValue > timeoutValue) {
/* lockState == DRX_NOT_LOCKED and timeout */
doneWaiting = true;
current_time = drxbsp_hst_clock();
timer_value = current_time - start_time_lock_stage;
if (lock_state >= desired_lock_state) {
*is_locked = true;
done_waiting = true;
} /* if ( lock_state >= desired_lock_state ) .. */
else if (lock_state == DRX_NEVER_LOCK) {
done_waiting = true;
} /* if ( lock_state == DRX_NEVER_LOCK ) .. */
else if (timer_value > timeout_value) {
/* lock_state == DRX_NOT_LOCKED and timeout */
done_waiting = true;
} else {
if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) {
if (drxbsp_hst_sleep(10) != DRX_STS_OK) {
return DRX_STS_ERROR;
}
} /* if ( timerValue > timeoutValue ) .. */
} /* if ( timer_value > timeout_value ) .. */
} /* while */
......@@ -267,70 +267,70 @@ static int ScanWaitForLock(pDRXDemodInstance_t demod, bool *isLocked)
* \retval DRX_STS_OK: Succes.
* \retval DRX_STS_INVALID_ARG: Invalid frequency plan.
*
* Helper function for CtrlScanNext() function.
* Helper function for ctrl_scan_next() function.
* Compute next frequency & index in frequency plan.
* Check if scan is ready.
*
*/
static int
ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip)
scan_prepare_next_scan(pdrx_demod_instance_t demod, s32 skip)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
u16 tableIndex = 0;
u16 frequencyPlanSize = 0;
pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t) (NULL);
s32 nextFrequency = 0;
s32 tunerMinFrequency = 0;
s32 tunerMaxFrequency = 0;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
tableIndex = commonAttr->scanFreqPlanIndex;
frequencyPlan = commonAttr->scanParam->frequencyPlan;
nextFrequency = commonAttr->scanNextFrequency;
tunerMinFrequency = commonAttr->tunerMinFreqRF;
tunerMaxFrequency = commonAttr->tunerMaxFreqRF;
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
u16 table_index = 0;
u16 frequency_plan_size = 0;
p_drx_frequency_plan_t frequency_plan = (p_drx_frequency_plan_t) (NULL);
s32 next_frequency = 0;
s32 tuner_min_frequency = 0;
s32 tuner_max_frequency = 0;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
table_index = common_attr->scan_freq_plan_index;
frequency_plan = common_attr->scan_param->frequency_plan;
next_frequency = common_attr->scan_next_frequency;
tuner_min_frequency = common_attr->tuner_min_freq_rf;
tuner_max_frequency = common_attr->tuner_max_freq_rf;
do {
/* Search next frequency to scan */
/* always take at least one step */
(commonAttr->scanChannelsScanned)++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
(common_attr->scan_channelsScanned)++;
next_frequency += frequency_plan[table_index].step;
skip -= frequency_plan[table_index].step;
/* and then as many steps necessary to exceed 'skip'
without exceeding end of the band */
while ((skip > 0) &&
(nextFrequency <= frequencyPlan[tableIndex].last)) {
(commonAttr->scanChannelsScanned)++;
nextFrequency += frequencyPlan[tableIndex].step;
skip -= frequencyPlan[tableIndex].step;
(next_frequency <= frequency_plan[table_index].last)) {
(common_attr->scan_channelsScanned)++;
next_frequency += frequency_plan[table_index].step;
skip -= frequency_plan[table_index].step;
}
/* reset skip, in case we move to the next band later */
skip = 0;
if (nextFrequency > frequencyPlan[tableIndex].last) {
if (next_frequency > frequency_plan[table_index].last) {
/* reached end of this band */
tableIndex++;
frequencyPlanSize =
commonAttr->scanParam->frequencyPlanSize;
if (tableIndex >= frequencyPlanSize) {
table_index++;
frequency_plan_size =
common_attr->scan_param->frequency_plan_size;
if (table_index >= frequency_plan_size) {
/* reached end of frequency plan */
commonAttr->scanReady = true;
common_attr->scan_ready = true;
} else {
nextFrequency = frequencyPlan[tableIndex].first;
next_frequency = frequency_plan[table_index].first;
}
}
if (nextFrequency > (tunerMaxFrequency)) {
if (next_frequency > (tuner_max_frequency)) {
/* reached end of tuner range */
commonAttr->scanReady = true;
common_attr->scan_ready = true;
}
} while ((nextFrequency < tunerMinFrequency) &&
(commonAttr->scanReady == false));
} while ((next_frequency < tuner_min_frequency) &&
(common_attr->scan_ready == false));
/* Store new values */
commonAttr->scanFreqPlanIndex = tableIndex;
commonAttr->scanNextFrequency = nextFrequency;
common_attr->scan_freq_plan_index = table_index;
common_attr->scan_next_frequency = next_frequency;
return DRX_STS_OK;
}
......@@ -341,9 +341,9 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip)
* \brief Default DTV scanning function.
*
* \param demod: Pointer to demodulator instance.
* \param scanCommand: Scanning command: INIT, NEXT or STOP.
* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO
* \param getNextChannel: Return true if next frequency is desired at next call
* \param scan_command: Scanning command: INIT, NEXT or STOP.
* \param scan_channel: Channel to check: frequency and bandwidth, others AUTO
* \param get_next_channel: Return true if next frequency is desired at next call
*
* \return int.
* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
......@@ -351,40 +351,40 @@ ScanPrepareNextScan(pDRXDemodInstance_t demod, s32 skip)
* \retval DRX_STS_BUSY: Channel not found (yet).
* \retval DRX_STS_ERROR: Something went wrong.
*
* scanChannel and getNextChannel will be NULL for INIT and STOP.
* scan_channel and get_next_channel will be NULL for INIT and STOP.
*/
static int
ScanFunctionDefault(void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel, bool *getNextChannel)
scan_function_default(void *scan_context,
drx_scan_command_t scan_command,
pdrx_channel_t scan_channel, bool *get_next_channel)
{
pDRXDemodInstance_t demod = NULL;
pdrx_demod_instance_t demod = NULL;
int status = DRX_STS_ERROR;
bool isLocked = false;
bool is_locked = false;
demod = (pDRXDemodInstance_t) scanContext;
demod = (pdrx_demod_instance_t) scan_context;
if (scanCommand != DRX_SCAN_COMMAND_NEXT) {
if (scan_command != DRX_SCAN_COMMAND_NEXT) {
/* just return OK if not doing "scan next" */
return DRX_STS_OK;
}
*getNextChannel = false;
*get_next_channel = false;
status = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, scanChannel);
status = drx_ctrl(demod, DRX_CTRL_SET_CHANNEL, scan_channel);
if (status != DRX_STS_OK) {
return (status);
}
status = ScanWaitForLock(demod, &isLocked);
status = scan_wait_for_lock(demod, &is_locked);
if (status != DRX_STS_OK) {
return status;
}
/* done with this channel, move to next one */
*getNextChannel = true;
*get_next_channel = true;
if (isLocked == false) {
if (is_locked == false) {
/* no channel found */
return DRX_STS_BUSY;
}
......@@ -397,7 +397,7 @@ ScanFunctionDefault(void *scanContext,
/**
* \brief Initialize for channel scan.
* \param demod: Pointer to demodulator instance.
* \param scanParam: Pointer to scan parameters.
* \param scan_param: Pointer to scan parameters.
* \return int.
* \retval DRX_STS_OK: Initialized for scan.
* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner
......@@ -412,131 +412,131 @@ ScanFunctionDefault(void *scanContext,
*
*/
static int
CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam)
ctrl_scan_init(pdrx_demod_instance_t demod, p_drx_scan_param_t scan_param)
{
int status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
s32 maxTunerFreq = 0;
s32 minTunerFreq = 0;
u16 nrChannelsInPlan = 0;
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
s32 max_tuner_freq = 0;
s32 min_tuner_freq = 0;
u16 nr_channels_in_plan = 0;
u16 i = 0;
void *scanContext = NULL;
void *scan_context = NULL;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
commonAttr->scanActive = true;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
common_attr->scan_active = true;
/* invalidate a previous SCAN_INIT */
commonAttr->scanParam = (pDRXScanParam_t) (NULL);
commonAttr->scanNextFrequency = 0;
common_attr->scan_param = (p_drx_scan_param_t) (NULL);
common_attr->scan_next_frequency = 0;
/* Check parameters */
if (((demod->myTuner == NULL) &&
(scanParam->numTries != 1)) ||
(scanParam == NULL) ||
(scanParam->numTries == 0) ||
(scanParam->frequencyPlan == NULL) ||
(scanParam->frequencyPlanSize == 0)
if (((demod->my_tuner == NULL) &&
(scan_param->num_tries != 1)) ||
(scan_param == NULL) ||
(scan_param->num_tries == 0) ||
(scan_param->frequency_plan == NULL) ||
(scan_param->frequency_plan_size == 0)
) {
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_INVALID_ARG;
}
/* Check frequency plan contents */
maxTunerFreq = commonAttr->tunerMaxFreqRF;
minTunerFreq = commonAttr->tunerMinFreqRF;
for (i = 0; i < (scanParam->frequencyPlanSize); i++) {
max_tuner_freq = common_attr->tuner_max_freq_rf;
min_tuner_freq = common_attr->tuner_min_freq_rf;
for (i = 0; i < (scan_param->frequency_plan_size); i++) {
s32 width = 0;
s32 step = scanParam->frequencyPlan[i].step;
s32 firstFreq = scanParam->frequencyPlan[i].first;
s32 lastFreq = scanParam->frequencyPlan[i].last;
s32 minFreq = 0;
s32 maxFreq = 0;
s32 step = scan_param->frequency_plan[i].step;
s32 first_freq = scan_param->frequency_plan[i].first;
s32 last_freq = scan_param->frequency_plan[i].last;
s32 min_freq = 0;
s32 max_freq = 0;
if (step <= 0) {
/* Step must be positive and non-zero */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_INVALID_ARG;
}
if (firstFreq > lastFreq) {
if (first_freq > last_freq) {
/* First center frequency is higher than last center frequency */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_INVALID_ARG;
}
width = lastFreq - firstFreq;
width = last_freq - first_freq;
if ((width % step) != 0) {
/* Difference between last and first center frequency is not
an integer number of steps */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_INVALID_ARG;
}
/* Check if frequency plan entry intersects with tuner range */
if (lastFreq >= minTunerFreq) {
if (firstFreq <= maxTunerFreq) {
if (firstFreq >= minTunerFreq) {
minFreq = firstFreq;
if (last_freq >= min_tuner_freq) {
if (first_freq <= max_tuner_freq) {
if (first_freq >= min_tuner_freq) {
min_freq = first_freq;
} else {
s32 n = 0;
n = (minTunerFreq - firstFreq) / step;
if (((minTunerFreq -
firstFreq) % step) != 0) {
n = (min_tuner_freq - first_freq) / step;
if (((min_tuner_freq -
first_freq) % step) != 0) {
n++;
}
minFreq = firstFreq + n * step;
min_freq = first_freq + n * step;
}
if (lastFreq <= maxTunerFreq) {
maxFreq = lastFreq;
if (last_freq <= max_tuner_freq) {
max_freq = last_freq;
} else {
s32 n = 0;
n = (lastFreq - maxTunerFreq) / step;
if (((lastFreq -
maxTunerFreq) % step) != 0) {
n = (last_freq - max_tuner_freq) / step;
if (((last_freq -
max_tuner_freq) % step) != 0) {
n++;
}
maxFreq = lastFreq - n * step;
max_freq = last_freq - n * step;
}
}
}
/* Keep track of total number of channels within tuner range
in this frequency plan. */
if ((minFreq != 0) && (maxFreq != 0)) {
nrChannelsInPlan +=
(u16) (((maxFreq - minFreq) / step) + 1);
if ((min_freq != 0) && (max_freq != 0)) {
nr_channels_in_plan +=
(u16) (((max_freq - min_freq) / step) + 1);
/* Determine first frequency (within tuner range) to scan */
if (commonAttr->scanNextFrequency == 0) {
commonAttr->scanNextFrequency = minFreq;
commonAttr->scanFreqPlanIndex = i;
if (common_attr->scan_next_frequency == 0) {
common_attr->scan_next_frequency = min_freq;
common_attr->scan_freq_plan_index = i;
}
}
} /* for ( ... ) */
if (nrChannelsInPlan == 0) {
if (nr_channels_in_plan == 0) {
/* Tuner range and frequency plan ranges do not overlap */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_ERROR;
}
/* Store parameters */
commonAttr->scanReady = false;
commonAttr->scanMaxChannels = nrChannelsInPlan;
commonAttr->scanChannelsScanned = 0;
commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */
common_attr->scan_ready = false;
common_attr->scan_max_channels = nr_channels_in_plan;
common_attr->scan_channelsScanned = 0;
common_attr->scan_param = scan_param; /* SCAN_NEXT is now allowed */
scanContext = GetScanContext(demod, scanContext);
scan_context = get_scan_context(demod, scan_context);
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL);
status = (*(get_scan_function(demod)))
(scan_context, DRX_SCAN_COMMAND_INIT, NULL, NULL);
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_OK;
}
......@@ -551,32 +551,32 @@ CtrlScanInit(pDRXDemodInstance_t demod, pDRXScanParam_t scanParam)
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*/
static int CtrlScanStop(pDRXDemodInstance_t demod)
static int ctrl_scan_stop(pdrx_demod_instance_t demod)
{
int status = DRX_STS_ERROR;
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
void *scanContext = NULL;
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
void *scan_context = NULL;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
commonAttr->scanActive = true;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
common_attr->scan_active = true;
if ((commonAttr->scanParam == NULL) ||
(commonAttr->scanMaxChannels == 0)) {
if ((common_attr->scan_param == NULL) ||
(common_attr->scan_max_channels == 0)) {
/* Scan was not running, just return OK */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_OK;
}
/* Call default or device-specific scanning stop function */
scanContext = GetScanContext(demod, scanContext);
scan_context = get_scan_context(demod, scan_context);
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL);
status = (*(get_scan_function(demod)))
(scan_context, DRX_SCAN_COMMAND_STOP, NULL, NULL);
/* All done, invalidate scan-init */
commonAttr->scanParam = NULL;
commonAttr->scanMaxChannels = 0;
commonAttr->scanActive = false;
common_attr->scan_param = NULL;
common_attr->scan_max_channels = 0;
common_attr->scan_active = false;
return status;
}
......@@ -586,126 +586,126 @@ static int CtrlScanStop(pDRXDemodInstance_t demod)
/**
* \brief Scan for next channel.
* \param demod: Pointer to demodulator instance.
* \param scanProgress: Pointer to scan progress.
* \param scan_progress: Pointer to scan progress.
* \return int.
* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
* to retrieve channel parameters.
* \retval DRX_STS_BUSY: Tried part of the channels, as specified in
* numTries field of scan parameters. At least one
* num_tries field of scan parameters. At least one
* more call to DRX_CTRL_SCAN_NEXT is needed to
* complete scanning.
* \retval DRX_STS_READY: Reached end of scan range.
* \retval DRX_STS_ERROR: Something went wrong.
* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL.
* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scan_progress may be NULL.
*
* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
*
*/
static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress)
static int ctrl_scan_next(pdrx_demod_instance_t demod, u16 *scan_progress)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
bool *scanReady = (bool *) (NULL);
u16 maxProgress = DRX_SCAN_MAX_PROGRESS;
u32 numTries = 0;
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
bool *scan_ready = (bool *) (NULL);
u16 max_progress = DRX_SCAN_MAX_PROGRESS;
u32 num_tries = 0;
u32 i = 0;
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
/* Check scan parameters */
if (scanProgress == NULL) {
commonAttr->scanActive = false;
if (scan_progress == NULL) {
common_attr->scan_active = false;
return DRX_STS_INVALID_ARG;
}
*scanProgress = 0;
commonAttr->scanActive = true;
if ((commonAttr->scanParam == NULL) ||
(commonAttr->scanMaxChannels == 0)) {
/* CtrlScanInit() was not called succesfully before CtrlScanNext() */
commonAttr->scanActive = false;
*scan_progress = 0;
common_attr->scan_active = true;
if ((common_attr->scan_param == NULL) ||
(common_attr->scan_max_channels == 0)) {
/* ctrl_scan_init() was not called succesfully before ctrl_scan_next() */
common_attr->scan_active = false;
return DRX_STS_ERROR;
}
*scanProgress = (u16) (((commonAttr->scanChannelsScanned) *
((u32) (maxProgress))) /
(commonAttr->scanMaxChannels));
*scan_progress = (u16) (((common_attr->scan_channelsScanned) *
((u32) (max_progress))) /
(common_attr->scan_max_channels));
/* Scan */
numTries = commonAttr->scanParam->numTries;
scanReady = &(commonAttr->scanReady);
num_tries = common_attr->scan_param->num_tries;
scan_ready = &(common_attr->scan_ready);
for (i = 0; ((i < numTries) && ((*scanReady) == false)); i++) {
DRXChannel_t scanChannel = { 0 };
for (i = 0; ((i < num_tries) && ((*scan_ready) == false)); i++) {
drx_channel_t scan_channel = { 0 };
int status = DRX_STS_ERROR;
pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL);
bool nextChannel = false;
void *scanContext = NULL;
p_drx_frequency_plan_t freq_plan = (p_drx_frequency_plan_t) (NULL);
bool next_channel = false;
void *scan_context = NULL;
/* Next channel to scan */
freqPlan =
&(commonAttr->scanParam->
frequencyPlan[commonAttr->scanFreqPlanIndex]);
scanChannel.frequency = commonAttr->scanNextFrequency;
scanChannel.bandwidth = freqPlan->bandwidth;
scanChannel.mirror = DRX_MIRROR_AUTO;
scanChannel.constellation = DRX_CONSTELLATION_AUTO;
scanChannel.hierarchy = DRX_HIERARCHY_AUTO;
scanChannel.priority = DRX_PRIORITY_HIGH;
scanChannel.coderate = DRX_CODERATE_AUTO;
scanChannel.guard = DRX_GUARD_AUTO;
scanChannel.fftmode = DRX_FFTMODE_AUTO;
scanChannel.classification = DRX_CLASSIFICATION_AUTO;
scanChannel.symbolrate = 0;
scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
scanChannel.ldpc = DRX_LDPC_AUTO;
scanChannel.carrier = DRX_CARRIER_AUTO;
scanChannel.framemode = DRX_FRAMEMODE_AUTO;
scanChannel.pilot = DRX_PILOT_AUTO;
freq_plan =
&(common_attr->scan_param->
frequency_plan[common_attr->scan_freq_plan_index]);
scan_channel.frequency = common_attr->scan_next_frequency;
scan_channel.bandwidth = freq_plan->bandwidth;
scan_channel.mirror = DRX_MIRROR_AUTO;
scan_channel.constellation = DRX_CONSTELLATION_AUTO;
scan_channel.hierarchy = DRX_HIERARCHY_AUTO;
scan_channel.priority = DRX_PRIORITY_HIGH;
scan_channel.coderate = DRX_CODERATE_AUTO;
scan_channel.guard = DRX_GUARD_AUTO;
scan_channel.fftmode = DRX_FFTMODE_AUTO;
scan_channel.classification = DRX_CLASSIFICATION_AUTO;
scan_channel.symbolrate = 0;
scan_channel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
scan_channel.ldpc = DRX_LDPC_AUTO;
scan_channel.carrier = DRX_CARRIER_AUTO;
scan_channel.framemode = DRX_FRAMEMODE_AUTO;
scan_channel.pilot = DRX_PILOT_AUTO;
/* Call default or device-specific scanning function */
scanContext = GetScanContext(demod, scanContext);
scan_context = get_scan_context(demod, scan_context);
status = (*(GetScanFunction(demod)))
(scanContext, DRX_SCAN_COMMAND_NEXT, &scanChannel,
&nextChannel);
status = (*(get_scan_function(demod)))
(scan_context, DRX_SCAN_COMMAND_NEXT, &scan_channel,
&next_channel);
/* Proceed to next channel if requested */
if (nextChannel == true) {
int nextStatus = DRX_STS_ERROR;
if (next_channel == true) {
int next_status = DRX_STS_ERROR;
s32 skip = 0;
if (status == DRX_STS_OK) {
/* a channel was found, so skip some frequency steps */
skip = commonAttr->scanParam->skip;
skip = common_attr->scan_param->skip;
}
nextStatus = ScanPrepareNextScan(demod, skip);
next_status = scan_prepare_next_scan(demod, skip);
/* keep track of progress */
*scanProgress =
(u16) (((commonAttr->scanChannelsScanned) *
((u32) (maxProgress))) /
(commonAttr->scanMaxChannels));
if (nextStatus != DRX_STS_OK) {
commonAttr->scanActive = false;
return (nextStatus);
*scan_progress =
(u16) (((common_attr->scan_channelsScanned) *
((u32) (max_progress))) /
(common_attr->scan_max_channels));
if (next_status != DRX_STS_OK) {
common_attr->scan_active = false;
return (next_status);
}
}
if (status != DRX_STS_BUSY) {
/* channel found or error */
commonAttr->scanActive = false;
common_attr->scan_active = false;
return status;
}
} /* for ( i = 0; i < ( ... numTries); i++) */
} /* for ( i = 0; i < ( ... num_tries); i++) */
if ((*scanReady) == true) {
if ((*scan_ready) == true) {
/* End of scan reached: call stop-scan, ignore any error */
CtrlScanStop(demod);
commonAttr->scanActive = false;
ctrl_scan_stop(demod);
common_attr->scan_active = false;
return (DRX_STS_READY);
}
commonAttr->scanActive = false;
common_attr->scan_active = false;
return DRX_STS_BUSY;
}
......@@ -728,101 +728,101 @@ static int CtrlScanNext(pDRXDemodInstance_t demod, u16 *scanProgress)
*
*/
static int
CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel)
ctrl_program_tuner(pdrx_demod_instance_t demod, pdrx_channel_t channel)
{
pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
pdrx_common_attr_t common_attr = (pdrx_common_attr_t) (NULL);
enum drx_standard standard = DRX_STANDARD_UNKNOWN;
u32 tunerMode = 0;
u32 tuner_mode = 0;
int status = DRX_STS_ERROR;
s32 ifFrequency = 0;
bool tunerSlowMode = false;
s32 if_frequency = 0;
bool tuner_slow_mode = false;
/* can't tune without a tuner */
if (demod->myTuner == NULL) {
if (demod->my_tuner == NULL) {
return DRX_STS_INVALID_ARG;
}
commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
common_attr = (pdrx_common_attr_t) demod->my_common_attr;
/* select analog or digital tuner mode based on current standard */
if (DRX_Ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) {
if (drx_ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) {
return DRX_STS_ERROR;
}
if (DRX_ISATVSTD(standard)) {
tunerMode |= TUNER_MODE_ANALOG;
tuner_mode |= TUNER_MODE_ANALOG;
} else { /* note: also for unknown standard */
tunerMode |= TUNER_MODE_DIGITAL;
tuner_mode |= TUNER_MODE_DIGITAL;
}
/* select tuner bandwidth */
switch (channel->bandwidth) {
case DRX_BANDWIDTH_6MHZ:
tunerMode |= TUNER_MODE_6MHZ;
tuner_mode |= TUNER_MODE_6MHZ;
break;
case DRX_BANDWIDTH_7MHZ:
tunerMode |= TUNER_MODE_7MHZ;
tuner_mode |= TUNER_MODE_7MHZ;
break;
case DRX_BANDWIDTH_8MHZ:
tunerMode |= TUNER_MODE_8MHZ;
tuner_mode |= TUNER_MODE_8MHZ;
break;
default: /* note: also for unknown bandwidth */
return DRX_STS_INVALID_ARG;
}
DRX_GET_TUNERSLOWMODE(demod, tunerSlowMode);
DRX_GET_TUNERSLOWMODE(demod, tuner_slow_mode);
/* select fast (switch) or slow (lock) tuner mode */
if (tunerSlowMode) {
tunerMode |= TUNER_MODE_LOCK;
if (tuner_slow_mode) {
tuner_mode |= TUNER_MODE_LOCK;
} else {
tunerMode |= TUNER_MODE_SWITCH;
tuner_mode |= TUNER_MODE_SWITCH;
}
if (commonAttr->tunerPortNr == 1) {
bool bridgeClosed = true;
int statusBridge = DRX_STS_ERROR;
if (common_attr->tuner_port_nr == 1) {
bool bridge_closed = true;
int status_bridge = DRX_STS_ERROR;
statusBridge =
DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
if (statusBridge != DRX_STS_OK) {
return statusBridge;
status_bridge =
drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed);
if (status_bridge != DRX_STS_OK) {
return status_bridge;
}
}
status = DRXBSP_TUNER_SetFrequency(demod->myTuner,
tunerMode, channel->frequency);
status = drxbsp_tuner_set_frequency(demod->my_tuner,
tuner_mode, channel->frequency);
/* attempt restoring bridge before checking status of SetFrequency */
if (commonAttr->tunerPortNr == 1) {
bool bridgeClosed = false;
int statusBridge = DRX_STS_ERROR;
/* attempt restoring bridge before checking status of set_frequency */
if (common_attr->tuner_port_nr == 1) {
bool bridge_closed = false;
int status_bridge = DRX_STS_ERROR;
statusBridge =
DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
if (statusBridge != DRX_STS_OK) {
return statusBridge;
status_bridge =
drx_ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridge_closed);
if (status_bridge != DRX_STS_OK) {
return status_bridge;
}
}
/* now check status of DRXBSP_TUNER_SetFrequency */
/* now check status of drxbsp_tuner_set_frequency */
if (status != DRX_STS_OK) {
return status;
}
/* get actual RF and IF frequencies from tuner */
status = DRXBSP_TUNER_GetFrequency(demod->myTuner,
tunerMode,
status = drxbsp_tuner_get_frequency(demod->my_tuner,
tuner_mode,
&(channel->frequency),
&(ifFrequency));
&(if_frequency));
if (status != DRX_STS_OK) {
return status;
}
/* update common attributes with information available from this function;
TODO: check if this is required and safe */
DRX_SET_INTERMEDIATEFREQ(demod, ifFrequency);
DRX_SET_INTERMEDIATEFREQ(demod, if_frequency);
return DRX_STS_OK;
}
......@@ -839,8 +839,8 @@ CtrlProgramTuner(pDRXDemodInstance_t demod, pDRXChannel_t channel)
* \retval DRX_STS_INVALID_ARG: Wrong parameters.
*
*/
int CtrlDumpRegisters(pDRXDemodInstance_t demod,
pDRXRegDump_t registers)
int ctrl_dump_registers(pdrx_demod_instance_t demod,
p_drx_reg_dump_t registers)
{
u16 i = 0;
......@@ -856,7 +856,7 @@ int CtrlDumpRegisters(pDRXDemodInstance_t demod,
u32 data = 0;
status =
demod->myAccessFunct->readReg16Func(demod->myI2CDevAddr,
demod->my_access_funct->read_reg16func(demod->my_i2c_dev_addr,
registers[i].address,
&value, 0);
......@@ -890,7 +890,7 @@ int CtrlDumpRegisters(pDRXDemodInstance_t demod,
* host and the data contained in the microcode image file.
*
*/
static u16 UCodeRead16(u8 *addr)
static u16 u_code_read16(u8 *addr)
{
/* Works fo any host processor */
......@@ -914,7 +914,7 @@ static u16 UCodeRead16(u8 *addr)
* host and the data contained in the microcode image file.
*
*/
static u32 UCodeRead32(u8 *addr)
static u32 u_code_read32(u8 *addr)
{
/* Works fo any host processor */
......@@ -935,38 +935,38 @@ static u32 UCodeRead32(u8 *addr)
/**
* \brief Compute CRC of block of microcode data.
* \param blockData: Pointer to microcode data.
* \param nrWords: Size of microcode block (number of 16 bits words).
* \param block_data: Pointer to microcode data.
* \param nr_words: Size of microcode block (number of 16 bits words).
* \return u16 The computed CRC residu.
*/
static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords)
static u16 u_code_compute_crc(u8 *block_data, u16 nr_words)
{
u16 i = 0;
u16 j = 0;
u32 CRCWord = 0;
u32 crc_word = 0;
u32 carry = 0;
while (i < nrWords) {
CRCWord |= (u32) UCodeRead16(blockData);
while (i < nr_words) {
crc_word |= (u32) u_code_read16(block_data);
for (j = 0; j < 16; j++) {
CRCWord <<= 1;
crc_word <<= 1;
if (carry != 0) {
CRCWord ^= 0x80050000UL;
crc_word ^= 0x80050000UL;
}
carry = CRCWord & 0x80000000UL;
carry = crc_word & 0x80000000UL;
}
i++;
blockData += (sizeof(u16));
block_data += (sizeof(u16));
}
return ((u16) (CRCWord >> 16));
return ((u16) (crc_word >> 16));
}
/*============================================================================*/
/**
* \brief Handle microcode upload or verify.
* \param devAddr: Address of device.
* \param mcInfo: Pointer to information about microcode data.
* \param dev_addr: Address of device.
* \param mc_info: Pointer to information about microcode data.
* \param action: Either UCODE_UPLOAD or UCODE_VERIFY
* \return int.
* \retval DRX_STS_OK:
......@@ -982,32 +982,32 @@ static u16 UCodeComputeCRC(u8 *blockData, u16 nrWords)
* - Provided image is corrupt
*/
static int
CtrlUCode(pDRXDemodInstance_t demod,
pDRXUCodeInfo_t mcInfo, DRXUCodeAction_t action)
ctrl_u_code(pdrx_demod_instance_t demod,
p_drxu_code_info_t mc_info, drxu_code_action_t action)
{
int rc;
u16 i = 0;
u16 mcNrOfBlks = 0;
u16 mcMagicWord = 0;
u8 *mcData = (u8 *) (NULL);
struct i2c_device_addr *devAddr = (struct i2c_device_addr *) (NULL);
u16 mc_nr_of_blks = 0;
u16 mc_magic_word = 0;
u8 *mc_data = (u8 *) (NULL);
struct i2c_device_addr *dev_addr = (struct i2c_device_addr *) (NULL);
devAddr = demod->myI2CDevAddr;
dev_addr = demod->my_i2c_dev_addr;
/* Check arguments */
if ((mcInfo == NULL) || (mcInfo->mcData == NULL)) {
if ((mc_info == NULL) || (mc_info->mc_data == NULL)) {
return DRX_STS_INVALID_ARG;
}
mcData = mcInfo->mcData;
mc_data = mc_info->mc_data;
/* Check data */
mcMagicWord = UCodeRead16(mcData);
mcData += sizeof(u16);
mcNrOfBlks = UCodeRead16(mcData);
mcData += sizeof(u16);
mc_magic_word = u_code_read16(mc_data);
mc_data += sizeof(u16);
mc_nr_of_blks = u_code_read16(mc_data);
mc_data += sizeof(u16);
if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) || (mcNrOfBlks == 0)) {
if ((mc_magic_word != DRX_UCODE_MAGIC_WORD) || (mc_nr_of_blks == 0)) {
/* wrong endianess or wrong data ? */
return DRX_STS_INVALID_ARG;
}
......@@ -1019,95 +1019,95 @@ CtrlUCode(pDRXDemodInstance_t demod,
DRX_SET_MCDEV(demod, 0);
DRX_SET_MCVERSION(demod, 0);
DRX_SET_MCPATCH(demod, 0);
for (i = 0; i < mcNrOfBlks; i++) {
DRXUCodeBlockHdr_t blockHdr;
for (i = 0; i < mc_nr_of_blks; i++) {
drxu_code_block_hdr_t block_hdr;
/* Process block header */
blockHdr.addr = UCodeRead32(mcData);
mcData += sizeof(u32);
blockHdr.size = UCodeRead16(mcData);
mcData += sizeof(u16);
blockHdr.flags = UCodeRead16(mcData);
mcData += sizeof(u16);
blockHdr.CRC = UCodeRead16(mcData);
mcData += sizeof(u16);
if (blockHdr.flags & 0x8) {
block_hdr.addr = u_code_read32(mc_data);
mc_data += sizeof(u32);
block_hdr.size = u_code_read16(mc_data);
mc_data += sizeof(u16);
block_hdr.flags = u_code_read16(mc_data);
mc_data += sizeof(u16);
block_hdr.CRC = u_code_read16(mc_data);
mc_data += sizeof(u16);
if (block_hdr.flags & 0x8) {
/* Aux block. Check type */
u8 *auxblk = mcInfo->mcData + blockHdr.addr;
u16 auxtype = UCodeRead16(auxblk);
u8 *auxblk = mc_info->mc_data + block_hdr.addr;
u16 auxtype = u_code_read16(auxblk);
if (DRX_ISMCVERTYPE(auxtype)) {
DRX_SET_MCVERTYPE(demod,
UCodeRead16(auxblk));
u_code_read16(auxblk));
auxblk += sizeof(u16);
DRX_SET_MCDEV(demod,
UCodeRead32(auxblk));
u_code_read32(auxblk));
auxblk += sizeof(u32);
DRX_SET_MCVERSION(demod,
UCodeRead32(auxblk));
u_code_read32(auxblk));
auxblk += sizeof(u32);
DRX_SET_MCPATCH(demod,
UCodeRead32(auxblk));
u_code_read32(auxblk));
}
}
/* Next block */
mcData += blockHdr.size * sizeof(u16);
mc_data += block_hdr.size * sizeof(u16);
}
/* After scanning, validate the microcode.
It is also valid if no validation control exists.
*/
rc = DRX_Ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL);
rc = drx_ctrl(demod, DRX_CTRL_VALIDATE_UCODE, NULL);
if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) {
return rc;
}
/* Restore data pointer */
mcData = mcInfo->mcData + 2 * sizeof(u16);
mc_data = mc_info->mc_data + 2 * sizeof(u16);
}
/* Process microcode blocks */
for (i = 0; i < mcNrOfBlks; i++) {
DRXUCodeBlockHdr_t blockHdr;
u16 mcBlockNrBytes = 0;
for (i = 0; i < mc_nr_of_blks; i++) {
drxu_code_block_hdr_t block_hdr;
u16 mc_block_nr_bytes = 0;
/* Process block header */
blockHdr.addr = UCodeRead32(mcData);
mcData += sizeof(u32);
blockHdr.size = UCodeRead16(mcData);
mcData += sizeof(u16);
blockHdr.flags = UCodeRead16(mcData);
mcData += sizeof(u16);
blockHdr.CRC = UCodeRead16(mcData);
mcData += sizeof(u16);
block_hdr.addr = u_code_read32(mc_data);
mc_data += sizeof(u32);
block_hdr.size = u_code_read16(mc_data);
mc_data += sizeof(u16);
block_hdr.flags = u_code_read16(mc_data);
mc_data += sizeof(u16);
block_hdr.CRC = u_code_read16(mc_data);
mc_data += sizeof(u16);
/* Check block header on:
- data larger than 64Kb
- if CRC enabled check CRC
*/
if ((blockHdr.size > 0x7FFF) ||
(((blockHdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
(blockHdr.CRC != UCodeComputeCRC(mcData, blockHdr.size)))
if ((block_hdr.size > 0x7FFF) ||
(((block_hdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
(block_hdr.CRC != u_code_compute_crc(mc_data, block_hdr.size)))
) {
/* Wrong data ! */
return DRX_STS_INVALID_ARG;
}
mcBlockNrBytes = blockHdr.size * ((u16) sizeof(u16));
mc_block_nr_bytes = block_hdr.size * ((u16) sizeof(u16));
if (blockHdr.size != 0) {
if (block_hdr.size != 0) {
/* Perform the desired action */
switch (action) {
/*================================================================*/
case UCODE_UPLOAD:
{
/* Upload microcode */
if (demod->myAccessFunct->
writeBlockFunc(devAddr,
(DRXaddr_t) blockHdr.
addr, mcBlockNrBytes,
mcData,
if (demod->my_access_funct->
write_block_func(dev_addr,
(dr_xaddr_t) block_hdr.
addr, mc_block_nr_bytes,
mc_data,
0x0000) !=
DRX_STS_OK) {
return (DRX_STS_ERROR);
......@@ -1119,58 +1119,58 @@ CtrlUCode(pDRXDemodInstance_t demod,
case UCODE_VERIFY:
{
int result = 0;
u8 mcDataBuffer
u8 mc_dataBuffer
[DRX_UCODE_MAX_BUF_SIZE];
u32 bytesToCompare = 0;
u32 bytesLeftToCompare = 0;
DRXaddr_t currAddr = (DRXaddr_t) 0;
u8 *currPtr = NULL;
u32 bytes_to_compare = 0;
u32 bytes_left_to_compare = 0;
dr_xaddr_t curr_addr = (dr_xaddr_t) 0;
u8 *curr_ptr = NULL;
bytesLeftToCompare = mcBlockNrBytes;
currAddr = blockHdr.addr;
currPtr = mcData;
bytes_left_to_compare = mc_block_nr_bytes;
curr_addr = block_hdr.addr;
curr_ptr = mc_data;
while (bytesLeftToCompare != 0) {
if (bytesLeftToCompare >
while (bytes_left_to_compare != 0) {
if (bytes_left_to_compare >
((u32)
DRX_UCODE_MAX_BUF_SIZE)) {
bytesToCompare =
bytes_to_compare =
((u32)
DRX_UCODE_MAX_BUF_SIZE);
} else {
bytesToCompare =
bytesLeftToCompare;
bytes_to_compare =
bytes_left_to_compare;
}
if (demod->myAccessFunct->
readBlockFunc(devAddr,
currAddr,
if (demod->my_access_funct->
read_block_func(dev_addr,
curr_addr,
(u16)
bytesToCompare,
bytes_to_compare,
(u8 *)
mcDataBuffer,
mc_dataBuffer,
0x0000) !=
DRX_STS_OK) {
return (DRX_STS_ERROR);
}
result =
DRXBSP_HST_Memcmp(currPtr,
mcDataBuffer,
bytesToCompare);
drxbsp_hst_memcmp(curr_ptr,
mc_dataBuffer,
bytes_to_compare);
if (result != 0) {
return DRX_STS_ERROR;
}
currAddr +=
((DRXaddr_t)
(bytesToCompare / 2));
currPtr =
&(currPtr[bytesToCompare]);
bytesLeftToCompare -=
((u32) bytesToCompare);
} /* while( bytesToCompare > DRX_UCODE_MAX_BUF_SIZE ) */
curr_addr +=
((dr_xaddr_t)
(bytes_to_compare / 2));
curr_ptr =
&(curr_ptr[bytes_to_compare]);
bytes_left_to_compare -=
((u32) bytes_to_compare);
} /* while( bytes_to_compare > DRX_UCODE_MAX_BUF_SIZE ) */
};
break;
......@@ -1182,11 +1182,11 @@ CtrlUCode(pDRXDemodInstance_t demod,
} /* switch ( action ) */
}
/* if (blockHdr.size != 0 ) */
/* if (block_hdr.size != 0 ) */
/* Next block */
mcData += mcBlockNrBytes;
mc_data += mc_block_nr_bytes;
} /* for( i = 0 ; i<mcNrOfBlks ; i++ ) */
} /* for( i = 0 ; i<mc_nr_of_blks ; i++ ) */
return DRX_STS_OK;
}
......@@ -1196,60 +1196,60 @@ CtrlUCode(pDRXDemodInstance_t demod,
/**
* \brief Build list of version information.
* \param demod: A pointer to a demodulator instance.
* \param versionList: Pointer to linked list of versions.
* \param version_list: Pointer to linked list of versions.
* \return int.
* \retval DRX_STS_OK: Version information stored in versionList
* \retval DRX_STS_OK: Version information stored in version_list
* \retval DRX_STS_INVALID_ARG: Invalid arguments.
*/
static int
CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList)
ctrl_version(pdrx_demod_instance_t demod, p_drx_version_list_t *version_list)
{
static char drxDriverCoreModuleName[] = "Core driver";
static char drxDriverCoreVersionText[] =
static char drx_driver_core_module_name[] = "Core driver";
static char drx_driver_core_version_text[] =
DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH);
static DRXVersion_t drxDriverCoreVersion;
static DRXVersionList_t drxDriverCoreVersionList;
static drx_version_t drx_driver_core_version;
static drx_version_list_t drx_driver_core_versionList;
pDRXVersionList_t demodVersionList = (pDRXVersionList_t) (NULL);
int returnStatus = DRX_STS_ERROR;
p_drx_version_list_t demod_version_list = (p_drx_version_list_t) (NULL);
int return_status = DRX_STS_ERROR;
/* Check arguments */
if (versionList == NULL) {
if (version_list == NULL) {
return DRX_STS_INVALID_ARG;
}
/* Get version info list from demod */
returnStatus = (*(demod->myDemodFunct->ctrlFunc)) (demod,
return_status = (*(demod->my_demod_funct->ctrl_func)) (demod,
DRX_CTRL_VERSION,
(void *)
&demodVersionList);
&demod_version_list);
/* Always fill in the information of the driver SW . */
drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE;
drxDriverCoreVersion.moduleName = drxDriverCoreModuleName;
drxDriverCoreVersion.vMajor = VERSION_MAJOR;
drxDriverCoreVersion.vMinor = VERSION_MINOR;
drxDriverCoreVersion.vPatch = VERSION_PATCH;
drxDriverCoreVersion.vString = drxDriverCoreVersionText;
drx_driver_core_version.module_type = DRX_MODULE_DRIVERCORE;
drx_driver_core_version.module_name = drx_driver_core_module_name;
drx_driver_core_version.v_major = VERSION_MAJOR;
drx_driver_core_version.v_minor = VERSION_MINOR;
drx_driver_core_version.v_patch = VERSION_PATCH;
drx_driver_core_version.v_string = drx_driver_core_version_text;
drxDriverCoreVersionList.version = &drxDriverCoreVersion;
drxDriverCoreVersionList.next = (pDRXVersionList_t) (NULL);
drx_driver_core_versionList.version = &drx_driver_core_version;
drx_driver_core_versionList.next = (p_drx_version_list_t) (NULL);
if ((returnStatus == DRX_STS_OK) && (demodVersionList != NULL)) {
if ((return_status == DRX_STS_OK) && (demod_version_list != NULL)) {
/* Append versioninfo from driver to versioninfo from demod */
/* Return version info in "bottom-up" order. This way, multiple
devices can be handled without using malloc. */
pDRXVersionList_t currentListElement = demodVersionList;
while (currentListElement->next != NULL) {
currentListElement = currentListElement->next;
p_drx_version_list_t current_list_element = demod_version_list;
while (current_list_element->next != NULL) {
current_list_element = current_list_element->next;
}
currentListElement->next = &drxDriverCoreVersionList;
current_list_element->next = &drx_driver_core_versionList;
*versionList = demodVersionList;
*version_list = demod_version_list;
} else {
/* Just return versioninfo from driver */
*versionList = &drxDriverCoreVersionList;
*version_list = &drx_driver_core_versionList;
}
return DRX_STS_OK;
......@@ -1271,7 +1271,7 @@ CtrlVersion(pDRXDemodInstance_t demod, pDRXVersionList_t *versionList)
*
*/
int DRX_Init(pDRXDemodInstance_t demods[])
int drx_init(pdrx_demod_instance_t demods[])
{
return DRX_STS_OK;
}
......@@ -1287,7 +1287,7 @@ int DRX_Init(pDRXDemodInstance_t demods[])
*
*/
int DRX_Term(void)
int drx_term(void)
{
return DRX_STS_OK;
}
......@@ -1305,23 +1305,23 @@ int DRX_Term(void)
*
*/
int DRX_Open(pDRXDemodInstance_t demod)
int drx_open(pdrx_demod_instance_t demod)
{
int status = DRX_STS_OK;
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) ||
(demod->myI2CDevAddr == NULL) ||
(demod->myCommonAttr->isOpened == true)) {
(demod->my_demod_funct == NULL) ||
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
(demod->my_common_attr->is_opened == true)) {
return (DRX_STS_INVALID_ARG);
}
status = (*(demod->myDemodFunct->openFunc)) (demod);
status = (*(demod->my_demod_funct->open_func)) (demod);
if (status == DRX_STS_OK) {
demod->myCommonAttr->isOpened = true;
demod->my_common_attr->is_opened = true;
}
return status;
......@@ -1342,20 +1342,20 @@ int DRX_Open(pDRXDemodInstance_t demod)
* Put device into sleep mode.
*/
int DRX_Close(pDRXDemodInstance_t demod)
int drx_close(pdrx_demod_instance_t demod)
{
int status = DRX_STS_OK;
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) ||
(demod->myI2CDevAddr == NULL) ||
(demod->myCommonAttr->isOpened == false)) {
(demod->my_demod_funct == NULL) ||
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) ||
(demod->my_i2c_dev_addr == NULL) ||
(demod->my_common_attr->is_opened == false)) {
return DRX_STS_INVALID_ARG;
}
status = (*(demod->myDemodFunct->closeFunc)) (demod);
status = (*(demod->my_demod_funct->close_func)) (demod);
DRX_SET_ISOPENED(demod, false);
......@@ -1368,40 +1368,40 @@ int DRX_Close(pDRXDemodInstance_t demod)
* \brief Control the device.
* \param demod: A pointer to a demodulator instance.
* \param ctrl: Reference to desired control function.
* \param ctrlData: Pointer to data structure for control function.
* \param ctrl_data: Pointer to data structure for control function.
* \return int Return status.
* \retval DRX_STS_OK: Control function completed successfully.
* \retval DRX_STS_ERROR: Driver not initialized or error during
* control demod.
* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid
* \retval DRX_STS_INVALID_ARG: Demod instance or ctrl_data has invalid
* content.
* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not
* available.
*
* Data needed or returned by the control function is stored in ctrlData.
* Data needed or returned by the control function is stored in ctrl_data.
*
*/
int
DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData)
drx_ctrl(pdrx_demod_instance_t demod, u32 ctrl, void *ctrl_data)
{
int status = DRX_STS_ERROR;
if ((demod == NULL) ||
(demod->myDemodFunct == NULL) ||
(demod->myCommonAttr == NULL) ||
(demod->myExtAttr == NULL) || (demod->myI2CDevAddr == NULL)
(demod->my_demod_funct == NULL) ||
(demod->my_common_attr == NULL) ||
(demod->my_ext_attr == NULL) || (demod->my_i2c_dev_addr == NULL)
) {
return (DRX_STS_INVALID_ARG);
}
if (((demod->myCommonAttr->isOpened == false) &&
if (((demod->my_common_attr->is_opened == false) &&
(ctrl != DRX_CTRL_PROBE_DEVICE) && (ctrl != DRX_CTRL_VERSION))
) {
return (DRX_STS_INVALID_ARG);
}
if ((DRX_ISPOWERDOWNMODE(demod->myCommonAttr->currentPowerMode) &&
if ((DRX_ISPOWERDOWNMODE(demod->my_common_attr->current_power_mode) &&
(ctrl != DRX_CTRL_POWER_MODE) &&
(ctrl != DRX_CTRL_PROBE_DEVICE) &&
(ctrl != DRX_CTRL_NOP) && (ctrl != DRX_CTRL_VERSION)
......@@ -1420,7 +1420,7 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData)
/*======================================================================*/
case DRX_CTRL_VERSION:
return CtrlVersion(demod, (pDRXVersionList_t *) ctrlData);
return ctrl_version(demod, (p_drx_version_list_t *) ctrl_data);
break;
/*======================================================================*/
......@@ -1431,22 +1431,22 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData)
/* Virtual functions */
/* First try calling function from derived class */
status = (*(demod->myDemodFunct->ctrlFunc)) (demod, ctrl, ctrlData);
status = (*(demod->my_demod_funct->ctrl_func)) (demod, ctrl, ctrl_data);
if (status == DRX_STS_FUNC_NOT_AVAILABLE) {
/* Now try calling a the base class function */
switch (ctrl) {
/*===================================================================*/
case DRX_CTRL_LOAD_UCODE:
return CtrlUCode(demod,
(pDRXUCodeInfo_t) ctrlData,
return ctrl_u_code(demod,
(p_drxu_code_info_t) ctrl_data,
UCODE_UPLOAD);
break;
/*===================================================================*/
case DRX_CTRL_VERIFY_UCODE:
{
return CtrlUCode(demod,
(pDRXUCodeInfo_t) ctrlData,
return ctrl_u_code(demod,
(p_drxu_code_info_t) ctrl_data,
UCODE_VERIFY);
}
break;
......@@ -1455,22 +1455,22 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData)
/*===================================================================*/
case DRX_CTRL_SCAN_INIT:
{
return CtrlScanInit(demod,
(pDRXScanParam_t) ctrlData);
return ctrl_scan_init(demod,
(p_drx_scan_param_t) ctrl_data);
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_NEXT:
{
return CtrlScanNext(demod, (u16 *) ctrlData);
return ctrl_scan_next(demod, (u16 *) ctrl_data);
}
break;
/*===================================================================*/
case DRX_CTRL_SCAN_STOP:
{
return CtrlScanStop(demod);
return ctrl_scan_stop(demod);
}
break;
#endif /* #ifndef DRX_EXCLUDE_SCAN */
......@@ -1478,18 +1478,18 @@ DRX_Ctrl(pDRXDemodInstance_t demod, u32 ctrl, void *ctrlData)
/*===================================================================*/
case DRX_CTRL_PROGRAM_TUNER:
{
return CtrlProgramTuner(demod,
(pDRXChannel_t)
ctrlData);
return ctrl_program_tuner(demod,
(pdrx_channel_t)
ctrl_data);
}
break;
/*===================================================================*/
case DRX_CTRL_DUMP_REGISTERS:
{
return CtrlDumpRegisters(demod,
(pDRXRegDump_t)
ctrlData);
return ctrl_dump_registers(demod,
(p_drx_reg_dump_t)
ctrl_data);
}
break;
......
drivers/media/dvb-frontends/drx39xyj/drx_driver.h
View file @ 57afe2f0
......@@ -42,7 +42,7 @@
INCLUDES
-------------------------------------------------------------------------*/
enum DRXStatus {
enum drx_status {
DRX_STS_READY = 3, /**< device/service is ready */
DRX_STS_BUSY = 2, /**< device/service is busy */
DRX_STS_OK = 1, /**< everything is OK */
......@@ -54,13 +54,13 @@ enum DRXStatus {
};
/*
* This structure contains the I2C address, the device ID and a userData pointer.
* The userData pointer can be used for application specific purposes.
* This structure contains the I2C address, the device ID and a user_data pointer.
* The user_data pointer can be used for application specific purposes.
*/
struct i2c_device_addr {
u16 i2cAddr; /* The I2C address of the device. */
u16 i2cDevId; /* The device identifier. */
void *userData; /* User data pointer */
u16 i2c_addr; /* The I2C address of the device. */
u16 i2c_dev_id; /* The device identifier. */
void *user_data; /* User data pointer */
};
/**
......@@ -79,44 +79,44 @@ Exported FUNCTIONS
------------------------------------------------------------------------------*/
/**
* \fn DRXBSP_I2C_Init()
* \fn drxbsp_i2c_init()
* \brief Initialize I2C communication module.
* \return int Return status.
* \retval DRX_STS_OK Initialization successful.
* \retval DRX_STS_ERROR Initialization failed.
*/
int DRXBSP_I2C_Init(void);
int drxbsp_i2c_init(void);
/**
* \fn DRXBSP_I2C_Term()
* \fn drxbsp_i2c_term()
* \brief Terminate I2C communication module.
* \return int Return status.
* \retval DRX_STS_OK Termination successful.
* \retval DRX_STS_ERROR Termination failed.
*/
int DRXBSP_I2C_Term(void);
int drxbsp_i2c_term(void);
/**
* \fn int DRXBSP_I2C_WriteRead( struct i2c_device_addr *wDevAddr,
* u16 wCount,
* \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
* u16 w_count,
* u8 * wData,
* struct i2c_device_addr *rDevAddr,
* u16 rCount,
* u8 * rData)
* struct i2c_device_addr *r_dev_addr,
* u16 r_count,
* u8 * r_data)
* \brief Read and/or write count bytes from I2C bus, store them in data[].
* \param wDevAddr The device i2c address and the device ID to write to
* \param wCount The number of bytes to write
* \param w_dev_addr The device i2c address and the device ID to write to
* \param w_count The number of bytes to write
* \param wData The array to write the data to
* \param rDevAddr The device i2c address and the device ID to read from
* \param rCount The number of bytes to read
* \param rData The array to read the data from
* \param r_dev_addr The device i2c address and the device ID to read from
* \param r_count The number of bytes to read
* \param r_data The array to read the data from
* \return int Return status.
* \retval DRX_STS_OK Succes.
* \retval DRX_STS_ERROR Failure.
* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
* 'wdata' contains NULL.
* Idem for 'rcount' and 'rdata'.
* Both wDevAddr and rDevAddr are NULL.
* Both w_dev_addr and r_dev_addr are NULL.
*
* This function must implement an atomic write and/or read action on the I2C bus
* No other process may use the I2C bus when this function is executing.
......@@ -126,26 +126,26 @@ int DRXBSP_I2C_Term(void);
* The device ID can be useful if several devices share an I2C address.
* It can be used to control a "switch" on the I2C bus to the correct device.
*/
int DRXBSP_I2C_WriteRead(struct i2c_device_addr *wDevAddr,
u16 wCount,
int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *rDevAddr,
u16 rCount, u8 *rData);
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data);
/**
* \fn DRXBSP_I2C_ErrorText()
* \fn drxbsp_i2c_error_text()
* \brief Returns a human readable error.
* Counter part of numerical DRX_I2C_Error_g.
* Counter part of numerical drx_i2c_error_g.
*
* \return char* Pointer to human readable error text.
*/
char *DRXBSP_I2C_ErrorText(void);
char *drxbsp_i2c_error_text(void);
/**
* \var DRX_I2C_Error_g;
* \var drx_i2c_error_g;
* \brief I2C specific error codes, platform dependent.
*/
extern int DRX_I2C_Error_g;
extern int drx_i2c_error_g;
#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
......@@ -178,105 +178,105 @@ enum tuner_lock_status {
struct tuner_common {
char *name; /* Tuner brand & type name */
s32 minFreqRF; /* Lowest RF input frequency, in kHz */
s32 maxFreqRF; /* Highest RF input frequency, in kHz */
s32 min_freq_rf; /* Lowest RF input frequency, in kHz */
s32 max_freq_rf; /* Highest RF input frequency, in kHz */
u8 subMode; /* Index to sub-mode in use */
char ***subModeDescriptions; /* Pointer to description of sub-modes */
u8 subModes; /* Number of available sub-modes */
u8 sub_mode; /* Index to sub-mode in use */
char ***sub_modeDescriptions; /* Pointer to description of sub-modes */
u8 sub_modes; /* Number of available sub-modes */
/* The following fields will be either 0, NULL or false and do not need
initialisation */
void *selfCheck; /* gives proof of initialization */
bool programmed; /* only valid if selfCheck is OK */
s32 RFfrequency; /* only valid if programmed */
s32 IFfrequency; /* only valid if programmed */
void *self_check; /* gives proof of initialization */
bool programmed; /* only valid if self_check is OK */
s32 r_ffrequency; /* only valid if programmed */
s32 i_ffrequency; /* only valid if programmed */
void *myUserData; /* pointer to associated demod instance */
u16 myCapabilities; /* value for storing application flags */
void *myUser_data; /* pointer to associated demod instance */
u16 my_capabilities; /* value for storing application flags */
};
struct tuner_instance;
typedef int(*TUNEROpenFunc_t) (struct tuner_instance *tuner);
typedef int(*TUNERCloseFunc_t) (struct tuner_instance *tuner);
typedef int(*tuner_open_func_t) (struct tuner_instance *tuner);
typedef int(*tuner_close_func_t) (struct tuner_instance *tuner);
typedef int(*TUNERSetFrequencyFunc_t) (struct tuner_instance *tuner,
typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner,
u32 mode,
s32
frequency);
typedef int(*TUNERGetFrequencyFunc_t) (struct tuner_instance *tuner,
typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner,
u32 mode,
s32 *
RFfrequency,
r_ffrequency,
s32 *
IFfrequency);
i_ffrequency);
typedef int(*TUNERLockStatusFunc_t) (struct tuner_instance *tuner,
typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner,
enum tuner_lock_status *
lockStat);
lock_stat);
typedef int(*TUNERi2cWriteReadFunc_t) (struct tuner_instance *tuner,
typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner,
struct i2c_device_addr *
wDevAddr, u16 wCount,
w_dev_addr, u16 w_count,
u8 *wData,
struct i2c_device_addr *
rDevAddr, u16 rCount,
u8 *rData);
r_dev_addr, u16 r_count,
u8 *r_data);
struct tuner_ops {
TUNEROpenFunc_t openFunc;
TUNERCloseFunc_t closeFunc;
TUNERSetFrequencyFunc_t setFrequencyFunc;
TUNERGetFrequencyFunc_t getFrequencyFunc;
TUNERLockStatusFunc_t lockStatusFunc;
TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
tuner_open_func_t open_func;
tuner_close_func_t close_func;
tuner_set_frequency_func_t set_frequency_func;
tuner_get_frequency_func_t get_frequency_func;
tuner_lock_status_func_t lock_statusFunc;
tune_ri2c_write_read_func_t i2c_write_read_func;
};
struct tuner_instance {
struct i2c_device_addr myI2CDevAddr;
struct tuner_common *myCommonAttr;
void *myExtAttr;
struct tuner_ops *myFunct;
struct i2c_device_addr my_i2c_dev_addr;
struct tuner_common *my_common_attr;
void *my_ext_attr;
struct tuner_ops *my_funct;
};
int DRXBSP_TUNER_Open(struct tuner_instance *tuner);
int drxbsp_tuner_open(struct tuner_instance *tuner);
int DRXBSP_TUNER_Close(struct tuner_instance *tuner);
int drxbsp_tuner_close(struct tuner_instance *tuner);
int DRXBSP_TUNER_SetFrequency(struct tuner_instance *tuner,
int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
u32 mode,
s32 frequency);
int DRXBSP_TUNER_GetFrequency(struct tuner_instance *tuner,
int drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
u32 mode,
s32 *RFfrequency,
s32 *IFfrequency);
s32 *r_ffrequency,
s32 *i_ffrequency);
int DRXBSP_TUNER_LockStatus(struct tuner_instance *tuner,
enum tuner_lock_status *lockStat);
int drxbsp_tuner_lock_status(struct tuner_instance *tuner,
enum tuner_lock_status *lock_stat);
int DRXBSP_TUNER_DefaultI2CWriteRead(struct tuner_instance *tuner,
struct i2c_device_addr *wDevAddr,
u16 wCount,
int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner,
struct i2c_device_addr *w_dev_addr,
u16 w_count,
u8 *wData,
struct i2c_device_addr *rDevAddr,
u16 rCount, u8 *rData);
struct i2c_device_addr *r_dev_addr,
u16 r_count, u8 *r_data);
int DRXBSP_HST_Init(void);
int drxbsp_hst_init(void);
int DRXBSP_HST_Term(void);
int drxbsp_hst_term(void);
void *DRXBSP_HST_Memcpy(void *to, void *from, u32 n);
void *drxbsp_hst_memcpy(void *to, void *from, u32 n);
int DRXBSP_HST_Memcmp(void *s1, void *s2, u32 n);
int drxbsp_hst_memcmp(void *s1, void *s2, u32 n);
u32 DRXBSP_HST_Clock(void);
u32 drxbsp_hst_clock(void);
int DRXBSP_HST_Sleep(u32 n);
int drxbsp_hst_sleep(u32 n);
......@@ -856,7 +856,7 @@ enum drx_pilot_mode {
#define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */
/**
* \enum DRXUCodeAction_t
* \enum drxu_code_action_t
* \brief Used to indicate if firmware has to be uploaded or verified.
*/
......@@ -865,10 +865,10 @@ enum drx_pilot_mode {
/**< Upload the microcode image to device */
UCODE_VERIFY
/**< Compare microcode image with code on device */
} DRXUCodeAction_t, *pDRXUCodeAction_t;
} drxu_code_action_t, *pdrxu_code_action_t;
/**
* \enum DRXLockStatus_t
* \enum drx_lock_status_t
* \brief Used to reflect current lock status of demodulator.
*
* The generic lock states have device dependent semantics.
......@@ -897,7 +897,7 @@ enum drx_pilot_mode {
DRX_LOCK_STATE_9,
/**< Generic lock state */
DRX_LOCKED /**< Device is in lock */
} DRXLockStatus_t, *pDRXLockStatus_t;
} drx_lock_status_t, *pdrx_lock_status_t;
/**
* \enum DRXUIO_t
......@@ -937,10 +937,10 @@ enum drx_pilot_mode {
DRX_UIO31,
DRX_UIO32,
DRX_UIO_MAX = DRX_UIO32
} DRXUIO_t, *pDRXUIO_t;
} DRXUIO_t, *p_drxuio_t;
/**
* \enum DRXUIOMode_t
* \enum drxuio_mode_t
* \brief Used to configure the modus oprandi of a UIO.
*
* DRX_UIO_MODE_FIRMWARE is an old uio mode.
......@@ -967,10 +967,10 @@ enum drx_pilot_mode {
/**< controlled by firmware, function 4 */
DRX_UIO_MODE_FIRMWARE5 = 0x80
/**< controlled by firmware, function 5 */
} DRXUIOMode_t, *pDRXUIOMode_t;
} drxuio_mode_t, *pdrxuio_mode_t;
/**
* \enum DRXOOBDownstreamStandard_t
* \enum drxoob_downstream_standard_t
* \brief Used to select OOB standard.
*
* Based on ANSI 55-1 and 55-2
......@@ -982,7 +982,7 @@ enum drx_pilot_mode {
/**< ANSI 55-2 A */
DRX_OOB_MODE_B_GRADE_B
/**< ANSI 55-2 B */
} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
} drxoob_downstream_standard_t, *pdrxoob_downstream_standard_t;
/*-------------------------------------------------------------------------
STRUCTS
......@@ -995,13 +995,13 @@ STRUCTS
/*============================================================================*/
/**
* \enum DRXCfgType_t
* \enum drx_cfg_type_t
* \brief Generic configuration function identifiers.
*/
typedef u32 DRXCfgType_t, *pDRXCfgType_t;
typedef u32 drx_cfg_type_t, *pdrx_cfg_type_t;
#ifndef DRX_CFG_BASE
#define DRX_CFG_BASE ((DRXCfgType_t)0)
#define DRX_CFG_BASE ((drx_cfg_type_t)0)
#endif
#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */
......@@ -1032,20 +1032,20 @@ STRUCTS
/*============================================================================*/
/**
* \struct DRXUCodeInfo_t
* \struct drxu_code_info_t
* \brief Parameters for microcode upload and verfiy.
*
* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
*/
typedef struct {
u8 *mcData;
u8 *mc_data;
/**< Pointer to microcode image. */
u16 mcSize;
u16 mc_size;
/**< Microcode image size. */
} DRXUCodeInfo_t, *pDRXUCodeInfo_t;
} drxu_code_info_t, *p_drxu_code_info_t;
/**
* \struct DRXMcVersionRec_t
* \struct drx_mc_version_rec_t
* \brief Microcode version record
* Version numbers are stored in BCD format, as usual:
* o major number = bits 31-20 (first three nibbles of MSW)
......@@ -1056,43 +1056,43 @@ STRUCTS
* JTAG ID, using everything except the bond ID and the metal fix.
*
* Special values:
* - mcDevType == 0 => any device allowed
* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version)
* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version
* (mcVersion is the version)
* - mc_dev_type == 0 => any device allowed
* - mc_base_version == 0.0.0 => full microcode (mc_version is the version)
* - mc_base_version != 0.0.0 => patch microcode, the base microcode version
* (mc_version is the version)
*/
#define AUX_VER_RECORD 0x8000
typedef struct {
u16 auxType; /* type of aux data - 0x8000 for version record */
u32 mcDevType; /* device type, based on JTAG ID */
u32 mcVersion; /* version of microcode */
u32 mcBaseVersion; /* in case of patch: the original microcode version */
} DRXMcVersionRec_t, *pDRXMcVersionRec_t;
u16 aux_type; /* type of aux data - 0x8000 for version record */
u32 mc_dev_type; /* device type, based on JTAG ID */
u32 mc_version; /* version of microcode */
u32 mc_base_version; /* in case of patch: the original microcode version */
} drx_mc_version_rec_t, *pdrx_mc_version_rec_t;
/*========================================*/
/**
* \struct DRXFilterInfo_t
* \struct drx_filter_info_t
* \brief Parameters for loading filter coefficients
*
* Used by DRX_CTRL_LOAD_FILTER
*/
typedef struct {
u8 *dataRe;
u8 *data_re;
/**< pointer to coefficients for RE */
u8 *dataIm;
u8 *data_im;
/**< pointer to coefficients for IM */
u16 sizeRe;
u16 size_re;
/**< size of coefficients for RE */
u16 sizeIm;
u16 size_im;
/**< size of coefficients for IM */
} DRXFilterInfo_t, *pDRXFilterInfo_t;
} drx_filter_info_t, *pdrx_filter_info_t;
/*========================================*/
/**
* \struct DRXChannel_t
* \struct drx_channel_t
* \brief The set of parameters describing a single channel.
*
* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
......@@ -1124,46 +1124,46 @@ STRUCTS
enum drx_frame_mode framemode;
/**< frame mode */
enum drx_pilot_mode pilot; /**< pilot mode */
} DRXChannel_t, *pDRXChannel_t;
} drx_channel_t, *pdrx_channel_t;
/*========================================*/
/**
* \struct DRXSigQuality_t
* \struct drx_sig_quality_t
* Signal quality metrics.
*
* Used by DRX_CTRL_SIG_QUALITY.
*/
typedef struct {
u16 MER; /**< in steps of 0.1 dB */
u32 preViterbiBER;
/**< in steps of 1/scaleFactorBER */
u32 postViterbiBER;
/**< in steps of 1/scaleFactorBER */
u32 scaleFactorBER;
u32 pre_viterbi_ber;
/**< in steps of 1/scale_factor_ber */
u32 post_viterbi_ber;
/**< in steps of 1/scale_factor_ber */
u32 scale_factor_ber;
/**< scale factor for BER */
u16 packetError;
u16 packet_error;
/**< number of packet errors */
u32 postReedSolomonBER;
/**< in steps of 1/scaleFactorBER */
u32 preLdpcBER;
/**< in steps of 1/scaleFactorBER */
u32 averIter;/**< in steps of 0.01 */
u32 post_reed_solomon_ber;
/**< in steps of 1/scale_factor_ber */
u32 pre_ldpc_ber;
/**< in steps of 1/scale_factor_ber */
u32 aver_iter;/**< in steps of 0.01 */
u16 indicator;
/**< indicative signal quality low=0..100=high */
} DRXSigQuality_t, *pDRXSigQuality_t;
} drx_sig_quality_t, *pdrx_sig_quality_t;
typedef enum {
DRX_SQI_SPEED_FAST = 0,
DRX_SQI_SPEED_MEDIUM,
DRX_SQI_SPEED_SLOW,
DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
} drx_cfg_sqi_speed_t, *pdrx_cfg_sqi_speed_t;
/*========================================*/
/**
* \struct DRXComplex_t
* \struct drx_complex_t
* A complex number.
*
* Used by DRX_CTRL_CONSTEL.
......@@ -1173,12 +1173,12 @@ STRUCTS
/**< Imaginary part. */
s16 re;
/**< Real part. */
} DRXComplex_t, *pDRXComplex_t;
} drx_complex_t, *pdrx_complex_t;
/*========================================*/
/**
* \struct DRXFrequencyPlan_t
* \struct drx_frequency_plan_t
* Array element of a frequency plan.
*
* Used by DRX_CTRL_SCAN_INIT.
......@@ -1192,72 +1192,72 @@ STRUCTS
/**< Stepping frequency in this band */
enum drx_bandwidth bandwidth;
/**< Bandwidth within this frequency band */
u16 chNumber;
u16 ch_number;
/**< First channel number in this band, or first
index in chNames */
char **chNames;
index in ch_names */
char **ch_names;
/**< Optional list of channel names in this
band */
} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
} drx_frequency_plan_t, *p_drx_frequency_plan_t;
/*========================================*/
/**
* \struct DRXFrequencyPlanInfo_t
* \struct drx_frequency_plan_info_t
* Array element of a list of frequency plans.
*
* Used by frequency_plan.h
*/
typedef struct {
pDRXFrequencyPlan_t freqPlan;
int freqPlanSize;
char *freqPlanName;
} DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
p_drx_frequency_plan_t freq_plan;
int freq_planSize;
char *freq_planName;
} drx_frequency_plan_info_t, *pdrx_frequency_plan_info_t;
/*========================================*/
/**
* /struct DRXScanDataQam_t
* /struct drx_scan_data_qam_t
* QAM specific scanning variables
*/
typedef struct {
u32 *symbolrate; /**< list of symbolrates to scan */
u16 symbolrateSize; /**< size of symbolrate array */
u16 symbolrate_size; /**< size of symbolrate array */
enum drx_modulation *constellation;
/**< list of constellations */
u16 constellationSize; /**< size of constellation array */
u16 ifAgcThreshold; /**< thresholf for IF-AGC based
u16 constellation_size; /**< size of constellation array */
u16 if_agc_threshold; /**< thresholf for IF-AGC based
scanning filter */
} DRXScanDataQam_t, *pDRXScanDataQam_t;
} drx_scan_data_qam_t, *pdrx_scan_data_qam_t;
/*========================================*/
/**
* /struct DRXScanDataAtv_t
* /struct drx_scan_data_atv_t
* ATV specific scanning variables
*/
typedef struct {
s16 svrThreshold;
s16 svr_threshold;
/**< threshold of Sound/Video ratio in 0.1dB steps */
} DRXScanDataAtv_t, *pDRXScanDataAtv_t;
} drx_scan_data_atv_t, *pdrx_scan_data_atv_t;
/*========================================*/
/**
* \struct DRXScanParam_t
* \struct drx_scan_param_t
* Parameters for channel scan.
*
* Used by DRX_CTRL_SCAN_INIT.
*/
typedef struct {
pDRXFrequencyPlan_t frequencyPlan;
p_drx_frequency_plan_t frequency_plan;
/**< Frequency plan (array)*/
u16 frequencyPlanSize; /**< Number of bands */
u32 numTries; /**< Max channels tried */
u16 frequency_plan_size; /**< Number of bands */
u32 num_tries; /**< Max channels tried */
s32 skip; /**< Minimum frequency step to take
after a channel is found */
void *extParams; /**< Standard specific params */
} DRXScanParam_t, *pDRXScanParam_t;
void *ext_params; /**< Standard specific params */
} drx_scan_param_t, *p_drx_scan_param_t;
/*========================================*/
......@@ -1269,22 +1269,22 @@ STRUCTS
DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */
DRX_SCAN_COMMAND_NEXT, /**< Next scan */
DRX_SCAN_COMMAND_STOP /**< Stop scanning */
} DRXScanCommand_t, *pDRXScanCommand_t;
} drx_scan_command_t, *pdrx_scan_command_t;
/*========================================*/
/**
* \brief Inner scan function prototype.
*/
typedef int(*DRXScanFunc_t) (void *scanContext,
DRXScanCommand_t scanCommand,
pDRXChannel_t scanChannel,
bool *getNextChannel);
typedef int(*drx_scan_func_t) (void *scan_context,
drx_scan_command_t scan_command,
pdrx_channel_t scan_channel,
bool *get_next_channel);
/*========================================*/
/**
* \struct DRXTPSInfo_t
* \struct drxtps_info_t
* TPS information, DVB-T specific.
*
* Used by DRX_CTRL_TPS_INFO.
......@@ -1296,14 +1296,14 @@ STRUCTS
/**< Constellation */
enum drx_hierarchy hierarchy;
/**< Hierarchy */
enum drx_coderate highCoderate;
enum drx_coderate high_coderate;
/**< High code rate */
enum drx_coderate lowCoderate;
enum drx_coderate low_coderate;
/**< Low cod rate */
enum drx_tps_frame frame; /**< Tps frame */
u8 length; /**< Length */
u16 cellId; /**< Cell id */
} DRXTPSInfo_t, *pDRXTPSInfo_t;
u16 cell_id; /**< Cell id */
} drxtps_info_t, *pdrxtps_info_t;
/*========================================*/
......@@ -1350,12 +1350,12 @@ STRUCTS
/**< Device specific , Power Down Mode */
DRX_POWER_DOWN = 255
/**< Generic , Power Down Mode */
} DRXPowerMode_t, *pDRXPowerMode_t;
} drx_power_mode_t, *pdrx_power_mode_t;
/*========================================*/
/**
* \enum DRXModule_t
* \enum drx_module_t
* \brief Software module identification.
*
* Used by DRX_CTRL_VERSION.
......@@ -1370,36 +1370,36 @@ STRUCTS
DRX_MODULE_BSP_TUNER,
DRX_MODULE_BSP_HOST,
DRX_MODULE_UNKNOWN
} DRXModule_t, *pDRXModule_t;
} drx_module_t, *pdrx_module_t;
/**
* \enum DRXVersion_t
* \enum drx_version_t
* \brief Version information of one software module.
*
* Used by DRX_CTRL_VERSION.
*/
typedef struct {
DRXModule_t moduleType;
drx_module_t module_type;
/**< Type identifier of the module */
char *moduleName;
char *module_name;
/**< Name or description of module */
u16 vMajor; /**< Major version number */
u16 vMinor; /**< Minor version number */
u16 vPatch; /**< Patch version number */
char *vString; /**< Version as text string */
} DRXVersion_t, *pDRXVersion_t;
u16 v_major; /**< Major version number */
u16 v_minor; /**< Minor version number */
u16 v_patch; /**< Patch version number */
char *v_string; /**< Version as text string */
} drx_version_t, *pdrx_version_t;
/**
* \enum DRXVersionList_t
* \enum drx_version_list_t
* \brief List element of NULL terminated, linked list for version information.
*
* Used by DRX_CTRL_VERSION.
*/
typedef struct DRXVersionList_s {
pDRXVersion_t version;/**< Version information */
struct DRXVersionList_s *next;
typedef struct drx_version_list_s {
pdrx_version_t version;/**< Version information */
struct drx_version_list_s *next;
/**< Next list element */
} DRXVersionList_t, *pDRXVersionList_t;
} drx_version_list_t, *p_drx_version_list_t;
/*========================================*/
......@@ -1411,9 +1411,9 @@ STRUCTS
typedef struct {
DRXUIO_t uio;
/**< UIO identifier */
DRXUIOMode_t mode;
drxuio_mode_t mode;
/**< UIO operational mode */
} DRXUIOCfg_t, *pDRXUIOCfg_t;
} drxuio_cfg_t, *pdrxuio_cfg_t;
/*========================================*/
......@@ -1427,7 +1427,7 @@ STRUCTS
/**< UIO identifier */
bool value;
/**< UIO value (true=1, false=0) */
} DRXUIOData_t, *pDRXUIOData_t;
} drxuio_data_t, *pdrxuio_data_t;
/*========================================*/
......@@ -1438,11 +1438,11 @@ STRUCTS
*/
typedef struct {
s32 frequency; /**< Frequency in kHz */
DRXOOBDownstreamStandard_t standard;
drxoob_downstream_standard_t standard;
/**< OOB standard */
bool spectrumInverted; /**< If true, then spectrum
bool spectrum_inverted; /**< If true, then spectrum
is inverted */
} DRXOOB_t, *pDRXOOB_t;
} DRXOOB_t, *p_drxoob_t;
/*========================================*/
......@@ -1453,10 +1453,10 @@ STRUCTS
*/
typedef struct {
s32 frequency; /**< Frequency in Khz */
DRXLockStatus_t lock; /**< Lock status */
drx_lock_status_t lock; /**< Lock status */
u32 mer; /**< MER */
s32 symbolRateOffset; /**< Symbolrate offset in ppm */
} DRXOOBStatus_t, *pDRXOOBStatus_t;
s32 symbol_rate_offset; /**< Symbolrate offset in ppm */
} drxoob_status_t, *pdrxoob_status_t;
/*========================================*/
......@@ -1464,14 +1464,14 @@ STRUCTS
* \brief Device dependent configuration data.
*
* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
* A sort of nested DRX_Ctrl() functionality for device specific controls.
* A sort of nested drx_ctrl() functionality for device specific controls.
*/
typedef struct {
DRXCfgType_t cfgType;
drx_cfg_type_t cfg_type;
/**< Function identifier */
void *cfgData;
void *cfg_data;
/**< Function data */
} DRXCfg_t, *pDRXCfg_t;
} drx_cfg_t, *pdrx_cfg_t;
/*========================================*/
......@@ -1483,11 +1483,11 @@ STRUCTS
typedef enum {
DRX_MPEG_STR_WIDTH_1,
DRX_MPEG_STR_WIDTH_8
} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
} drxmpeg_str_width_t, *pdrxmpeg_str_width_t;
/* CTRL CFG MPEG ouput */
/**
* \struct DRXCfgMPEGOutput_t
* \struct drx_cfg_mpeg_output_t
* \brief Configuartion parameters for MPEG output control.
*
* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
......@@ -1495,71 +1495,71 @@ STRUCTS
*/
typedef struct {
bool enableMPEGOutput;/**< If true, enable MPEG output */
bool insertRSByte; /**< If true, insert RS byte */
bool enableParallel; /**< If true, parallel out otherwise
bool enable_mpeg_output;/**< If true, enable MPEG output */
bool insert_rs_byte; /**< If true, insert RS byte */
bool enable_parallel; /**< If true, parallel out otherwise
serial */
bool invertDATA; /**< If true, invert DATA signals */
bool invertERR; /**< If true, invert ERR signal */
bool invertSTR; /**< If true, invert STR signals */
bool invertVAL; /**< If true, invert VAL signals */
bool invertCLK; /**< If true, invert CLK signals */
bool staticCLK; /**< If true, static MPEG clockrate
bool invert_data; /**< If true, invert DATA signals */
bool invert_err; /**< If true, invert ERR signal */
bool invert_str; /**< If true, invert STR signals */
bool invert_val; /**< If true, invert VAL signals */
bool invert_clk; /**< If true, invert CLK signals */
bool static_clk; /**< If true, static MPEG clockrate
will be used, otherwise clockrate
will adapt to the bitrate of the
TS */
u32 bitrate; /**< Maximum bitrate in b/s in case
static clockrate is selected */
DRXMPEGStrWidth_t widthSTR;
drxmpeg_str_width_t width_str;
/**< MPEG start width */
} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
} drx_cfg_mpeg_output_t, *pdrx_cfg_mpeg_output_t;
/* CTRL CFG SMA */
/**
* /struct DRXCfgSMAIO_t
* /struct drx_cfg_smaio_t
* smart antenna i/o.
*/
typedef enum DRXCfgSMAIO_t {
typedef enum drx_cfg_smaio_t {
DRX_SMA_OUTPUT = 0,
DRX_SMA_INPUT
} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
} drx_cfg_smaio_t, *pdrx_cfg_smaio_t;
/**
* /struct DRXCfgSMA_t
* /struct drx_cfg_sma_t
* Set smart antenna.
*/
typedef struct {
DRXCfgSMAIO_t io;
u16 ctrlData;
bool smartAntInverted;
} DRXCfgSMA_t, *pDRXCfgSMA_t;
drx_cfg_smaio_t io;
u16 ctrl_data;
bool smart_ant_inverted;
} drx_cfg_sma_t, *pdrx_cfg_sma_t;
/*========================================*/
/**
* \struct DRXI2CData_t
* \struct drxi2c_data_t
* \brief Data for I2C via 2nd or 3rd or etc I2C port.
*
* Used by DRX_CTRL_I2C_READWRITE.
* If portNr is equal to primairy portNr BSPI2C will be used.
* If port_nr is equal to primairy port_nr BSPI2C will be used.
*
*/
typedef struct {
u16 portNr; /**< I2C port number */
struct i2c_device_addr *wDevAddr;
u16 port_nr; /**< I2C port number */
struct i2c_device_addr *w_dev_addr;
/**< Write device address */
u16 wCount; /**< Size of write data in bytes */
u16 w_count; /**< Size of write data in bytes */
u8 *wData; /**< Pointer to write data */
struct i2c_device_addr *rDevAddr;
struct i2c_device_addr *r_dev_addr;
/**< Read device address */
u16 rCount; /**< Size of data to read in bytes */
u8 *rData; /**< Pointer to read buffer */
} DRXI2CData_t, *pDRXI2CData_t;
u16 r_count; /**< Size of data to read in bytes */
u8 *r_data; /**< Pointer to read buffer */
} drxi2c_data_t, *pdrxi2c_data_t;
/*========================================*/
/**
* \enum DRXAudStandard_t
* \enum drx_aud_standard_t
* \brief Audio standard identifier.
*
* Used by DRX_CTRL_SET_AUD.
......@@ -1588,11 +1588,11 @@ STRUCTS
/**< Automatic Standard Detection */
DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
/**< used as auto and for readback */
} DRXAudStandard_t, *pDRXAudStandard_t;
} drx_aud_standard_t, *pdrx_aud_standard_t;
/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */
/* CTRL_AUD_GET_STATUS - drx_aud_status_t */
/**
* \enum DRXAudNICAMStatus_t
* \enum drx_aud_nicam_status_t
* \brief Status of NICAM carrier.
*/
typedef enum {
......@@ -1601,22 +1601,22 @@ STRUCTS
DRX_AUD_NICAM_NOT_DETECTED,
/**< NICAM carrier not detected */
DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
} drx_aud_nicam_status_t, *pdrx_aud_nicam_status_t;
/**
* \struct DRXAudStatus_t
* \struct drx_aud_status_t
* \brief Audio status characteristics.
*/
typedef struct {
bool stereo; /**< stereo detection */
bool carrierA; /**< carrier A detected */
bool carrierB; /**< carrier B detected */
bool carrier_a; /**< carrier A detected */
bool carrier_b; /**< carrier B detected */
bool sap; /**< sap / bilingual detection */
bool rds; /**< RDS data array present */
DRXAudNICAMStatus_t nicamStatus;
drx_aud_nicam_status_t nicam_status;
/**< status of NICAM carrier */
s8 fmIdent; /**< FM Identification value */
} DRXAudStatus_t, *pDRXAudStatus_t;
s8 fm_ident; /**< FM Identification value */
} drx_aud_status_t, *pdrx_aud_status_t;
/* CTRL_AUD_READ_RDS - DRXRDSdata_t */
......@@ -1627,9 +1627,9 @@ STRUCTS
typedef struct {
bool valid; /**< RDS data validation */
u16 data[18]; /**< data from one RDS data array */
} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
} drx_cfg_aud_rds_t, *pdrx_cfg_aud_rds_t;
/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */
/* DRX_CFG_AUD_VOLUME - drx_cfg_aud_volume_t - set/get */
/**
* \enum DRXAudAVCDecayTime_t
* \brief Automatic volume control configuration.
......@@ -1640,7 +1640,7 @@ STRUCTS
DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */
} DRXAudAVCMode_t, *pDRXAudAVCMode_t;
} drx_aud_avc_mode_t, *pdrx_aud_avc_mode_t;
/**
* /enum DRXAudMaxAVCGain_t
......@@ -1650,7 +1650,7 @@ STRUCTS
DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
} drx_aud_avc_max_gain_t, *pdrx_aud_avc_max_gain_t;
/**
* /enum DRXAudMaxAVCAtten_t
......@@ -1662,45 +1662,45 @@ STRUCTS
DRX_AUD_AVC_MAX_ATTEN_18DB,
/**< maximum AVC attenuation 18 dB */
DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */
} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
} drx_aud_avc_max_atten_t, *pdrx_aud_avc_max_atten_t;
/**
* \struct DRXCfgAudVolume_t
* \struct drx_cfg_aud_volume_t
* \brief Audio volume configuration.
*/
typedef struct {
bool mute; /**< mute overrides volume setting */
s16 volume; /**< volume, range -114 to 12 dB */
DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
u16 avcRefLevel; /**< AVC reference level */
DRXAudAVCMaxGain_t avcMaxGain;
drx_aud_avc_mode_t avc_mode; /**< AVC auto volume control mode */
u16 avc_ref_level; /**< AVC reference level */
drx_aud_avc_max_gain_t avc_max_gain;
/**< AVC max gain selection */
DRXAudAVCMaxAtten_t avcMaxAtten;
drx_aud_avc_max_atten_t avc_max_atten;
/**< AVC max attenuation selection */
s16 strengthLeft; /**< quasi-peak, left speaker */
s16 strengthRight; /**< quasi-peak, right speaker */
} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
s16 strength_left; /**< quasi-peak, left speaker */
s16 strength_right; /**< quasi-peak, right speaker */
} drx_cfg_aud_volume_t, *pdrx_cfg_aud_volume_t;
/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */
/* DRX_CFG_I2S_OUTPUT - drx_cfg_i2s_output_t - set/get */
/**
* \enum DRXI2SMode_t
* \enum drxi2s_mode_t
* \brief I2S output mode.
*/
typedef enum {
DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
} DRXI2SMode_t, *pDRXI2SMode_t;
} drxi2s_mode_t, *pdrxi2s_mode_t;
/**
* \enum DRXI2SWordLength_t
* \enum drxi2s_word_length_t
* \brief Width of I2S data.
*/
typedef enum {
DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */
DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
} DRXI2SWordLength_t, *pDRXI2SWordLength_t;
} drxi2s_word_length_t, *pdrxi2s_word_length_t;
/**
* \enum DRXI2SFormat_t
* \enum drxi2s_format_t
* \brief Data wordstrobe alignment for I2S.
*/
typedef enum {
......@@ -1708,34 +1708,34 @@ STRUCTS
/**< I2S data and wordstrobe are aligned */
DRX_I2S_FORMAT_WS_ADVANCED
/**< I2S data one cycle after wordstrobe */
} DRXI2SFormat_t, *pDRXI2SFormat_t;
} drxi2s_format_t, *pdrxi2s_format_t;
/**
* \enum DRXI2SPolarity_t
* \enum drxi2s_polarity_t
* \brief Polarity of I2S data.
*/
typedef enum {
DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */
DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
} DRXI2SPolarity_t, *pDRXI2SPolarity_t;
} drxi2s_polarity_t, *pdrxi2s_polarity_t;
/**
* \struct DRXCfgI2SOutput_t
* \struct drx_cfg_i2s_output_t
* \brief I2S output configuration.
*/
typedef struct {
bool outputEnable; /**< I2S output enable */
bool output_enable; /**< I2S output enable */
u32 frequency; /**< range from 8000-48000 Hz */
DRXI2SMode_t mode; /**< I2S mode, master or slave */
DRXI2SWordLength_t wordLength;
drxi2s_mode_t mode; /**< I2S mode, master or slave */
drxi2s_word_length_t word_length;
/**< I2S wordlength, 16 or 32 bits */
DRXI2SPolarity_t polarity;/**< I2S wordstrobe polarity */
DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
drxi2s_polarity_t polarity;/**< I2S wordstrobe polarity */
drxi2s_format_t format; /**< I2S wordstrobe delay to data */
} drx_cfg_i2s_output_t, *pdrx_cfg_i2s_output_t;
/* ------------------------------expert interface-----------------------------*/
/**
* /enum DRXAudFMDeemphasis_t
* /enum drx_aud_fm_deemphasis_t
* setting for FM-Deemphasis in audio demodulator.
*
*/
......@@ -1743,7 +1743,7 @@ STRUCTS
DRX_AUD_FM_DEEMPH_50US,
DRX_AUD_FM_DEEMPH_75US,
DRX_AUD_FM_DEEMPH_OFF
} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
} drx_aud_fm_deemphasis_t, *pdrx_aud_fm_deemphasis_t;
/**
* /enum DRXAudDeviation_t
......@@ -1753,17 +1753,17 @@ STRUCTS
typedef enum {
DRX_AUD_DEVIATION_NORMAL,
DRX_AUD_DEVIATION_HIGH
} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
} drx_cfg_aud_deviation_t, *pdrx_cfg_aud_deviation_t;
/**
* /enum DRXNoCarrierOption_t
* /enum drx_no_carrier_option_t
* setting for carrier, mute/noise.
*
*/
typedef enum {
DRX_NO_CARRIER_MUTE,
DRX_NO_CARRIER_NOISE
} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
} drx_no_carrier_option_t, *pdrx_no_carrier_option_t;
/**
* \enum DRXAudAutoSound_t
......@@ -1773,7 +1773,7 @@ STRUCTS
DRX_AUD_AUTO_SOUND_OFF = 0,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
} drx_cfg_aud_auto_sound_t, *pdrx_cfg_aud_auto_sound_t;
/**
* \enum DRXAudASSThres_t
......@@ -1783,30 +1783,30 @@ STRUCTS
u16 a2; /* A2 Threshold for ASS configuration */
u16 btsc; /* BTSC Threshold for ASS configuration */
u16 nicam; /* Nicam Threshold for ASS configuration */
} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
} drx_cfg_aud_ass_thres_t, *pdrx_cfg_aud_ass_thres_t;
/**
* \struct DRXAudCarrier_t
* \struct drx_aud_carrier_t
* \brief Carrier detection related parameters
*/
typedef struct {
u16 thres; /* carrier detetcion threshold for primary carrier (A) */
DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
drx_no_carrier_option_t opt; /* Mute or noise at no carrier detection (A) */
s32 shift; /* DC level of incoming signal (A) */
s32 dco; /* frequency adjustment (A) */
} DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
} drx_aud_carrier_t, *p_drx_cfg_aud_carrier_t;
/**
* \struct DRXCfgAudCarriers_t
* \struct drx_cfg_aud_carriers_t
* \brief combining carrier A & B to one struct
*/
typedef struct {
DRXAudCarrier_t a;
DRXAudCarrier_t b;
} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
drx_aud_carrier_t a;
drx_aud_carrier_t b;
} drx_cfg_aud_carriers_t, *pdrx_cfg_aud_carriers_t;
/**
* /enum DRXAudI2SSrc_t
* /enum drx_aud_i2s_src_t
* Selection of audio source
*/
typedef enum {
......@@ -1814,10 +1814,10 @@ STRUCTS
DRX_AUD_SRC_STEREO_OR_AB,
DRX_AUD_SRC_STEREO_OR_A,
DRX_AUD_SRC_STEREO_OR_B
} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
} drx_aud_i2s_src_t, *pdrx_aud_i2s_src_t;
/**
* \enum DRXAudI2SMatrix_t
* \enum drx_aud_i2s_matrix_t
* \brief Used for selecting I2S output.
*/
typedef enum {
......@@ -1828,10 +1828,10 @@ STRUCTS
DRX_AUD_I2S_MATRIX_STEREO,
/**< A+B sound, transparant */
DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
} drx_aud_i2s_matrix_t, *pdrx_aud_i2s_matrix_t;
/**
* /enum DRXAudFMMatrix_t
* /enum drx_aud_fm_matrix_t
* setting for FM-Matrix in audio demodulator.
*
*/
......@@ -1841,17 +1841,17 @@ STRUCTS
DRX_AUD_FM_MATRIX_KOREAN,
DRX_AUD_FM_MATRIX_SOUND_A,
DRX_AUD_FM_MATRIX_SOUND_B
} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
} drx_aud_fm_matrix_t, *pdrx_aud_fm_matrix_t;
/**
* \struct DRXAudMatrices_t
* \brief Mixer settings
*/
typedef struct {
DRXAudI2SSrc_t sourceI2S;
DRXAudI2SMatrix_t matrixI2S;
DRXAudFMMatrix_t matrixFm;
} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
drx_aud_i2s_src_t source_i2s;
drx_aud_i2s_matrix_t matrix_i2s;
drx_aud_fm_matrix_t matrix_fm;
} drx_cfg_aud_mixer_t, *pdrx_cfg_aud_mixer_t;
/**
* \enum DRXI2SVidSync_t
......@@ -1867,68 +1867,68 @@ STRUCTS
/**< it is a MONOCHROME system */
DRX_AUD_AVSYNC_PAL_SECAM
/**< it is a PAL/SECAM system */
} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
} drx_cfg_aud_av_sync_t, *pdrx_cfg_aud_av_sync_t;
/**
* \struct DRXCfgAudPrescale_t
* \struct drx_cfg_aud_prescale_t
* \brief Prescalers
*/
typedef struct {
u16 fmDeviation;
s16 nicamGain;
} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
u16 fm_deviation;
s16 nicam_gain;
} drx_cfg_aud_prescale_t, *pdrx_cfg_aud_prescale_t;
/**
* \struct DRXAudBeep_t
* \struct drx_aud_beep_t
* \brief Beep
*/
typedef struct {
s16 volume; /* dB */
u16 frequency; /* Hz */
bool mute;
} DRXAudBeep_t, *pDRXAudBeep_t;
} drx_aud_beep_t, *pdrx_aud_beep_t;
/**
* \enum DRXAudBtscDetect_t
* \enum drx_aud_btsc_detect_t
* \brief BTSC detetcion mode
*/
typedef enum {
DRX_BTSC_STEREO,
DRX_BTSC_MONO_AND_SAP
} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
} drx_aud_btsc_detect_t, *pdrx_aud_btsc_detect_t;
/**
* \struct DRXAudData_t
* \struct drx_aud_data_t
* \brief Audio data structure
*/
typedef struct {
/* audio storage */
bool audioIsActive;
DRXAudStandard_t audioStandard;
DRXCfgI2SOutput_t i2sdata;
DRXCfgAudVolume_t volume;
DRXCfgAudAutoSound_t autoSound;
DRXCfgAudASSThres_t assThresholds;
DRXCfgAudCarriers_t carriers;
DRXCfgAudMixer_t mixer;
DRXCfgAudDeviation_t deviation;
DRXCfgAudAVSync_t avSync;
DRXCfgAudPrescale_t prescale;
DRXAudFMDeemphasis_t deemph;
DRXAudBtscDetect_t btscDetect;
bool audio_is_active;
drx_aud_standard_t audio_standard;
drx_cfg_i2s_output_t i2sdata;
drx_cfg_aud_volume_t volume;
drx_cfg_aud_auto_sound_t auto_sound;
drx_cfg_aud_ass_thres_t ass_thresholds;
drx_cfg_aud_carriers_t carriers;
drx_cfg_aud_mixer_t mixer;
drx_cfg_aud_deviation_t deviation;
drx_cfg_aud_av_sync_t av_sync;
drx_cfg_aud_prescale_t prescale;
drx_aud_fm_deemphasis_t deemph;
drx_aud_btsc_detect_t btsc_detect;
/* rds */
u16 rdsDataCounter;
bool rdsDataPresent;
} DRXAudData_t, *pDRXAudData_t;
u16 rds_data_counter;
bool rds_data_present;
} drx_aud_data_t, *pdrx_aud_data_t;
/**
* \enum DRXQamLockRange_t
* \enum drx_qam_lock_range_t
* \brief QAM lock range mode
*/
typedef enum {
DRX_QAM_LOCKRANGE_NORMAL,
DRX_QAM_LOCKRANGE_EXTENDED
} DRXQamLockRange_t, *pDRXQamLockRange_t;
} drx_qam_lock_range_t, *pdrx_qam_lock_range_t;
/*============================================================================*/
/*============================================================================*/
......@@ -1937,108 +1937,108 @@ STRUCTS
/*============================================================================*/
/* Address on device */
typedef u32 DRXaddr_t, *pDRXaddr_t;
typedef u32 dr_xaddr_t, *pdr_xaddr_t;
/* Protocol specific flags */
typedef u32 DRXflags_t, *pDRXflags_t;
typedef u32 dr_xflags_t, *pdr_xflags_t;
/* Write block of data to device */
typedef int(*DRXWriteBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data in bytes */
u8 *data, /* data to send */
DRXflags_t flags);
dr_xflags_t flags);
/* Read block of data from device */
typedef int(*DRXReadBlockFunc_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 datasize, /* size of data in bytes */
u8 *data, /* receive buffer */
DRXflags_t flags);
dr_xflags_t flags);
/* Write 8-bits value to device */
typedef int(*DRXWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u8 data, /* data to send */
DRXflags_t flags);
dr_xflags_t flags);
/* Read 8-bits value to device */
typedef int(*DRXReadReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u8 *data, /* receive buffer */
DRXflags_t flags);
dr_xflags_t flags);
/* Read modify write 8-bits value to device */
typedef int(*DRXReadModifyWriteReg8Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* write address of register */
dr_xaddr_t raddr, /* read address of register */
u8 wdata, /* data to write */
u8 *rdata); /* data to read */
/* Write 16-bits value to device */
typedef int(*DRXWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 data, /* data to send */
DRXflags_t flags);
dr_xflags_t flags);
/* Read 16-bits value to device */
typedef int(*DRXReadReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u16 *data, /* receive buffer */
DRXflags_t flags);
dr_xflags_t flags);
/* Read modify write 16-bits value to device */
typedef int(*DRXReadModifyWriteReg16Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* write address of register */
dr_xaddr_t raddr, /* read address of register */
u16 wdata, /* data to write */
u16 *rdata); /* data to read */
/* Write 32-bits value to device */
typedef int(*DRXWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u32 data, /* data to send */
DRXflags_t flags);
dr_xflags_t flags);
/* Read 32-bits value to device */
typedef int(*DRXReadReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t addr, /* address of register/memory */
typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t addr, /* address of register/memory */
u32 *data, /* receive buffer */
DRXflags_t flags);
dr_xflags_t flags);
/* Read modify write 32-bits value to device */
typedef int(*DRXReadModifyWriteReg32Func_t) (struct i2c_device_addr *devAddr, /* address of I2C device */
DRXaddr_t waddr, /* write address of register */
DRXaddr_t raddr, /* read address of register */
typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
dr_xaddr_t waddr, /* write address of register */
dr_xaddr_t raddr, /* read address of register */
u32 wdata, /* data to write */
u32 *rdata); /* data to read */
/**
* \struct DRXAccessFunc_t
* \struct drx_access_func_t
* \brief Interface to an access protocol.
*/
typedef struct {
pDRXVersion_t protocolVersion;
DRXWriteBlockFunc_t writeBlockFunc;
DRXReadBlockFunc_t readBlockFunc;
DRXWriteReg8Func_t writeReg8Func;
DRXReadReg8Func_t readReg8Func;
DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
DRXWriteReg16Func_t writeReg16Func;
DRXReadReg16Func_t readReg16Func;
DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
DRXWriteReg32Func_t writeReg32Func;
DRXReadReg32Func_t readReg32Func;
DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
} DRXAccessFunc_t, *pDRXAccessFunc_t;
pdrx_version_t protocolVersion;
drx_write_block_func_t write_block_func;
drx_read_block_func_t read_block_func;
drx_write_reg8func_t write_reg8func;
drx_read_reg8func_t read_reg8func;
drx_read_modify_write_reg8func_t read_modify_write_reg8func;
drx_write_reg16func_t write_reg16func;
drx_read_reg16func_t read_reg16func;
drx_read_modify_write_reg16func_t read_modify_write_reg16func;
drx_write_reg32func_t write_reg32func;
drx_read_reg32func_t read_reg32func;
drx_read_modify_write_reg32func_t read_modify_write_reg32func;
} drx_access_func_t, *pdrx_access_func_t;
/* Register address and data for register dump function */
typedef struct {
DRXaddr_t address;
dr_xaddr_t address;
u32 data;
} DRXRegDump_t, *pDRXRegDump_t;
} drx_reg_dump_t, *p_drx_reg_dump_t;
/*============================================================================*/
/*============================================================================*/
......@@ -2047,131 +2047,131 @@ STRUCTS
/*============================================================================*/
/**
* \struct DRXCommonAttr_t
* \struct drx_common_attr_t
* \brief Set of common attributes, shared by all DRX devices.
*/
typedef struct {
/* Microcode (firmware) attributes */
u8 *microcode; /**< Pointer to microcode image. */
u16 microcodeSize;
u16 microcode_size;
/**< Size of microcode image in bytes. */
bool verifyMicrocode;
bool verify_microcode;
/**< Use microcode verify or not. */
DRXMcVersionRec_t mcversion;
drx_mc_version_rec_t mcversion;
/**< Version record of microcode from file */
/* Clocks and tuner attributes */
s32 intermediateFreq;
s32 intermediate_freq;
/**< IF,if tuner instance not used. (kHz)*/
s32 sysClockFreq;
s32 sys_clock_freq;
/**< Systemclock frequency. (kHz) */
s32 oscClockFreq;
s32 osc_clock_freq;
/**< Oscillator clock frequency. (kHz) */
s16 oscClockDeviation;
s16 osc_clock_deviation;
/**< Oscillator clock deviation. (ppm) */
bool mirrorFreqSpect;
bool mirror_freq_spect;
/**< Mirror IF frequency spectrum or not.*/
/* Initial MPEG output attributes */
DRXCfgMPEGOutput_t mpegCfg;
drx_cfg_mpeg_output_t mpeg_cfg;
/**< MPEG configuration */
bool isOpened; /**< if true instance is already opened. */
bool is_opened; /**< if true instance is already opened. */
/* Channel scan */
pDRXScanParam_t scanParam;
p_drx_scan_param_t scan_param;
/**< scan parameters */
u16 scanFreqPlanIndex;
u16 scan_freq_plan_index;
/**< next index in freq plan */
s32 scanNextFrequency;
s32 scan_next_frequency;
/**< next freq to scan */
bool scanReady; /**< scan ready flag */
u32 scanMaxChannels;/**< number of channels in freqplan */
u32 scanChannelsScanned;
bool scan_ready; /**< scan ready flag */
u32 scan_max_channels;/**< number of channels in freqplan */
u32 scan_channelsScanned;
/**< number of channels scanned */
/* Channel scan - inner loop: demod related */
DRXScanFunc_t scanFunction;
drx_scan_func_t scan_function;
/**< function to check channel */
/* Channel scan - inner loop: SYSObj related */
void *scanContext; /**< Context Pointer of SYSObj */
void *scan_context; /**< Context Pointer of SYSObj */
/* Channel scan - parameters for default DTV scan function in core driver */
u16 scanDemodLockTimeout;
u16 scan_demod_lock_timeout;
/**< millisecs to wait for lock */
DRXLockStatus_t scanDesiredLock;
drx_lock_status_t scan_desired_lock;
/**< lock requirement for channel found */
/* scanActive can be used by SetChannel to decide how to program the tuner,
/* scan_active can be used by SetChannel to decide how to program the tuner,
fast or slow (but stable). Usually fast during scan. */
bool scanActive; /**< true when scan routines are active */
bool scan_active; /**< true when scan routines are active */
/* Power management */
DRXPowerMode_t currentPowerMode;
drx_power_mode_t current_power_mode;
/**< current power management mode */
/* Tuner */
u8 tunerPortNr; /**< nr of I2C port to wich tuner is */
s32 tunerMinFreqRF;
u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */
s32 tuner_min_freq_rf;
/**< minimum RF input frequency, in kHz */
s32 tunerMaxFreqRF;
s32 tuner_max_freq_rf;
/**< maximum RF input frequency, in kHz */
bool tunerRfAgcPol; /**< if true invert RF AGC polarity */
bool tunerIfAgcPol; /**< if true invert IF AGC polarity */
bool tunerSlowMode; /**< if true invert IF AGC polarity */
bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */
bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */
bool tuner_slow_mode; /**< if true invert IF AGC polarity */
DRXChannel_t currentChannel;
drx_channel_t current_channel;
/**< current channel parameters */
enum drx_standard currentStandard;
enum drx_standard current_standard;
/**< current standard selection */
enum drx_standard prevStandard;
enum drx_standard prev_standard;
/**< previous standard selection */
enum drx_standard diCacheStandard;
enum drx_standard di_cache_standard;
/**< standard in DI cache if available */
bool useBootloader; /**< use bootloader in open */
bool use_bootloader; /**< use bootloader in open */
u32 capabilities; /**< capabilities flags */
u32 productId; /**< product ID inc. metal fix number */
u32 product_id; /**< product ID inc. metal fix number */
} DRXCommonAttr_t, *pDRXCommonAttr_t;
} drx_common_attr_t, *pdrx_common_attr_t;
/*
* Generic functions for DRX devices.
*/
typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
typedef struct drx_demod_instance_s *pdrx_demod_instance_t;
typedef int(*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
typedef int(*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
typedef int(*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
typedef int(*drx_open_func_t) (pdrx_demod_instance_t demod);
typedef int(*drx_close_func_t) (pdrx_demod_instance_t demod);
typedef int(*drx_ctrl_func_t) (pdrx_demod_instance_t demod,
u32 ctrl,
void *ctrlData);
void *ctrl_data);
/**
* \struct DRXDemodFunc_t
* \struct drx_demod_func_t
* \brief A stucture containing all functions of a demodulator.
*/
typedef struct {
u32 typeId; /**< Device type identifier. */
DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
DRXCloseFunc_t closeFunc;/**< Pointer to Close() function. */
DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
} DRXDemodFunc_t, *pDRXDemodFunc_t;
u32 type_id; /**< Device type identifier. */
drx_open_func_t open_func; /**< Pointer to Open() function. */
drx_close_func_t close_func;/**< Pointer to Close() function. */
drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */
} drx_demod_func_t, *pdrx_demod_func_t;
/**
* \struct DRXDemodInstance_t
* \struct drx_demod_instance_t
* \brief Top structure of demodulator instance.
*/
typedef struct DRXDemodInstance_s {
typedef struct drx_demod_instance_s {
/* type specific demodulator data */
pDRXDemodFunc_t myDemodFunct;
pdrx_demod_func_t my_demod_funct;
/**< demodulator functions */
pDRXAccessFunc_t myAccessFunct;
pdrx_access_func_t my_access_funct;
/**< data access protocol functions */
struct tuner_instance *myTuner;
struct tuner_instance *my_tuner;
/**< tuner instance,if NULL then baseband */
struct i2c_device_addr *myI2CDevAddr;
struct i2c_device_addr *my_i2c_dev_addr;
/**< i2c address and device identifier */
pDRXCommonAttr_t myCommonAttr;
pdrx_common_attr_t my_common_attr;
/**< common DRX attributes */
void *myExtAttr; /**< device specific attributes */
void *my_ext_attr; /**< device specific attributes */
/* generic demodulator data */
} DRXDemodInstance_t;
} drx_demod_instance_t;
/*-------------------------------------------------------------------------
MACROS
......@@ -2466,29 +2466,29 @@ Access macros
*
*/
#define DRX_ATTR_MCRECORD(d) ((d)->myCommonAttr->mcversion)
#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->myCommonAttr->mirrorFreqSpect)
#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->myCommonAttr->currentPowerMode)
#define DRX_ATTR_ISOPENED(d) ((d)->myCommonAttr->isOpened)
#define DRX_ATTR_USEBOOTLOADER(d) ((d)->myCommonAttr->useBootloader)
#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->myCommonAttr->currentStandard)
#define DRX_ATTR_PREVSTANDARD(d) ((d)->myCommonAttr->prevStandard)
#define DRX_ATTR_CACHESTANDARD(d) ((d)->myCommonAttr->diCacheStandard)
#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->myCommonAttr->currentChannel)
#define DRX_ATTR_MICROCODE(d) ((d)->myCommonAttr->microcode)
#define DRX_ATTR_MICROCODESIZE(d) ((d)->myCommonAttr->microcodeSize)
#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->myCommonAttr->verifyMicrocode)
#define DRX_ATTR_CAPABILITIES(d) ((d)->myCommonAttr->capabilities)
#define DRX_ATTR_PRODUCTID(d) ((d)->myCommonAttr->productId)
#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->myCommonAttr->intermediateFreq)
#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->myCommonAttr->sysClockFreq)
#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->myCommonAttr->tunerRfAgcPol)
#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->myCommonAttr->tunerIfAgcPol)
#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->myCommonAttr->tunerSlowMode)
#define DRX_ATTR_TUNERSPORTNR(d) ((d)->myCommonAttr->tunerPortNr)
#define DRX_ATTR_TUNER(d) ((d)->myTuner)
#define DRX_ATTR_I2CADDR(d) ((d)->myI2CDevAddr->i2cAddr)
#define DRX_ATTR_I2CDEVID(d) ((d)->myI2CDevAddr->i2cDevId)
#define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion)
#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect)
#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode)
#define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened)
#define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader)
#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard)
#define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard)
#define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard)
#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel)
#define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode)
#define DRX_ATTR_MICROCODESIZE(d) ((d)->my_common_attr->microcode_size)
#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode)
#define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities)
#define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id)
#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq)
#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq)
#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol)
#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol)
#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode)
#define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr)
#define DRX_ATTR_TUNER(d) ((d)->my_tuner)
#define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr)
#define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id)
/**
* \brief Actual access macro's
......@@ -2564,12 +2564,12 @@ Access macros
#define DRX_SET_MCVERTYPE(d, x) \
do { \
DRX_ATTR_MCRECORD(d).auxType = (x); \
DRX_ATTR_MCRECORD(d).aux_type = (x); \
} while (0)
#define DRX_GET_MCVERTYPE(d, x) \
do { \
(x) = DRX_ATTR_MCRECORD(d).auxType; \
(x) = DRX_ATTR_MCRECORD(d).aux_type; \
} while (0)
/**************************/
......@@ -2580,35 +2580,35 @@ Access macros
#define DRX_SET_MCDEV(d, x) \
do { \
DRX_ATTR_MCRECORD(d).mcDevType = (x); \
DRX_ATTR_MCRECORD(d).mc_dev_type = (x); \
} while (0)
#define DRX_GET_MCDEV(d, x) \
do { \
(x) = DRX_ATTR_MCRECORD(d).mcDevType; \
(x) = DRX_ATTR_MCRECORD(d).mc_dev_type; \
} while (0)
/**************************/
#define DRX_SET_MCVERSION(d, x) \
do { \
DRX_ATTR_MCRECORD(d).mcVersion = (x); \
DRX_ATTR_MCRECORD(d).mc_version = (x); \
} while (0)
#define DRX_GET_MCVERSION(d, x) \
do { \
(x) = DRX_ATTR_MCRECORD(d).mcVersion; \
(x) = DRX_ATTR_MCRECORD(d).mc_version; \
} while (0)
/**************************/
#define DRX_SET_MCPATCH(d, x) \
do { \
DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \
DRX_ATTR_MCRECORD(d).mc_base_version = (x); \
} while (0)
#define DRX_GET_MCPATCH(d, x) \
do { \
(x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \
(x) = DRX_ATTR_MCRECORD(d).mc_base_version; \
} while (0)
/**************************/
......@@ -2826,28 +2826,28 @@ Access macros
/* Macros with device-specific handling are converted to CFG functions */
#define DRX_ACCESSMACRO_SET(demod, value, cfgName, dataType) \
#define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \
do { \
DRXCfg_t config; \
dataType cfgData; \
config.cfgType = cfgName; \
config.cfgData = &cfgData; \
cfgData = value; \
DRX_Ctrl(demod, DRX_CTRL_SET_CFG, &config); \
drx_cfg_t config; \
data_type cfg_data; \
config.cfg_type = cfg_name; \
config.cfg_data = &cfg_data; \
cfg_data = value; \
drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \
} while (0)
#define DRX_ACCESSMACRO_GET(demod, value, cfgName, dataType, errorValue) \
#define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \
do { \
int cfgStatus; \
DRXCfg_t config; \
dataType cfgData; \
config.cfgType = cfgName; \
config.cfgData = &cfgData; \
cfgStatus = DRX_Ctrl(demod, DRX_CTRL_GET_CFG, &config); \
if (cfgStatus == DRX_STS_OK) { \
value = cfgData; \
int cfg_status; \
drx_cfg_t config; \
data_type cfg_data; \
config.cfg_type = cfg_name; \
config.cfg_data = &cfg_data; \
cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \
if (cfg_status == DRX_STS_OK) { \
value = cfg_data; \
} else { \
value = (dataType)errorValue; \
value = (data_type)error_value; \
} \
} while (0)
......@@ -2869,14 +2869,14 @@ Access macros
DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET( (d), (x), \
DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t)
DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t)
#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET( (d), (x), \
DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN)
DRX_XS_CFG_AUD_BTSC_DETECT, drx_aud_btsc_detect_t, DRX_UNKNOWN)
#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET( (d), (x), \
DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t)
DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t)
#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET( (d), (x), \
DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN)
DRX_XS_CFG_QAM_LOCKRANGE, drx_qam_lock_range_t, DRX_UNKNOWN)
/**
* \brief Macro to check if std is an ATV standard
......@@ -2919,16 +2919,16 @@ Access macros
Exported FUNCTIONS
-------------------------------------------------------------------------*/
int DRX_Init(pDRXDemodInstance_t demods[]);
int drx_init(pdrx_demod_instance_t demods[]);
int DRX_Term(void);
int drx_term(void);
int DRX_Open(pDRXDemodInstance_t demod);
int drx_open(pdrx_demod_instance_t demod);
int DRX_Close(pDRXDemodInstance_t demod);
int drx_close(pdrx_demod_instance_t demod);
int DRX_Ctrl(pDRXDemodInstance_t demod,
u32 ctrl, void *ctrlData);
int drx_ctrl(pdrx_demod_instance_t demod,
u32 ctrl, void *ctrl_data);
/*-------------------------------------------------------------------------
THE END
......
drivers/media/dvb-frontends/drx39xyj/drx_driver_version.h
View file @ 57afe2f0
......@@ -53,8 +53,8 @@ extern "C" {
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drx_driver_version[];
extern RegisterTableInfo_t drx_driver_version_info[];
extern register_table_t drx_driver_version[];
extern register_table_info_t drx_driver_version_info[];
#endif /* _REGISTERTABLE_ */
/*
......
drivers/media/dvb-frontends/drx39xyj/drxj.c
View file @ 57afe2f0
This source diff could not be displayed because it is too large. You can view the blob instead.
drivers/media/dvb-frontends/drx39xyj/drxj.h
View file @ 57afe2f0
......@@ -77,15 +77,15 @@ TYPEDEFS
typedef struct {
u16 command;
/**< Command number */
u16 parameterLen;
u16 parameter_len;
/**< Data length in byte */
u16 resultLen;
u16 result_len;
/**< result length in byte */
u16 *parameter;
/**< General purpous param */
u16 *result;
/**< General purpous param */
} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
} drxjscu_cmd_t, *p_drxjscu_cmd_t;
/*============================================================================*/
/*============================================================================*/
......@@ -137,25 +137,25 @@ TYPEDEFS
DRXJ_CFG_OOB_LO_POW,
DRXJ_CFG_MAX /* dummy, never to be used */
} DRXJCfgType_t, *pDRXJCfgType_t;
} drxj_cfg_type_t, *pdrxj_cfg_type_t;
/**
* /struct DRXJCfgSmartAntIO_t
* /struct drxj_cfg_smart_ant_io_t
* smart antenna i/o.
*/
typedef enum DRXJCfgSmartAntIO_t {
typedef enum drxj_cfg_smart_ant_io_t {
DRXJ_SMT_ANT_OUTPUT = 0,
DRXJ_SMT_ANT_INPUT
} DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
} drxj_cfg_smart_ant_io_t, *pdrxj_cfg_smart_ant_io_t;
/**
* /struct DRXJCfgSmartAnt_t
* /struct drxj_cfg_smart_ant_t
* Set smart antenna.
*/
typedef struct {
DRXJCfgSmartAntIO_t io;
u16 ctrlData;
} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
drxj_cfg_smart_ant_io_t io;
u16 ctrl_data;
} drxj_cfg_smart_ant_t, *p_drxj_cfg_smart_ant_t;
/**
* /struct DRXJAGCSTATUS_t
......@@ -164,101 +164,101 @@ TYPEDEFS
typedef struct {
u16 IFAGC;
u16 RFAGC;
u16 DigitalAGC;
} DRXJAgcStatus_t, *pDRXJAgcStatus_t;
u16 digital_agc;
} drxj_agc_status_t, *pdrxj_agc_status_t;
/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
/**
* /struct DRXJAgcCtrlMode_t
* /struct drxj_agc_ctrl_mode_t
* Available AGCs modes in the DRXJ.
*/
typedef enum {
DRX_AGC_CTRL_AUTO = 0,
DRX_AGC_CTRL_USER,
DRX_AGC_CTRL_OFF
} DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
} drxj_agc_ctrl_mode_t, *pdrxj_agc_ctrl_mode_t;
/**
* /struct DRXJCfgAgc_t
* /struct drxj_cfg_agc_t
* Generic interface for all AGCs present on the DRXJ.
*/
typedef struct {
enum drx_standard standard; /* standard for which these settings apply */
DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
u16 outputLevel; /* range dependent on AGC */
u16 minOutputLevel; /* range dependent on AGC */
u16 maxOutputLevel; /* range dependent on AGC */
drxj_agc_ctrl_mode_t ctrl_mode; /* off, user, auto */
u16 output_level; /* range dependent on AGC */
u16 min_output_level; /* range dependent on AGC */
u16 max_output_level; /* range dependent on AGC */
u16 speed; /* range dependent on AGC */
u16 top; /* rf-agc take over point */
u16 cutOffCurrent; /* rf-agc is accelerated if output current
u16 cut_off_current; /* rf-agc is accelerated if output current
is below cut-off current */
} DRXJCfgAgc_t, *pDRXJCfgAgc_t;
} drxj_cfg_agc_t, *p_drxj_cfg_agc_t;
/* DRXJ_CFG_PRE_SAW */
/**
* /struct DRXJCfgPreSaw_t
* /struct drxj_cfg_pre_saw_t
* Interface to configure pre SAW sense.
*/
typedef struct {
enum drx_standard standard; /* standard to which these settings apply */
u16 reference; /* pre SAW reference value, range 0 .. 31 */
bool usePreSaw; /* true algorithms must use pre SAW sense */
} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
bool use_pre_saw; /* true algorithms must use pre SAW sense */
} drxj_cfg_pre_saw_t, *p_drxj_cfg_pre_saw_t;
/* DRXJ_CFG_AFE_GAIN */
/**
* /struct DRXJCfgAfeGain_t
* /struct drxj_cfg_afe_gain_t
* Interface to configure gain of AFE (LNA + PGA).
*/
typedef struct {
enum drx_standard standard; /* standard to which these settings apply */
u16 gain; /* gain in 0.1 dB steps, DRXJ range 140 .. 335 */
} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
} drxj_cfg_afe_gain_t, *p_drxj_cfg_afe_gain_t;
/**
* /struct DRXJRSErrors_t
* /struct DRXJrs_errors_t
* Available failure information in DRXJ_FEC_RS.
*
* Container for errors that are received in the most recently finished measurment period
*
*/
typedef struct {
u16 nrBitErrors;
u16 nr_bit_errors;
/**< no of pre RS bit errors */
u16 nrSymbolErrors;
u16 nr_symbol_errors;
/**< no of pre RS symbol errors */
u16 nrPacketErrors;
u16 nr_packet_errors;
/**< no of pre RS packet errors */
u16 nrFailures;
u16 nr_failures;
/**< no of post RS failures to decode */
u16 nrSncParFailCount;
u16 nr_snc_par_fail_count;
/**< no of post RS bit erros */
} DRXJRSErrors_t, *pDRXJRSErrors_t;
} DRXJrs_errors_t, *p_drxjrs_errors_t;
/**
* /struct DRXJCfgVSBMisc_t
* /struct drxj_cfg_vsb_misc_t
* symbol error rate
*/
typedef struct {
u32 symbError;
u32 symb_error;
/**< symbol error rate sps */
} DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
} drxj_cfg_vsb_misc_t, *p_drxj_cfg_vsb_misc_t;
/**
* /enum DRXJMpegOutputClockRate_t
* /enum drxj_mpeg_output_clock_rate_t
* Mpeg output clock rate.
*
*/
typedef enum {
DRXJ_MPEG_START_WIDTH_1CLKCYC,
DRXJ_MPEG_START_WIDTH_8CLKCYC
} DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
} drxj_mpeg_start_width_t, *pdrxj_mpeg_start_width_t;
/**
* /enum DRXJMpegOutputClockRate_t
* /enum drxj_mpeg_output_clock_rate_t
* Mpeg output clock rate.
*
*/
......@@ -270,7 +270,7 @@ TYPEDEFS
DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
} DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
} drxj_mpeg_output_clock_rate_t, *pdrxj_mpeg_output_clock_rate_t;
/**
* /struct DRXJCfgMisc_t
......@@ -279,15 +279,15 @@ TYPEDEFS
* set MPEG output clock rate
*/
typedef struct {
bool disableTEIHandling; /**< if true pass (not change) TEI bit */
bool bitReverseMpegOutout; /**< if true, parallel: msb on MD0; serial: lsb out first */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
bool disable_tei_handling; /**< if true pass (not change) TEI bit */
bool bit_reverse_mpeg_outout; /**< if true, parallel: msb on MD0; serial: lsb out first */
drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate;
/**< set MPEG output clock rate that overwirtes the derived one from symbol rate */
DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output start width */
} DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
drxj_mpeg_start_width_t mpeg_start_width; /**< set MPEG output start width */
} drxj_cfg_mpeg_output_misc_t, *p_drxj_cfg_mpeg_output_misc_t;
/**
* /enum DRXJXtalFreq_t
* /enum drxj_xtal_freq_t
* Supported external crystal reference frequency.
*/
typedef enum {
......@@ -295,38 +295,38 @@ TYPEDEFS
DRXJ_XTAL_FREQ_27MHZ,
DRXJ_XTAL_FREQ_20P25MHZ,
DRXJ_XTAL_FREQ_4MHZ
} DRXJXtalFreq_t, *pDRXJXtalFreq_t;
} drxj_xtal_freq_t, *pdrxj_xtal_freq_t;
/**
* /enum DRXJXtalFreq_t
* /enum drxj_xtal_freq_t
* Supported external crystal reference frequency.
*/
typedef enum {
DRXJ_I2C_SPEED_400KBPS,
DRXJ_I2C_SPEED_100KBPS
} DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
} drxji2c_speed_t, *pdrxji2c_speed_t;
/**
* /struct DRXJCfgHwCfg_t
* /struct drxj_cfg_hw_cfg_t
* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
*/
typedef struct {
DRXJXtalFreq_t xtalFreq;
drxj_xtal_freq_t xtal_freq;
/**< crystal reference frequency */
DRXJI2CSpeed_t i2cSpeed;
drxji2c_speed_t i2c_speed;
/**< 100 or 400 kbps */
} DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
} drxj_cfg_hw_cfg_t, *p_drxj_cfg_hw_cfg_t;
/*
* DRXJ_CFG_ATV_MISC
*/
typedef struct {
s16 peakFilter; /* -8 .. 15 */
u16 noiseFilter; /* 0 .. 15 */
} DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
s16 peak_filter; /* -8 .. 15 */
u16 noise_filter; /* 0 .. 15 */
} drxj_cfg_atv_misc_t, *p_drxj_cfg_atv_misc_t;
/*
* DRXJCfgOOBMisc_t
* drxj_cfg_oob_misc_t
*/
#define DRXJ_OOB_STATE_RESET 0x0
#define DRXJ_OOB_STATE_AGN_HUNT 0x1
......@@ -340,15 +340,15 @@ TYPEDEFS
#define DRXJ_OOB_STATE_SYNC 0x40
typedef struct {
DRXJAgcStatus_t agc;
bool eqLock;
bool symTimingLock;
bool phaseLock;
bool freqLock;
bool digGainLock;
bool anaGainLock;
drxj_agc_status_t agc;
bool eq_lock;
bool sym_timing_lock;
bool phase_lock;
bool freq_lock;
bool dig_gain_lock;
bool ana_gain_lock;
u8 state;
} DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
} drxj_cfg_oob_misc_t, *p_drxj_cfg_oob_misc_t;
/*
* Index of in array of coef
......@@ -359,7 +359,7 @@ TYPEDEFS
DRXJ_OOB_LO_POW_MINUS10DB,
DRXJ_OOB_LO_POW_MINUS15DB,
DRXJ_OOB_LO_POW_MAX
} DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
} drxj_cfg_oob_lo_power_t, *p_drxj_cfg_oob_lo_power_t;
/*
* DRXJ_CFG_ATV_EQU_COEF
......@@ -369,7 +369,7 @@ TYPEDEFS
s16 coef1; /* -256 .. 255 */
s16 coef2; /* -256 .. 255 */
s16 coef3; /* -256 .. 255 */
} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
} drxj_cfg_atv_equ_coef_t, *p_drxj_cfg_atv_equ_coef_t;
/*
* Index of in array of coef
......@@ -383,7 +383,7 @@ TYPEDEFS
DRXJ_COEF_IDX_DK,
DRXJ_COEF_IDX_I,
DRXJ_COEF_IDX_MAX
} DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
} drxj_coef_array_index_t, *pdrxj_coef_array_index_t;
/*
* DRXJ_CFG_ATV_OUTPUT
......@@ -399,32 +399,32 @@ TYPEDEFS
DRXJ_SIF_ATTENUATION_3DB,
DRXJ_SIF_ATTENUATION_6DB,
DRXJ_SIF_ATTENUATION_9DB
} DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
} drxjsif_attenuation_t, *pdrxjsif_attenuation_t;
/**
* /struct DRXJCfgAtvOutput_t
* /struct drxj_cfg_atv_output_t
* SIF attenuation setting.
*
*/
typedef struct {
bool enableCVBSOutput; /* true= enabled */
bool enableSIFOutput; /* true= enabled */
DRXJSIFAttenuation_t sifAttenuation;
} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
bool enable_cvbs_output; /* true= enabled */
bool enable_sif_output; /* true= enabled */
drxjsif_attenuation_t sif_attenuation;
} drxj_cfg_atv_output_t, *p_drxj_cfg_atv_output_t;
/*
DRXJ_CFG_ATV_AGC_STATUS (get only)
*/
/* TODO : AFE interface not yet finished, subject to change */
typedef struct {
u16 rfAgcGain; /* 0 .. 877 uA */
u16 ifAgcGain; /* 0 .. 877 uA */
s16 videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */
s16 audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */
u16 rfAgcLoopGain; /* 0 .. 7 */
u16 ifAgcLoopGain; /* 0 .. 7 */
u16 videoAgcLoopGain; /* 0 .. 7 */
} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
u16 rf_agc_gain; /* 0 .. 877 uA */
u16 if_agc_gain; /* 0 .. 877 uA */
s16 video_agc_gain; /* -75 .. 1972 in 0.1 dB steps */
s16 audio_agc_gain; /* -4 .. 1020 in 0.1 dB steps */
u16 rf_agc_loop_gain; /* 0 .. 7 */
u16 if_agc_loop_gain; /* 0 .. 7 */
u16 video_agc_loop_gain; /* 0 .. 7 */
} drxj_cfg_atv_agc_status_t, *p_drxj_cfg_atv_agc_status_t;
/*============================================================================*/
/*============================================================================*/
......@@ -439,142 +439,142 @@ TYPEDEFS
/*========================================*/
/**
* /struct DRXJData_t
* /struct drxj_data_t
* DRXJ specific attributes.
*
* Global data container for DRXJ specific data.
*
*/
typedef struct {
/* device capabilties (determined during DRX_Open()) */
bool hasLNA; /**< true if LNA (aka PGA) present */
bool hasOOB; /**< true if OOB supported */
bool hasNTSC; /**< true if NTSC supported */
bool hasBTSC; /**< true if BTSC supported */
bool hasSMATX; /**< true if mat_tx is available */
bool hasSMARX; /**< true if mat_rx is available */
bool hasGPIO; /**< true if GPIO is available */
bool hasIRQN; /**< true if IRQN is available */
/* device capabilties (determined during drx_open()) */
bool has_lna; /**< true if LNA (aka PGA) present */
bool has_oob; /**< true if OOB supported */
bool has_ntsc; /**< true if NTSC supported */
bool has_btsc; /**< true if BTSC supported */
bool has_smatx; /**< true if mat_tx is available */
bool has_smarx; /**< true if mat_rx is available */
bool has_gpio; /**< true if GPIO is available */
bool has_irqn; /**< true if IRQN is available */
/* A1/A2/A... */
u8 mfx; /**< metal fix */
/* tuner settings */
bool mirrorFreqSpectOOB;/**< tuner inversion (true = tuner mirrors the signal */
bool mirror_freq_spectOOB;/**< tuner inversion (true = tuner mirrors the signal */
/* standard/channel settings */
enum drx_standard standard; /**< current standard information */
enum drx_modulation constellation;
/**< current constellation */
s32 frequency; /**< center signal frequency in KHz */
enum drx_bandwidth currBandwidth;
enum drx_bandwidth curr_bandwidth;
/**< current channel bandwidth */
enum drx_mirror mirror; /**< current channel mirror */
/* signal quality information */
u32 fecBitsDesired; /**< BER accounting period */
u16 fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
u16 qamVdPrescale; /**< Viterbi Measurement Prescale */
u16 qamVdPeriod; /**< Viterbi Measurement period */
u16 fecRsPlen; /**< defines RS BER measurement period */
u16 fecRsPrescale; /**< ReedSolomon Measurement Prescale */
u16 fecRsPeriod; /**< ReedSolomon Measurement period */
bool resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
u16 pktErrAccStart; /**< Set a flag to reset accumulated packet error */
u32 fec_bits_desired; /**< BER accounting period */
u16 fec_vd_plen; /**< no of trellis symbols: VD SER measurement period */
u16 qam_vd_prescale; /**< Viterbi Measurement Prescale */
u16 qam_vd_period; /**< Viterbi Measurement period */
u16 fec_rs_plen; /**< defines RS BER measurement period */
u16 fec_rs_prescale; /**< ReedSolomon Measurement Prescale */
u16 fec_rs_period; /**< ReedSolomon Measurement period */
bool reset_pkt_err_acc; /**< Set a flag to reset accumulated packet error */
u16 pkt_errAccStart; /**< Set a flag to reset accumulated packet error */
/* HI configuration */
u16 HICfgTimingDiv; /**< HI Configure() parameter 2 */
u16 HICfgBridgeDelay; /**< HI Configure() parameter 3 */
u16 HICfgWakeUpKey; /**< HI Configure() parameter 4 */
u16 HICfgCtrl; /**< HI Configure() parameter 5 */
u16 HICfgTransmit; /**< HI Configure() parameter 6 */
u16 hi_cfg_timing_div; /**< HI Configure() parameter 2 */
u16 hi_cfg_bridge_delay; /**< HI Configure() parameter 3 */
u16 hi_cfg_wake_up_key; /**< HI Configure() parameter 4 */
u16 hi_cfg_ctrl; /**< HI Configure() parameter 5 */
u16 hi_cfg_transmit; /**< HI Configure() parameter 6 */
/* UIO configuartion */
DRXUIOMode_t uioSmaRxMode;/**< current mode of SmaRx pin */
DRXUIOMode_t uioSmaTxMode;/**< current mode of SmaTx pin */
DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
drxuio_mode_t uio_sma_rx_mode;/**< current mode of SmaRx pin */
drxuio_mode_t uio_sma_tx_mode;/**< current mode of SmaTx pin */
drxuio_mode_t uio_gpio_mode; /**< current mode of ASEL pin */
drxuio_mode_t uio_irqn_mode; /**< current mode of IRQN pin */
/* IQM fs frequecy shift and inversion */
u32 iqmFsRateOfs; /**< frequency shifter setting after setchannel */
bool posImage; /**< Ture: positive image */
u32 iqm_fs_rate_ofs; /**< frequency shifter setting after setchannel */
bool pos_image; /**< Ture: positive image */
/* IQM RC frequecy shift */
u32 iqmRcRateOfs; /**< frequency shifter setting after setchannel */
u32 iqm_rc_rate_ofs; /**< frequency shifter setting after setchannel */
/* ATV configuartion */
u32 atvCfgChangedFlags; /**< flag: flags cfg changes */
s16 atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16 atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16 atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16 atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
bool phaseCorrectionBypass;/**< flag: true=bypass */
s16 atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16 atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
bool enableCVBSOutput; /**< flag CVBS ouput enable */
bool enableSIFOutput; /**< flag SIF ouput enable */
DRXJSIFAttenuation_t sifAttenuation;
u32 atv_cfg_changed_flags; /**< flag: flags cfg changes */
s16 atv_top_equ0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
s16 atv_top_equ1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
s16 atv_top_equ2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
s16 atv_top_equ3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
bool phase_correction_bypass;/**< flag: true=bypass */
s16 atv_top_vid_peak; /**< shadow of ATV_TOP_VID_PEAK__A */
u16 atv_top_noise_th; /**< shadow of ATV_TOP_NOISE_TH__A */
bool enable_cvbs_output; /**< flag CVBS ouput enable */
bool enable_sif_output; /**< flag SIF ouput enable */
drxjsif_attenuation_t sif_attenuation;
/**< current SIF att setting */
/* Agc configuration for QAM and VSB */
DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
drxj_cfg_agc_t qam_rf_agc_cfg; /**< qam RF AGC config */
drxj_cfg_agc_t qam_if_agc_cfg; /**< qam IF AGC config */
drxj_cfg_agc_t vsb_rf_agc_cfg; /**< vsb RF AGC config */
drxj_cfg_agc_t vsb_if_agc_cfg; /**< vsb IF AGC config */
/* PGA gain configuration for QAM and VSB */
u16 qamPgaCfg; /**< qam PGA config */
u16 vsbPgaCfg; /**< vsb PGA config */
u16 qam_pga_cfg; /**< qam PGA config */
u16 vsb_pga_cfg; /**< vsb PGA config */
/* Pre SAW configuration for QAM and VSB */
DRXJCfgPreSaw_t qamPreSawCfg;
drxj_cfg_pre_saw_t qam_pre_saw_cfg;
/**< qam pre SAW config */
DRXJCfgPreSaw_t vsbPreSawCfg;
drxj_cfg_pre_saw_t vsb_pre_saw_cfg;
/**< qam pre SAW config */
/* Version information */
char vText[2][12]; /**< allocated text versions */
DRXVersion_t vVersion[2]; /**< allocated versions structs */
DRXVersionList_t vListElements[2];
char v_text[2][12]; /**< allocated text versions */
drx_version_t v_version[2]; /**< allocated versions structs */
drx_version_list_t v_list_elements[2];
/**< allocated version list */
/* smart antenna configuration */
bool smartAntInverted;
bool smart_ant_inverted;
/* Tracking filter setting for OOB */
u16 oobTrkFilterCfg[8];
bool oobPowerOn;
u16 oob_trk_filter_cfg[8];
bool oob_power_on;
/* MPEG static bitrate setting */
u32 mpegTsStaticBitrate; /**< bitrate static MPEG output */
bool disableTEIhandling; /**< MPEG TS TEI handling */
bool bitReverseMpegOutout;/**< MPEG output bit order */
DRXJMpegOutputClockRate_t mpegOutputClockRate;
u32 mpeg_ts_static_bitrate; /**< bitrate static MPEG output */
bool disable_te_ihandling; /**< MPEG TS TEI handling */
bool bit_reverse_mpeg_outout;/**< MPEG output bit order */
drxj_mpeg_output_clock_rate_t mpeg_output_clock_rate;
/**< MPEG output clock rate */
DRXJMpegStartWidth_t mpegStartWidth;
drxj_mpeg_start_width_t mpeg_start_width;
/**< MPEG Start width */
/* Pre SAW & Agc configuration for ATV */
DRXJCfgPreSaw_t atvPreSawCfg;
drxj_cfg_pre_saw_t atv_pre_saw_cfg;
/**< atv pre SAW config */
DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
u16 atvPgaCfg; /**< atv pga config */
drxj_cfg_agc_t atv_rf_agc_cfg; /**< atv RF AGC config */
drxj_cfg_agc_t atv_if_agc_cfg; /**< atv IF AGC config */
u16 atv_pga_cfg; /**< atv pga config */
u32 currSymbolRate;
u32 curr_symbol_rate;
/* pin-safe mode */
bool pdrSafeMode; /**< PDR safe mode activated */
u16 pdrSafeRestoreValGpio;
u16 pdrSafeRestoreValVSync;
u16 pdrSafeRestoreValSmaRx;
u16 pdrSafeRestoreValSmaTx;
bool pdr_safe_mode; /**< PDR safe mode activated */
u16 pdr_safe_restore_val_gpio;
u16 pdr_safe_restore_val_v_sync;
u16 pdr_safe_restore_val_sma_rx;
u16 pdr_safe_restore_val_sma_tx;
/* OOB pre-saw value */
u16 oobPreSaw;
DRXJCfgOobLoPower_t oobLoPow;
u16 oob_pre_saw;
drxj_cfg_oob_lo_power_t oob_lo_pow;
DRXAudData_t audData;
drx_aud_data_t aud_data;
/**< audio storage */
} DRXJData_t, *pDRXJData_t;
} drxj_data_t, *pdrxj_data_t;
/*-------------------------------------------------------------------------
Access MACROS
......@@ -591,7 +591,7 @@ Access MACROS
*/
#define DRXJ_ATTR_BTSC_DETECT(d) \
(((pDRXJData_t)(d)->myExtAttr)->audData.btscDetect)
(((pdrxj_data_t)(d)->my_ext_attr)->aud_data.btsc_detect)
/**
* \brief Actual access macros
......@@ -723,20 +723,20 @@ STRUCTS
Exported FUNCTIONS
-------------------------------------------------------------------------*/
extern int DRXJ_Open(pDRXDemodInstance_t demod);
extern int DRXJ_Close(pDRXDemodInstance_t demod);
extern int DRXJ_Ctrl(pDRXDemodInstance_t demod,
u32 ctrl, void *ctrlData);
extern int drxj_open(pdrx_demod_instance_t demod);
extern int drxj_close(pdrx_demod_instance_t demod);
extern int drxj_ctrl(pdrx_demod_instance_t demod,
u32 ctrl, void *ctrl_data);
/*-------------------------------------------------------------------------
Exported GLOBAL VARIABLES
-------------------------------------------------------------------------*/
extern DRXAccessFunc_t drxDapDRXJFunct_g;
extern DRXDemodFunc_t DRXJFunctions_g;
extern DRXJData_t DRXJData_g;
extern struct i2c_device_addr DRXJDefaultAddr_g;
extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
extern DRXDemodInstance_t DRXJDefaultDemod_g;
extern drx_access_func_t drx_dap_drxj_funct_g;
extern drx_demod_func_t drxj_functions_g;
extern drxj_data_t drxj_data_g;
extern struct i2c_device_addr drxj_default_addr_g;
extern drx_common_attr_t drxj_default_comm_attr_g;
extern drx_demod_instance_t drxj_default_demod_g;
/*-------------------------------------------------------------------------
THE END
......
drivers/media/dvb-frontends/drx39xyj/drxj_map.h
View file @ 57afe2f0
......@@ -53,8 +53,8 @@ extern "C" {
#ifdef _REGISTERTABLE_
#include <registertable.h>
extern RegisterTable_t drxj_map[];
extern RegisterTableInfo_t drxj_map_info[];
extern register_table_t drxj_map[];
extern register_table_info_t drxj_map_info[];
#endif
#define ATV_COMM_EXEC__A 0xC00000
......
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