Commit 57fb32e6 authored by Maxime Ripard's avatar Maxime Ripard

drm/vc4: hdmi: Block odd horizontal timings

The FIFO between the pixelvalve and the HDMI controller runs at 2 pixels
per clock cycle, and cannot deal with odd timings.

Let's reject any mode with such timings.
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Reviewed-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201029122522.1917579-2-maxime@cerno.tech
parent 63495f6b
...@@ -768,6 +768,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, ...@@ -768,6 +768,11 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
unsigned long long pixel_rate = mode->clock * 1000; unsigned long long pixel_rate = mode->clock * 1000;
if (vc4_hdmi->variant->unsupported_odd_h_timings &&
((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
(mode->hsync_end % 2) || (mode->htotal % 2)))
return -EINVAL;
if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
return -EINVAL; return -EINVAL;
...@@ -780,6 +785,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, ...@@ -780,6 +785,11 @@ vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
{ {
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
if (vc4_hdmi->variant->unsupported_odd_h_timings &&
((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
(mode->hsync_end % 2) || (mode->htotal % 2)))
return MODE_H_ILLEGAL;
if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
return MODE_CLOCK_HIGH; return MODE_CLOCK_HIGH;
...@@ -1832,6 +1842,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { ...@@ -1832,6 +1842,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
PHY_LANE_2, PHY_LANE_2,
PHY_LANE_CK, PHY_LANE_CK,
}, },
.unsupported_odd_h_timings = true,
.init_resources = vc5_hdmi_init_resources, .init_resources = vc5_hdmi_init_resources,
.csc_setup = vc5_hdmi_csc_setup, .csc_setup = vc5_hdmi_csc_setup,
...@@ -1857,6 +1868,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { ...@@ -1857,6 +1868,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
PHY_LANE_CK, PHY_LANE_CK,
PHY_LANE_2, PHY_LANE_2,
}, },
.unsupported_odd_h_timings = true,
.init_resources = vc5_hdmi_init_resources, .init_resources = vc5_hdmi_init_resources,
.csc_setup = vc5_hdmi_csc_setup, .csc_setup = vc5_hdmi_csc_setup,
......
...@@ -62,6 +62,9 @@ struct vc4_hdmi_variant { ...@@ -62,6 +62,9 @@ struct vc4_hdmi_variant {
*/ */
enum vc4_hdmi_phy_channel phy_lane_mapping[4]; enum vc4_hdmi_phy_channel phy_lane_mapping[4];
/* The BCM2711 cannot deal with odd horizontal pixel timings */
bool unsupported_odd_h_timings;
/* Callback to get the resources (memory region, interrupts, /* Callback to get the resources (memory region, interrupts,
* clocks, etc) for that variant. * clocks, etc) for that variant.
*/ */
......
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