Commit 582a1db9 authored by David S. Miller's avatar David S. Miller

Merge branch 'qed-selftests'

Sudarsana Reddy Kalluru says:

====================
qed/qede: ethtool selftests support.

This series adds the driver support for following selftests:
1. Register test
2. Memory test
3. Clock test
4. Interrupt test
5. Internal loopback test
Patch (1) adds the qed driver infrastructure for selftests. Patches (2) and
(3) add qede driver support for ethtool selftests.

Please consider applying this series to "net-next".
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 158bc065 16f46bf0
obj-$(CONFIG_QED) := qed.o obj-$(CONFIG_QED) := qed.o
qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \ qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \
qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \
qed_selftest.o
...@@ -3857,6 +3857,7 @@ struct public_drv_mb { ...@@ -3857,6 +3857,7 @@ struct public_drv_mb {
#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
#define DRV_MSG_CODE_SET_VERSION 0x000f0000 #define DRV_MSG_CODE_SET_VERSION 0x000f0000
#define DRV_MSG_CODE_BIST_TEST 0x001e0000
#define DRV_MSG_CODE_SET_LED_MODE 0x00200000 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
...@@ -3914,6 +3915,18 @@ struct public_drv_mb { ...@@ -3914,6 +3915,18 @@ struct public_drv_mb {
#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
#define DRV_MB_PARAM_BIST_RC_PASSED 1
#define DRV_MB_PARAM_BIST_RC_FAILED 2
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
u32 fw_mb_header; u32 fw_mb_header;
#define FW_MSG_CODE_MASK 0xffff0000 #define FW_MSG_CODE_MASK 0xffff0000
#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "qed_dev_api.h" #include "qed_dev_api.h"
#include "qed_mcp.h" #include "qed_mcp.h"
#include "qed_hw.h" #include "qed_hw.h"
#include "qed_selftest.h"
static char version[] = static char version[] =
"QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n"; "QLogic FastLinQ 4xxxx Core Module qed " DRV_MODULE_VERSION "\n";
...@@ -976,6 +977,25 @@ static int qed_set_link(struct qed_dev *cdev, ...@@ -976,6 +977,25 @@ static int qed_set_link(struct qed_dev *cdev,
else else
link_params->pause.forced_tx = false; link_params->pause.forced_tx = false;
} }
if (params->override_flags & QED_LINK_OVERRIDE_LOOPBACK_MODE) {
switch (params->loopback_mode) {
case QED_LINK_LOOPBACK_INT_PHY:
link_params->loopback_mode = PMM_LOOPBACK_INT_PHY;
break;
case QED_LINK_LOOPBACK_EXT_PHY:
link_params->loopback_mode = PMM_LOOPBACK_EXT_PHY;
break;
case QED_LINK_LOOPBACK_EXT:
link_params->loopback_mode = PMM_LOOPBACK_EXT;
break;
case QED_LINK_LOOPBACK_MAC:
link_params->loopback_mode = PMM_LOOPBACK_MAC;
break;
default:
link_params->loopback_mode = PMM_LOOPBACK_NONE;
break;
}
}
rc = qed_mcp_set_link(hwfn, ptt, params->link_up); rc = qed_mcp_set_link(hwfn, ptt, params->link_up);
...@@ -1182,7 +1202,15 @@ static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode) ...@@ -1182,7 +1202,15 @@ static int qed_set_led(struct qed_dev *cdev, enum qed_led_mode mode)
return status; return status;
} }
struct qed_selftest_ops qed_selftest_ops_pass = {
.selftest_memory = &qed_selftest_memory,
.selftest_interrupt = &qed_selftest_interrupt,
.selftest_register = &qed_selftest_register,
.selftest_clock = &qed_selftest_clock,
};
const struct qed_common_ops qed_common_ops_pass = { const struct qed_common_ops qed_common_ops_pass = {
.selftest = &qed_selftest_ops_pass,
.probe = &qed_probe, .probe = &qed_probe,
.remove = &qed_remove, .remove = &qed_remove,
.set_power_state = &qed_set_power_state, .set_power_state = &qed_set_power_state,
......
...@@ -1017,3 +1017,45 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, ...@@ -1017,3 +1017,45 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
return rc; return rc;
} }
int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 drv_mb_param = 0, rsp, param;
int rc = 0;
drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, &param);
if (rc)
return rc;
if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
(param != DRV_MB_PARAM_BIST_RC_PASSED))
rc = -EAGAIN;
return rc;
}
int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
{
u32 drv_mb_param, rsp, param;
int rc = 0;
drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, &param);
if (rc)
return rc;
if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
(param != DRV_MB_PARAM_BIST_RC_PASSED))
rc = -EAGAIN;
return rc;
}
...@@ -245,6 +245,28 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn, ...@@ -245,6 +245,28 @@ int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, struct qed_ptt *p_ptt,
enum qed_led_mode mode); enum qed_led_mode mode);
/**
* @brief Bist register test
*
* @param p_hwfn - hw function
* @param p_ptt - PTT required for register access
*
* @return int - 0 - operation was successful.
*/
int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/**
* @brief Bist clock test
*
* @param p_hwfn - hw function
* @param p_ptt - PTT required for register access
*
* @return int - 0 - operation was successful.
*/
int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt);
/* Using hwfn number (and not pf_num) is required since in CMT mode, /* Using hwfn number (and not pf_num) is required since in CMT mode,
* same pf_num may be used by two different hwfn * same pf_num may be used by two different hwfn
* TODO - this shouldn't really be in .h file, but until all fields * TODO - this shouldn't really be in .h file, but until all fields
......
#include "qed.h"
#include "qed_dev_api.h"
#include "qed_mcp.h"
#include "qed_sp.h"
int qed_selftest_memory(struct qed_dev *cdev)
{
int rc = 0, i;
for_each_hwfn(cdev, i) {
rc = qed_sp_heartbeat_ramrod(&cdev->hwfns[i]);
if (rc)
return rc;
}
return rc;
}
int qed_selftest_interrupt(struct qed_dev *cdev)
{
int rc = 0, i;
for_each_hwfn(cdev, i) {
rc = qed_sp_heartbeat_ramrod(&cdev->hwfns[i]);
if (rc)
return rc;
}
return rc;
}
int qed_selftest_register(struct qed_dev *cdev)
{
struct qed_hwfn *p_hwfn;
struct qed_ptt *p_ptt;
int rc = 0, i;
/* although performed by MCP, this test is per engine */
for_each_hwfn(cdev, i) {
p_hwfn = &cdev->hwfns[i];
p_ptt = qed_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_ERR(p_hwfn, "failed to acquire ptt\n");
return -EBUSY;
}
rc = qed_mcp_bist_register_test(p_hwfn, p_ptt);
qed_ptt_release(p_hwfn, p_ptt);
if (rc)
break;
}
return rc;
}
int qed_selftest_clock(struct qed_dev *cdev)
{
struct qed_hwfn *p_hwfn;
struct qed_ptt *p_ptt;
int rc = 0, i;
/* although performed by MCP, this test is per engine */
for_each_hwfn(cdev, i) {
p_hwfn = &cdev->hwfns[i];
p_ptt = qed_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_ERR(p_hwfn, "failed to acquire ptt\n");
return -EBUSY;
}
rc = qed_mcp_bist_clock_test(p_hwfn, p_ptt);
qed_ptt_release(p_hwfn, p_ptt);
if (rc)
break;
}
return rc;
}
#ifndef _QED_SELFTEST_API_H
#define _QED_SELFTEST_API_H
#include <linux/types.h>
/**
* @brief qed_selftest_memory - Perform memory test
*
* @param cdev
*
* @return int
*/
int qed_selftest_memory(struct qed_dev *cdev);
/**
* @brief qed_selftest_interrupt - Perform interrupt test
*
* @param cdev
*
* @return int
*/
int qed_selftest_interrupt(struct qed_dev *cdev);
/**
* @brief qed_selftest_register - Perform register test
*
* @param cdev
*
* @return int
*/
int qed_selftest_register(struct qed_dev *cdev);
/**
* @brief qed_selftest_clock - Perform clock test
*
* @param cdev
*
* @return int
*/
int qed_selftest_clock(struct qed_dev *cdev);
#endif
...@@ -369,4 +369,14 @@ int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn, ...@@ -369,4 +369,14 @@ int qed_sp_pf_update_tunn_cfg(struct qed_hwfn *p_hwfn,
struct qed_tunn_update_params *p_tunn, struct qed_tunn_update_params *p_tunn,
enum spq_mode comp_mode, enum spq_mode comp_mode,
struct qed_spq_comp_cb *p_comp_data); struct qed_spq_comp_cb *p_comp_data);
/**
* @brief qed_sp_heartbeat_ramrod - Send empty Ramrod
*
* @param p_hwfn
*
* @return int
*/
int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn);
#endif #endif
...@@ -428,3 +428,24 @@ int qed_sp_pf_stop(struct qed_hwfn *p_hwfn) ...@@ -428,3 +428,24 @@ int qed_sp_pf_stop(struct qed_hwfn *p_hwfn)
return qed_spq_post(p_hwfn, p_ent, NULL); return qed_spq_post(p_hwfn, p_ent, NULL);
} }
int qed_sp_heartbeat_ramrod(struct qed_hwfn *p_hwfn)
{
struct qed_spq_entry *p_ent = NULL;
struct qed_sp_init_data init_data;
int rc;
/* Get SPQ entry */
memset(&init_data, 0, sizeof(init_data));
init_data.cid = qed_spq_get_cid(p_hwfn);
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
init_data.comp_mode = QED_SPQ_MODE_EBLOCK;
rc = qed_sp_init_request(p_hwfn, &p_ent,
COMMON_RAMROD_EMPTY, PROTOCOLID_COMMON,
&init_data);
if (rc)
return rc;
return qed_spq_post(p_hwfn, p_ent, NULL);
}
...@@ -308,6 +308,10 @@ void qede_reload(struct qede_dev *edev, ...@@ -308,6 +308,10 @@ void qede_reload(struct qede_dev *edev,
union qede_reload_args *args); union qede_reload_args *args);
int qede_change_mtu(struct net_device *dev, int new_mtu); int qede_change_mtu(struct net_device *dev, int new_mtu);
void qede_fill_by_demand_stats(struct qede_dev *edev); void qede_fill_by_demand_stats(struct qede_dev *edev);
bool qede_has_rx_work(struct qede_rx_queue *rxq);
int qede_txq_has_work(struct qede_tx_queue *txq);
void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, struct qede_dev *edev,
u8 count);
#define RX_RING_SIZE_POW 13 #define RX_RING_SIZE_POW 13
#define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW)) #define RX_RING_SIZE ((u16)BIT(RX_RING_SIZE_POW))
......
...@@ -668,7 +668,7 @@ netdev_tx_t qede_start_xmit(struct sk_buff *skb, ...@@ -668,7 +668,7 @@ netdev_tx_t qede_start_xmit(struct sk_buff *skb,
return NETDEV_TX_OK; return NETDEV_TX_OK;
} }
static int qede_txq_has_work(struct qede_tx_queue *txq) int qede_txq_has_work(struct qede_tx_queue *txq)
{ {
u16 hw_bd_cons; u16 hw_bd_cons;
...@@ -751,7 +751,7 @@ static int qede_tx_int(struct qede_dev *edev, ...@@ -751,7 +751,7 @@ static int qede_tx_int(struct qede_dev *edev,
return 0; return 0;
} }
static bool qede_has_rx_work(struct qede_rx_queue *rxq) bool qede_has_rx_work(struct qede_rx_queue *rxq)
{ {
u16 hw_comp_cons, sw_comp_cons; u16 hw_comp_cons, sw_comp_cons;
...@@ -806,7 +806,7 @@ static inline void qede_reuse_page(struct qede_dev *edev, ...@@ -806,7 +806,7 @@ static inline void qede_reuse_page(struct qede_dev *edev,
/* In case of allocation failures reuse buffers /* In case of allocation failures reuse buffers
* from consumer index to produce buffers for firmware * from consumer index to produce buffers for firmware
*/ */
static void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq, void qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
struct qede_dev *edev, u8 count) struct qede_dev *edev, u8 count)
{ {
struct sw_rx_data *curr_cons; struct sw_rx_data *curr_cons;
......
...@@ -110,6 +110,7 @@ struct qed_link_params { ...@@ -110,6 +110,7 @@ struct qed_link_params {
#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1) #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2) #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3) #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
u32 override_flags; u32 override_flags;
bool autoneg; bool autoneg;
u32 adv_speeds; u32 adv_speeds;
...@@ -118,6 +119,12 @@ struct qed_link_params { ...@@ -118,6 +119,12 @@ struct qed_link_params {
#define QED_LINK_PAUSE_RX_ENABLE BIT(1) #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
#define QED_LINK_PAUSE_TX_ENABLE BIT(2) #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
u32 pause_config; u32 pause_config;
#define QED_LINK_LOOPBACK_NONE BIT(0)
#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
#define QED_LINK_LOOPBACK_EXT BIT(3)
#define QED_LINK_LOOPBACK_MAC BIT(4)
u32 loopback_mode;
}; };
struct qed_link_output { struct qed_link_output {
...@@ -158,7 +165,47 @@ struct qed_common_cb_ops { ...@@ -158,7 +165,47 @@ struct qed_common_cb_ops {
struct qed_link_output *link); struct qed_link_output *link);
}; };
struct qed_selftest_ops {
/**
* @brief selftest_interrupt - Perform interrupt test
*
* @param cdev
*
* @return 0 on success, error otherwise.
*/
int (*selftest_interrupt)(struct qed_dev *cdev);
/**
* @brief selftest_memory - Perform memory test
*
* @param cdev
*
* @return 0 on success, error otherwise.
*/
int (*selftest_memory)(struct qed_dev *cdev);
/**
* @brief selftest_register - Perform register test
*
* @param cdev
*
* @return 0 on success, error otherwise.
*/
int (*selftest_register)(struct qed_dev *cdev);
/**
* @brief selftest_clock - Perform clock test
*
* @param cdev
*
* @return 0 on success, error otherwise.
*/
int (*selftest_clock)(struct qed_dev *cdev);
};
struct qed_common_ops { struct qed_common_ops {
struct qed_selftest_ops *selftest;
struct qed_dev* (*probe)(struct pci_dev *dev, struct qed_dev* (*probe)(struct pci_dev *dev,
enum qed_protocol protocol, enum qed_protocol protocol,
u32 dp_module, u8 dp_level); u32 dp_module, u8 dp_level);
......
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