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Commit 5a2db4e3 authored by Uwe Kleine-König's avatar Uwe Kleine-König
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ARM: mx51: clean up mx51 header 

This makes the header more look like the other ones, i.e.

 - sort #defines by value
 - use lowercase hex constants
 - use a consistently named header guard
Acked-by: default avatarJason Wang <jason77.wang@gmail.com>
Acked-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
parent 64703108
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Showing with 300 additions and 308 deletions
arch/arm/plat-mxc/include/mach/mx51.h
View file @ 5a2db4e3
#ifndef __ASM_ARCH_MXC_MX51_H__ #ifndef __MACH_MX51_H__
#define __ASM_ARCH_MXC_MX51_H__ #define __MACH_MX51_H__
/* /*
* MX51 memory map: * MX51 memory map:
...@@ -7,24 +7,23 @@ ...@@ -7,24 +7,23 @@
* *
* Virt Phys Size What * Virt Phys Size What
* --------------------------------------------------------------------------- * ---------------------------------------------------------------------------
* FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
* 30000000 256M GPU * 30000000 256M GPU
* 40000000 512M IPU * 40000000 512M IPU
* FA200000 60000000 1M DEBUG * fa200000 60000000 1M DEBUG
* FB100000 70000000 1M SPBA 0 * fb100000 70000000 1M SPBA 0
* FB000000 73F00000 1M AIPS 1 * fb000000 73f00000 1M AIPS 1
* FB200000 83F00000 1M AIPS 2 * fb200000 83f00000 1M AIPS 2
* 8FFFC000 16K TZIC (interrupt controller) * 8fffc000 16K TZIC (interrupt controller)
* 90000000 256M CSD0 SDRAM/DDR * 90000000 256M CSD0 SDRAM/DDR
* A0000000 256M CSD1 SDRAM/DDR * a0000000 256M CSD1 SDRAM/DDR
* B0000000 128M CS0 Flash * b0000000 128M CS0 Flash
* B8000000 128M CS1 Flash * b8000000 128M CS1 Flash
* C0000000 128M CS2 Flash * c0000000 128M CS2 Flash
* C8000000 64M CS3 Flash * c8000000 64M CS3 Flash
* CC000000 32M CS4 SRAM * cc000000 32M CS4 SRAM
* CE000000 32M CS5 SRAM * ce000000 32M CS5 SRAM
* CFFF0000 64K NFC (NAND Flash AXI) * cfff0000 64K NFC (NAND Flash AXI)
*
*/ */
/* /*
...@@ -36,65 +35,140 @@ ...@@ -36,65 +35,140 @@
/* /*
* IRAM * IRAM
*/ */
#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 #define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
#define MX51_IRAM_PARTITIONS 16 #define MX51_IRAM_PARTITIONS 16
#define MX51_IRAM_PARTITIONS_TO1 12
#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ #define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
/*
* NFC
*/
#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */
#define MX51_NFC_AXI_SIZE SZ_64K
/*
* Graphics Memory of GPU
*/
#define MX51_GPU_BASE_ADDR 0x20000000 #define MX51_GPU_BASE_ADDR 0x20000000
#define MX51_GPU2D_BASE_ADDR 0xD0000000 #define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000
#define MX51_TZIC_BASE_ADDR 0xE0000000
#define MX51_DEBUG_BASE_ADDR 0x60000000 #define MX51_DEBUG_BASE_ADDR 0x60000000
#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 #define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
#define MX51_DEBUG_SIZE SZ_1M #define MX51_DEBUG_SIZE SZ_1M
#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000)
#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) #define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) #define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) #define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) #define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) #define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) #define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) #define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
/* /*
* SPBA global module enabled #0 * SPBA global module enabled #0
*/ */
#define MX51_SPBA0_BASE_ADDR 0x70000000 #define MX51_SPBA0_BASE_ADDR 0x70000000
#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 #define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
#define MX51_SPBA0_SIZE SZ_1M #define MX51_SPBA0_SIZE SZ_1M
#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) #define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) #define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) #define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) #define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) #define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) #define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) #define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) #define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) #define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) #define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) #define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) #define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
/*
* AIPS 1
*/
#define MX51_AIPS1_BASE_ADDR 0x73f00000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
/*
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83f00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
#define MX51_CSD0_BASE_ADDR 0x90000000
#define MX51_CSD1_BASE_ADDR 0xa0000000
#define MX51_CS0_BASE_ADDR 0xb0000000
#define MX51_CS1_BASE_ADDR 0xb8000000
#define MX51_CS2_BASE_ADDR 0xc0000000
#define MX51_CS3_BASE_ADDR 0xc8000000
#define MX51_CS4_BASE_ADDR 0xcc000000
#define MX51_CS5_BASE_ADDR 0xce000000
/*
* NFC
*/
#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
#define MX51_NFC_AXI_SIZE SZ_64K
#define MX51_GPU2D_BASE_ADDR 0xd0000000
#define MX51_TZIC_BASE_ADDR 0xe0000000
/* /*
* defines for SPBA modules * defines for SPBA modules
*/ */
#define MX51_SPBA_SDHC1 0x04 #define MX51_SPBA_SDHC1 0x04
#define MX51_SPBA_SDHC2 0x08 #define MX51_SPBA_SDHC2 0x08
#define MX51_SPBA_UART3 0x0C #define MX51_SPBA_UART3 0x0c
#define MX51_SPBA_CSPI1 0x10 #define MX51_SPBA_CSPI1 0x10
#define MX51_SPBA_SSI2 0x14 #define MX51_SPBA_SSI2 0x14
#define MX51_SPBA_SDHC3 0x20 #define MX51_SPBA_SDHC3 0x20
...@@ -103,35 +177,7 @@ ...@@ -103,35 +177,7 @@
#define MX51_SPBA_ATA 0x30 #define MX51_SPBA_ATA 0x30
#define MX51_SPBA_SLIM 0x34 #define MX51_SPBA_SLIM 0x34
#define MX51_SPBA_HSI2C 0x38 #define MX51_SPBA_HSI2C 0x38
#define MX51_SPBA_CTRL 0x3C #define MX51_SPBA_CTRL 0x3c
/*
* AIPS 1
*/
#define MX51_AIPS1_BASE_ADDR 0x73F00000
#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
#define MX51_AIPS1_SIZE SZ_1M
#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
/* /*
* Defines for modules using static and dynamic DMA channels * Defines for modules using static and dynamic DMA channels
...@@ -164,60 +210,6 @@ ...@@ -164,60 +210,6 @@
#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL #define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL #define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
/*
* AIPS 2
*/
#define MX51_AIPS2_BASE_ADDR 0x83F00000
#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
#define MX51_AIPS2_SIZE SZ_1M
#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
/*
* Memory regions and CS
*/
#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
#define MX51_CSD0_BASE_ADDR 0x90000000
#define MX51_CSD1_BASE_ADDR 0xA0000000
#define MX51_CS0_BASE_ADDR 0xB0000000
#define MX51_CS1_BASE_ADDR 0xB8000000
#define MX51_CS2_BASE_ADDR 0xC0000000
#define MX51_CS3_BASE_ADDR 0xC8000000
#define MX51_CS4_BASE_ADDR 0xCC000000
#define MX51_CS5_BASE_ADDR 0xCE000000
/* Does given address belongs to the specified memory region? */ /* Does given address belongs to the specified memory region? */
#define ADDRESS_IN_REGION(addr, start, size) \ #define ADDRESS_IN_REGION(addr, start, size) \
(((addr) >= (start)) && ((addr) < (start)+(size))) (((addr) >= (start)) && ((addr) < (start)+(size)))
...@@ -230,7 +222,7 @@ ...@@ -230,7 +222,7 @@
* This macro defines the physical to virtual address mapping for all the * This macro defines the physical to virtual address mapping for all the
* peripheral modules. It is used by passing in the physical address as x * peripheral modules. It is used by passing in the physical address as x
* and returning the virtual address. If the physical address is not mapped, * and returning the virtual address. If the physical address is not mapped,
* it returns 0xDEADBEEF * it returns 0xdeadbeef
*/ */
#define MX51_IO_ADDRESS(x) \ #define MX51_IO_ADDRESS(x) \
...@@ -240,7 +232,7 @@ ...@@ -240,7 +232,7 @@
MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
0xDEADBEEF) 0xdeadbeef)
/* /*
* define the address mapping macros: in physical address order * define the address mapping macros: in physical address order
...@@ -265,54 +257,54 @@ ...@@ -265,54 +257,54 @@
/* /*
* DMA request assignments * DMA request assignments
*/ */
#define MX51_DMA_REQ_SSI3_TX1 47
#define MX51_DMA_REQ_SSI3_RX1 46
#define MX51_DMA_REQ_SPDIF 45
#define MX51_DMA_REQ_UART3_TX 44
#define MX51_DMA_REQ_UART3_RX 43
#define MX51_DMA_REQ_SLIM_B_TX 42
#define MX51_DMA_REQ_SDHC4 41
#define MX51_DMA_REQ_SDHC3 40
#define MX51_DMA_REQ_CSPI_TX 39
#define MX51_DMA_REQ_CSPI_RX 38
#define MX51_DMA_REQ_SSI3_TX2 37
#define MX51_DMA_REQ_IPU 36
#define MX51_DMA_REQ_SSI3_RX2 35
#define MX51_DMA_REQ_EPIT2 34
#define MX51_DMA_REQ_CTI2_1 33
#define MX51_DMA_REQ_EMI_WR 32
#define MX51_DMA_REQ_CTI2_0 31
#define MX51_DMA_REQ_EMI_RD 30
#define MX51_DMA_REQ_SSI1_TX1 29
#define MX51_DMA_REQ_SSI1_RX1 28
#define MX51_DMA_REQ_SSI1_TX2 27
#define MX51_DMA_REQ_SSI1_RX2 26
#define MX51_DMA_REQ_SSI2_TX1 25
#define MX51_DMA_REQ_SSI2_RX1 24
#define MX51_DMA_REQ_SSI2_TX2 23
#define MX51_DMA_REQ_SSI2_RX2 22
#define MX51_DMA_REQ_SDHC2 21
#define MX51_DMA_REQ_SDHC1 20
#define MX51_DMA_REQ_UART1_TX 19
#define MX51_DMA_REQ_UART1_RX 18
#define MX51_DMA_REQ_UART2_TX 17
#define MX51_DMA_REQ_UART2_RX 16
#define MX51_DMA_REQ_GPU 15
#define MX51_DMA_REQ_EXTREQ1 14
#define MX51_DMA_REQ_FIRI_TX 13
#define MX51_DMA_REQ_FIRI_RX 12
#define MX51_DMA_REQ_HS_I2C_RX 11
#define MX51_DMA_REQ_HS_I2C_TX 10
#define MX51_DMA_REQ_CSPI2_TX 9
#define MX51_DMA_REQ_CSPI2_RX 8
#define MX51_DMA_REQ_CSPI1_TX 7
#define MX51_DMA_REQ_CSPI1_RX 6
#define MX51_DMA_REQ_SLIM_B 5
#define MX51_DMA_REQ_ATA_TX_END 4
#define MX51_DMA_REQ_ATA_TX 3
#define MX51_DMA_REQ_ATA_RX 2
#define MX51_DMA_REQ_GPC 1
#define MX51_DMA_REQ_VPU 0 #define MX51_DMA_REQ_VPU 0
#define MX51_DMA_REQ_GPC 1
#define MX51_DMA_REQ_ATA_RX 2
#define MX51_DMA_REQ_ATA_TX 3
#define MX51_DMA_REQ_ATA_TX_END 4
#define MX51_DMA_REQ_SLIM_B 5
#define MX51_DMA_REQ_CSPI1_RX 6
#define MX51_DMA_REQ_CSPI1_TX 7
#define MX51_DMA_REQ_CSPI2_RX 8
#define MX51_DMA_REQ_CSPI2_TX 9
#define MX51_DMA_REQ_HS_I2C_TX 10
#define MX51_DMA_REQ_HS_I2C_RX 11
#define MX51_DMA_REQ_FIRI_RX 12
#define MX51_DMA_REQ_FIRI_TX 13
#define MX51_DMA_REQ_EXTREQ1 14
#define MX51_DMA_REQ_GPU 15
#define MX51_DMA_REQ_UART2_RX 16
#define MX51_DMA_REQ_UART2_TX 17
#define MX51_DMA_REQ_UART1_RX 18
#define MX51_DMA_REQ_UART1_TX 19
#define MX51_DMA_REQ_SDHC1 20
#define MX51_DMA_REQ_SDHC2 21
#define MX51_DMA_REQ_SSI2_RX2 22
#define MX51_DMA_REQ_SSI2_TX2 23
#define MX51_DMA_REQ_SSI2_RX1 24
#define MX51_DMA_REQ_SSI2_TX1 25
#define MX51_DMA_REQ_SSI1_RX2 26
#define MX51_DMA_REQ_SSI1_TX2 27
#define MX51_DMA_REQ_SSI1_RX1 28
#define MX51_DMA_REQ_SSI1_TX1 29
#define MX51_DMA_REQ_EMI_RD 30
#define MX51_DMA_REQ_CTI2_0 31
#define MX51_DMA_REQ_EMI_WR 32
#define MX51_DMA_REQ_CTI2_1 33
#define MX51_DMA_REQ_EPIT2 34
#define MX51_DMA_REQ_SSI3_RX2 35
#define MX51_DMA_REQ_IPU 36
#define MX51_DMA_REQ_SSI3_TX2 37
#define MX51_DMA_REQ_CSPI_RX 38
#define MX51_DMA_REQ_CSPI_TX 39
#define MX51_DMA_REQ_SDHC3 40
#define MX51_DMA_REQ_SDHC4 41
#define MX51_DMA_REQ_SLIM_B_TX 42
#define MX51_DMA_REQ_UART3_RX 43
#define MX51_DMA_REQ_UART3_TX 44
#define MX51_DMA_REQ_SPDIF 45
#define MX51_DMA_REQ_SSI3_RX1 46
#define MX51_DMA_REQ_SSI3_TX1 47
/* /*
* Interrupt numbers * Interrupt numbers
...@@ -435,11 +427,11 @@ ...@@ -435,11 +427,11 @@
#define MX51_CHIP_REV_3_1 0x31 #define MX51_CHIP_REV_3_1 0x31
#define MX51_CHIP_REV_3_2 0x32 #define MX51_CHIP_REV_3_2 0x32
/* Mandatory defines used globally */
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx51_revision(void); extern int mx51_revision(void);
#endif #endif
#endif /* __ASM_ARCH_MXC_MX51_H__ */ /* tape-out 1 defines */
#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
#endif /* ifndef __MACH_MX51_H__ */
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