Commit 5ada755d authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Vinod Koul

dt-bindings: phy: convert HDMI PHY binding to YAML schema

Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20201225075258.33352-6-chunfeng.yun@mediatek.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 67038ec1
...@@ -53,23 +53,7 @@ Required properties: ...@@ -53,23 +53,7 @@ Required properties:
HDMI PHY HDMI PHY
======== ========
See phy/mediatek,hdmi-phy.yaml
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
output and drives the HDMI pads.
Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"
- clock-output-names: must be "hdmitx_dig_cts" on mt8173
- #phy-cells: must be <0>
- #clock-cells: must be <0>
Optional properties:
- mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
- mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
Example: Example:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (c) 2020 MediaTek
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
maintainers:
- Chun-Kuang Hu <chunkuang.hu@kernel.org>
- Philipp Zabel <p.zabel@pengutronix.de>
- Chunfeng Yun <chunfeng.yun@mediatek.com>
description: |
The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
output and drives the HDMI pads.
properties:
$nodename:
pattern: "^hdmi-phy@[0-9a-f]+$"
compatible:
enum:
- mediatek,mt2701-hdmi-phy
- mediatek,mt7623-hdmi-phy
- mediatek,mt8173-hdmi-phy
reg:
maxItems: 1
clocks:
items:
- description: PLL reference clock
clock-names:
items:
- const: pll_ref
clock-output-names:
items:
- const: hdmitx_dig_cts
"#phy-cells":
const: 0
"#clock-cells":
const: 0
mediatek,ibias:
description:
TX DRV bias current for < 1.65Gbps
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
default: 0xa
mediatek,ibias_up:
description:
TX DRV bias current for >= 1.65Gbps
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
default: 0x1c
required:
- compatible
- reg
- clocks
- clock-names
- clock-output-names
- "#phy-cells"
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
hdmi_phy: hdmi-phy@10209100 {
compatible = "mediatek,mt8173-hdmi-phy";
reg = <0x10209100 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
mediatek,ibias = <0xa>;
mediatek,ibias_up = <0x1c>;
#clock-cells = <0>;
#phy-cells = <0>;
};
...
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