Commit 5b61d4a5 authored by Christopher Covington's avatar Christopher Covington Committed by Russell King

ARM: 7948/1: hw_breakpoint: Add ARMv8 support

Add the trivial support necessary to get hardware breakpoints
working for GDB on ARMv8 simulators running in AArch32 mode.
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarChristopher Covington <cov@codeaurora.org>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 889f172d
...@@ -51,6 +51,7 @@ static inline void decode_ctrl_reg(u32 reg, ...@@ -51,6 +51,7 @@ static inline void decode_ctrl_reg(u32 reg,
#define ARM_DEBUG_ARCH_V7_ECP14 3 #define ARM_DEBUG_ARCH_V7_ECP14 3
#define ARM_DEBUG_ARCH_V7_MM 4 #define ARM_DEBUG_ARCH_V7_MM 4
#define ARM_DEBUG_ARCH_V7_1 5 #define ARM_DEBUG_ARCH_V7_1 5
#define ARM_DEBUG_ARCH_V8 6
/* Breakpoint */ /* Breakpoint */
#define ARM_BREAKPOINT_EXECUTE 0 #define ARM_BREAKPOINT_EXECUTE 0
......
...@@ -167,7 +167,7 @@ static int debug_arch_supported(void) ...@@ -167,7 +167,7 @@ static int debug_arch_supported(void)
/* Can we determine the watchpoint access type from the fsr? */ /* Can we determine the watchpoint access type from the fsr? */
static int debug_exception_updates_fsr(void) static int debug_exception_updates_fsr(void)
{ {
return 0; return get_debug_arch() >= ARM_DEBUG_ARCH_V8;
} }
/* Determine number of WRP registers available. */ /* Determine number of WRP registers available. */
...@@ -257,6 +257,7 @@ static int enable_monitor_mode(void) ...@@ -257,6 +257,7 @@ static int enable_monitor_mode(void)
break; break;
case ARM_DEBUG_ARCH_V7_ECP14: case ARM_DEBUG_ARCH_V7_ECP14:
case ARM_DEBUG_ARCH_V7_1: case ARM_DEBUG_ARCH_V7_1:
case ARM_DEBUG_ARCH_V8:
ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN));
isb(); isb();
break; break;
......
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