Skip to content

L
linux
Commit 5d0e6922 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
Browse files
Options

clk: qcom: gcc-sm6375: switch to parent_hws 

Change several entries of parent_data to use parent_hws instead, which
results in slightly more ovbious code.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230103145515.1164020-12-dmitry.baryshkov@linaro.org
parent 76ffb192
Hide whitespace changes
Inline Side-by-side
Showing with 126 additions and 126 deletions
drivers/clk/qcom/gcc-sm6375.c
View file @ 5d0e6922
......@@ -1766,8 +1766,8 @@ static struct clk_branch gcc_camss_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1784,8 +1784,8 @@ static struct clk_branch gcc_camss_cci_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_cci_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_cci_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1802,8 +1802,8 @@ static struct clk_branch gcc_camss_cci_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cci_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_cci_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_cci_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1820,8 +1820,8 @@ static struct clk_branch gcc_camss_cphy_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1838,8 +1838,8 @@ static struct clk_branch gcc_camss_cphy_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1856,8 +1856,8 @@ static struct clk_branch gcc_camss_cphy_2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1874,8 +1874,8 @@ static struct clk_branch gcc_camss_cphy_3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_cphy_3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1892,8 +1892,8 @@ static struct clk_branch gcc_camss_csi0phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi0phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi0phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi0phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1910,8 +1910,8 @@ static struct clk_branch gcc_camss_csi1phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi1phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi1phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi1phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1928,8 +1928,8 @@ static struct clk_branch gcc_camss_csi2phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi2phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi2phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi2phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1946,8 +1946,8 @@ static struct clk_branch gcc_camss_csi3phytimer_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_csi3phytimer_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_csi3phytimer_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1964,8 +1964,8 @@ static struct clk_branch gcc_camss_mclk0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -1982,8 +1982,8 @@ static struct clk_branch gcc_camss_mclk1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2000,8 +2000,8 @@ static struct clk_branch gcc_camss_mclk2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2018,8 +2018,8 @@ static struct clk_branch gcc_camss_mclk3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2036,8 +2036,8 @@ static struct clk_branch gcc_camss_mclk4_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_mclk4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_mclk4_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2067,8 +2067,8 @@ static struct clk_branch gcc_camss_ope_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_ope_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_ope_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2085,8 +2085,8 @@ static struct clk_branch gcc_camss_ope_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_ope_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_ope_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_ope_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2116,8 +2116,8 @@ static struct clk_branch gcc_camss_tfe_0_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2134,8 +2134,8 @@ static struct clk_branch gcc_camss_tfe_0_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2152,8 +2152,8 @@ static struct clk_branch gcc_camss_tfe_0_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_0_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_0_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_0_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2170,8 +2170,8 @@ static struct clk_branch gcc_camss_tfe_1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2188,8 +2188,8 @@ static struct clk_branch gcc_camss_tfe_1_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2206,8 +2206,8 @@ static struct clk_branch gcc_camss_tfe_1_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_1_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_1_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_1_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2224,8 +2224,8 @@ static struct clk_branch gcc_camss_tfe_2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2242,8 +2242,8 @@ static struct clk_branch gcc_camss_tfe_2_cphy_rx_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_cphy_rx_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_cphy_rx_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2260,8 +2260,8 @@ static struct clk_branch gcc_camss_tfe_2_csid_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_tfe_2_csid_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_tfe_2_csid_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_tfe_2_csid_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2278,8 +2278,8 @@ static struct clk_branch gcc_camss_top_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_camss_top_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_camss_top_ahb_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_camss_top_ahb_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2298,8 +2298,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2344,8 +2344,8 @@ static struct clk_branch gcc_disp_gpll0_div_clk_src = {
.enable_mask = BIT(20),
.hw.init = &(struct clk_init_data){
.name = "gcc_disp_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_disp_gpll0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_disp_gpll0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2407,8 +2407,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2425,8 +2425,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2443,8 +2443,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_gp3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2476,8 +2476,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2493,8 +2493,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){
.hw = &gpll0_out_even.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2554,8 +2554,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_pdm2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2716,8 +2716,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2734,8 +2734,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2752,8 +2752,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2770,8 +2770,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2788,8 +2788,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2806,8 +2806,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2850,8 +2850,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2868,8 +2868,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2886,8 +2886,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2904,8 +2904,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2922,8 +2922,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -2940,8 +2940,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3031,8 +3031,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc1_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3051,8 +3051,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc1_ice_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc1_ice_core_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3082,8 +3082,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3102,8 +3102,8 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_cpuss_ahb_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
......@@ -3120,8 +3120,8 @@ static struct clk_branch gcc_sys_noc_ufs_phy_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3140,8 +3140,8 @@ static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_sys_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3175,8 +3175,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3195,8 +3195,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3215,8 +3215,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3261,8 +3261,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3279,8 +3279,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3297,8 +3297,8 @@ static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3367,8 +3367,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3487,8 +3487,8 @@ static struct clk_branch gcc_video_vcodec0_sys_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_vcodec0_sys_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_video_venus_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......@@ -3505,8 +3505,8 @@ static struct clk_branch gcc_video_venus_ctl_clk = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "gcc_video_venus_ctl_clk",
.parent_data = &(const struct clk_parent_data){
.hw = &gcc_video_venus_clk_src.clkr.hw,
.parent_hws = (const struct clk_hw*[]) {
&gcc_video_venus_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7