Commit 5df884d4 authored by Andrey Smirnov's avatar Andrey Smirnov Committed by Greg Kroah-Hartman

tty: serial: fsl_lpuart: Fix lpuart_flush_buffer()

Fix incorrect read-modify-write sequence in lpuart_flush_buffer() that
was reading from UARTPFIFO and writing to UARTCFIFO instead of
operating solely on the latter.

Fixes: 9bc19af9 ("tty: serial: fsl_lpuart: Flush HW FIFOs in .flush_buffer")
Signed-off-by: default avatarAndrey Smirnov <andrew.smirnov@gmail.com>
Reported-by: default avatarVivien Didelot <vivien.didelot@gmail.com>
Tested-by: default avatarVivien Didelot <vivien.didelot@gmail.com>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Jiri Slaby <jslaby@suse.com>
Link: https://lore.kernel.org/r/20191004215537.5308-1-andrew.smirnov@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 47934ef7
...@@ -548,7 +548,7 @@ static void lpuart_flush_buffer(struct uart_port *port) ...@@ -548,7 +548,7 @@ static void lpuart_flush_buffer(struct uart_port *port)
val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
lpuart32_write(&sport->port, val, UARTFIFO); lpuart32_write(&sport->port, val, UARTFIFO);
} else { } else {
val = readb(sport->port.membase + UARTPFIFO); val = readb(sport->port.membase + UARTCFIFO);
val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
writeb(val, sport->port.membase + UARTCFIFO); writeb(val, sport->port.membase + UARTCFIFO);
} }
......
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