[ARM PATCH] 1863/2: definitions and mapping for the Intel PXA27x internal registers

Patch from Nicolas Pitre

This reworks PXA register mapping to accommodate the extra registers
of the PXA27x chips (aka Bulverde).

arch/arm/mach-pxa/generic.c

@@ -126,16 +126,21 @@ void pxa_gpio_mode(int gpio_mode)
 EXPORT_SYMBOL(pxa_gpio_mode);
 
 /*
- * Note that 0xfffe0000-0xffffffff is reserved for the vector table and
- * cache flush area.
+ * Intel PXA2xx internal register mapping.
+ *
+ * Note 1: not all PXA2xx variants implement all those addresses.
+ *
+ * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
+ *         and cache flush area.
  */
 static struct map_desc standard_io_desc[] __initdata = {
  /* virtual     physical    length      type */
-  { 0xf6000000, 0x20000000, 0x01000000, MT_DEVICE }, /* PCMCIA0 IO */
-  { 0xf7000000, 0x30000000, 0x01000000, MT_DEVICE }, /* PCMCIA1 IO */
-  { 0xf8000000, 0x40000000, 0x01400000, MT_DEVICE }, /* Devs */
-  { 0xfa000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
-  { 0xfc000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
+  { 0xf2000000, 0x40000000, 0x01800000, MT_DEVICE }, /* Devs */
+  { 0xf4000000, 0x44000000, 0x00100000, MT_DEVICE }, /* LCD */
+  { 0xf6000000, 0x48000000, 0x00100000, MT_DEVICE }, /* Mem Ctl */
+  { 0xf8000000, 0x4c000000, 0x00100000, MT_DEVICE }, /* USB host */
+  { 0xfa000000, 0x50000000, 0x00100000, MT_DEVICE }, /* Camera */
+  { 0xfe000000, 0x58000000, 0x00100000, MT_DEVICE }, /* IMem ctl */
   { 0xff000000, 0x00000000, 0x00100000, MT_DEVICE }  /* UNCACHED_PHYS_0 */
 };
 

include/asm-arm/arch-pxa/hardware.h

@@ -16,15 +16,6 @@
 #include <asm/mach-types.h>
 
 
-/*
- * These are statically mapped PCMCIA IO space for designs using it as a
- * generic IO bus, typically with ISA parts, hardwired IDE interfaces, etc.
- * The actual PCMCIA code is mapping required IO region at run time.
- */
-#define PCMCIA_IO_0_BASE	0xf6000000
-#define PCMCIA_IO_1_BASE	0xf7000000
-
-
 /*
  * We requires absolute addresses.
  */
@@ -38,15 +29,21 @@
 #define UNCACHED_ADDR		UNCACHED_PHYS_0
 
 /*
- * Intel PXA internal I/O mappings:
+ * Intel PXA2xx internal register mapping:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
+ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
+ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
  *
- * 0x40000000 - 0x41ffffff <--> 0xf8000000 - 0xf9ffffff
- * 0x44000000 - 0x45ffffff <--> 0xfa000000 - 0xfbffffff
- * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
+ * Note that not all PXA2xx chips implement all those addresses, and the
+ * kernel only maps the minimum needed range of this mapping.
  */
-
-#define io_p2v(x)	( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
-#define io_v2p( x )	( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
+#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
+#define io_v2p(x) (0x40000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
 
 #ifndef __ASSEMBLY__