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Commit 5fa2481c authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update event list for Alderlake 

Update JSON event list for Alderlake to perf.

It is a hybrid event list for both Atom and Core.

Based on JSON list v1.11:

https://download.01.org/perfmon/ADL/Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220607092749.1976878-1-zhengjun.xing@linux.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 8147f79e
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Showing with 440 additions and 96 deletions
tools/perf/pmu-events/arch/x86/alderlake/floating-point.json
View file @ 5fa2481c
......@@ -7,6 +7,7 @@
"EventName": "MACHINE_CLEARS.FP_ASSIST",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_atom"
},
......@@ -23,7 +24,7 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "TBD",
"BriefDescription": "ARITH.FPDIV_ACTIVE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
......@@ -31,6 +32,7 @@
"EventName": "ARITH.FPDIV_ACTIVE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
......@@ -42,50 +44,55 @@
"EventName": "ASSISTS.FP",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.SSE_AVX_MIX",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb3",
"EventName": "FP_ARITH_DISPATCHED.PORT_5",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......
tools/perf/pmu-events/arch/x86/alderlake/frontend.json
View file @ 5fa2481c
......@@ -7,6 +7,7 @@
"EventName": "BACLEARS.ANY",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_atom"
},
......@@ -18,6 +19,7 @@
"EventName": "ICACHE.ACCESSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_atom"
},
......@@ -29,6 +31,7 @@
"EventName": "ICACHE.MISSES",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
......@@ -40,6 +43,7 @@
"EventName": "DECODE.LCP",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
......@@ -51,6 +55,7 @@
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -294,6 +299,21 @@
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
"EventName": "FRONTEND_RETIRED.MS_FLOWS",
"MSRIndex": "0x3F7",
"MSRValue": "0x8",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
"CollectPEBSRecord": "2",
......@@ -310,7 +330,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc6",
......@@ -332,6 +352,7 @@
"EventName": "ICACHE_DATA.STALLS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "500009",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -343,6 +364,7 @@
"EventName": "ICACHE_TAG.STALLS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -355,6 +377,7 @@
"EventName": "IDQ.DSB_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
......@@ -367,6 +390,7 @@
"EventName": "IDQ.DSB_CYCLES_OK",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
......@@ -378,6 +402,7 @@
"EventName": "IDQ.DSB_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
......@@ -390,6 +415,7 @@
"EventName": "IDQ.MITE_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -402,6 +428,7 @@
"EventName": "IDQ.MITE_CYCLES_OK",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -413,6 +440,7 @@
"EventName": "IDQ.MITE_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -425,6 +453,7 @@
"EventName": "IDQ.MS_CYCLES_ANY",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -438,6 +467,7 @@
"EventName": "IDQ.MS_SWITCHES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -449,6 +479,7 @@
"EventName": "IDQ.MS_UOPS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -460,6 +491,7 @@
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
......@@ -472,6 +504,7 @@
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
},
......@@ -485,6 +518,7 @@
"Invert": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
}
......
tools/perf/pmu-events/arch/x86/alderlake/memory.json
View file @ 5fa2481c
[
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ANY_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xff",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
"Counter": "0,1,2,3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.L1_BOUND_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xf4",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases when load subsequently retires when load subsequently retires.",
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.OTHER_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xc0",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk when load subsequently retires.",
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.PGWALK_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0xa0",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match when load subsequently retires.",
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.ST_ADDR_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x84",
"Unit": "cpu_atom"
},
......@@ -58,12 +67,13 @@
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "20003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
......@@ -74,7 +84,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
......@@ -92,6 +102,7 @@
"EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x6",
"Unit": "cpu_core"
},
......@@ -103,6 +114,7 @@
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -115,6 +127,7 @@
"EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -127,11 +140,12 @@
"EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x3",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "5",
......@@ -139,11 +153,12 @@
"EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x5",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "9",
......@@ -151,6 +166,7 @@
"EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x9",
"Unit": "cpu_core"
},
......@@ -283,7 +299,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "Retired instructions with at least 1 store uop. This PEBS event is the trigger for stores sampled by the PEBS Store Facility.",
"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
"CollectPEBSRecord": "2",
"Data_LA": "1",
"EventCode": "0xcd",
......@@ -295,7 +311,7 @@
},
{
"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
......@@ -306,7 +322,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.L3_MISS",
"MSRIndex": "0x1a6,0x1a7",
......
tools/perf/pmu-events/arch/x86/alderlake/other.json
View file @ 5fa2481c
[
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -12,7 +12,7 @@
},
{
"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -23,7 +23,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5",
"EventCode": "0xB7",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -33,74 +33,68 @@
"Unit": "cpu_atom"
},
{
"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.ANY",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"UMask": "0x1f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Count all other microcode assist beyond FP, AVX_TILE_MIX and A/D assists (counted by their own sub-events). This includes assists at uop writeback like AVX* load/store (non-FP) assists, Null Assist in SNC (due to lack of FP precision format convert with FMA3x3 uarch) or assists generated by ROB (like assists to due to Missprediction for FSW register - fixed in SNC)",
"BriefDescription": "ASSISTS.HARDWARE",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.HARDWARE",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "ASSISTS.PAGE_FAULT",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc1",
"EventName": "ASSISTS.PAGE_FAULT",
"PEBScounters": "0,1,2,3,4,5,6,7",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "CORE_POWER.LICENSE_1",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_1",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "CORE_POWER.LICENSE_2",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_2",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "CORE_POWER.LICENSE_3",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0x28",
"EventName": "CORE_POWER.LICENSE_3",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts demand data reads that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -111,7 +105,7 @@
},
{
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -122,7 +116,7 @@
},
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"Counter": "0,1,2,3",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x2A,0x2B",
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
......@@ -132,7 +126,7 @@
"Unit": "cpu_core"
},
{
"BriefDescription": "TBD",
"BriefDescription": "XQ.FULL_CYCLES",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"CounterMask": "1",
......@@ -140,6 +134,7 @@
"EventName": "XQ.FULL_CYCLES",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x1",
"Unit": "cpu_core"
}
......
tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json
View file @ 5fa2481c
......@@ -7,6 +7,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "200003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
......@@ -18,17 +19,19 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "2000003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss when load subsequently retires.",
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5",
"EventCode": "0x05",
"EventName": "LD_HEAD.DTLB_MISS_AT_RET",
"PEBScounters": "0,1,2,3,4,5",
"SampleAfterValue": "1000003",
"Speculative": "1",
"UMask": "0x90",
"Unit": "cpu_atom"
},
......@@ -40,6 +43,7 @@
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -52,6 +56,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
......@@ -63,6 +68,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
......@@ -74,6 +80,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
......@@ -85,6 +92,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -96,6 +104,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -107,6 +116,7 @@
"EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
......@@ -118,6 +128,7 @@
"EventName": "DTLB_STORE_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -130,6 +141,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
......@@ -141,6 +153,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
......@@ -152,6 +165,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x8",
"Unit": "cpu_core"
},
......@@ -163,6 +177,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -174,6 +189,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -185,6 +201,7 @@
"EventName": "DTLB_STORE_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
......@@ -196,6 +213,7 @@
"EventName": "ITLB_MISSES.STLB_HIT",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x20",
"Unit": "cpu_core"
},
......@@ -208,6 +226,7 @@
"EventName": "ITLB_MISSES.WALK_ACTIVE",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
},
......@@ -219,6 +238,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0xe",
"Unit": "cpu_core"
},
......@@ -230,6 +250,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4",
"Unit": "cpu_core"
},
......@@ -241,6 +262,7 @@
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x2",
"Unit": "cpu_core"
},
......@@ -252,6 +274,7 @@
"EventName": "ITLB_MISSES.WALK_PENDING",
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x10",
"Unit": "cpu_core"
}
......
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