Commit 5fdc760e authored by Russell King's avatar Russell King

[ARM] Add read_cpuid() to aid reading CPU ID registers.

parent a6212839
......@@ -219,9 +219,7 @@ static inline void dump_cache(const char *prefix, unsigned int cache)
static void __init dump_cpu_info(void)
{
unsigned int info;
asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (info));
unsigned int info = read_cpuid(CPUID_CACHETYPE);
if (info != processor_id) {
printk("CPU: D %s cache\n", cache_types[CACHE_TYPE(info)]);
......@@ -803,9 +801,7 @@ static int c_show(struct seq_file *m, void *v)
seq_printf(m, "CPU revision\t: %d\n", processor_id & 15);
{
unsigned int cache_info;
asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (cache_info));
unsigned int cache_info = read_cpuid(CPUID_CACHETYPE);
if (cache_info != processor_id) {
seq_printf(m, "Cache type\t: %s\n"
"Cache clean\t: %s\n"
......
......@@ -21,6 +21,7 @@
#include <linux/oprofile.h>
#include <linux/interrupt.h>
#include <asm/arch/irqs.h>
#include <asm/system.h>
#include "op_counter.h"
#include "op_arm_model.h"
......@@ -399,8 +400,7 @@ static int xscale_detect_pmu(void)
int ret = 0;
u32 id;
__asm__ __volatile__ ("mrc p15, 0, %0, c0, c0, 0" : "=r" (id));
id = (id >> 13) & 0x7;
id = (read_cpuid(CPUID_ID) >> 13) & 0x7;
switch (id) {
case 1:
......
......@@ -42,6 +42,19 @@
#define CR_XP (1 << 23) /* Extended page tables */
#define CR_VE (1 << 24) /* Vectored interrupts */
#define CPUID_ID 0
#define CPUID_CACHETYPE 1
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#define read_cpuid(reg) \
({ \
unsigned int __val; \
asm("mrc p15, 0, %0, c0, c0, " #reg \
: "=r" (__val)); \
__val; \
})
/*
* This is used to ensure the compiler did actually allocate the register we
* asked it for some inline assembly sequences. Apparently we can't trust
......
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