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Commit 60409e5c authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] JMR3927 update 

This updates support for the JMR3927 eval board.
parent 4ee45a31
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arch/mips/defconfig-jmr3927 0 → 100644
View file @ 60409e5c
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
CONFIG_TOSHIBA_JMR3927=y
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_NEW_PCI=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_FB=y
CONFIG_TOSHIBA_BOARDS=y
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
CONFIG_CPU_TX39XX=y
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
CONFIG_RTC_DS1742=y
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_PCI=y
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
# CONFIG_BINFMT_IRIX is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_PCI is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
#
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ISDN subsystem
#
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
# CONFIG_VT_CONSOLE is not set
CONFIG_HW_CONSOLE=y
CONFIG_SERIAL_NONSTANDARD=y
# CONFIG_COMPUTONE is not set
# CONFIG_ROCKETPORT is not set
# CONFIG_CYCLADES is not set
# CONFIG_DIGIEPCA is not set
# CONFIG_DIGI is not set
# CONFIG_MOXA_INTELLIO is not set
# CONFIG_MOXA_SMARTIO is not set
# CONFIG_SYNCLINK is not set
# CONFIG_SYNCLINKMP is not set
# CONFIG_N_HDLC is not set
# CONFIG_RISCOM8 is not set
# CONFIG_SPECIALIX is not set
# CONFIG_SX is not set
# CONFIG_RIO is not set
# CONFIG_STALDRV is not set
# CONFIG_SERIAL_TX3912 is not set
CONFIG_TXX927_SERIAL=y
CONFIG_TXX927_SERIAL_CONSOLE=y
# CONFIG_SERIAL_TXX9 is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
# CONFIG_UNIX98_PTYS is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Graphics support
#
# CONFIG_FB_CIRRUS is not set
# CONFIG_FB_PM2 is not set
# CONFIG_FB_CYBER2000 is not set
# CONFIG_FB_IMSTT is not set
# CONFIG_FB_RIVA is not set
# CONFIG_FB_MATROX is not set
# CONFIG_FB_RADEON is not set
# CONFIG_FB_ATY128 is not set
# CONFIG_FB_ATY is not set
# CONFIG_FB_SIS is not set
# CONFIG_FB_NEOMAGIC is not set
# CONFIG_FB_3DFX is not set
# CONFIG_FB_VOODOO1 is not set
# CONFIG_FB_TRIDENT is not set
# CONFIG_FB_PM3 is not set
# CONFIG_FB_E1356 is not set
# CONFIG_FB_VIRTUAL is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE is not set
#
# Logo configuration
#
# CONFIG_LOGO is not set
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
arch/mips/jmr3927/common/Makefile 0 → 100644
View file @ 60409e5c
#
# Makefile for the common code of TOSHIBA JMR-TX3927 board
#
obj-y += prom.o puts.o rtc_ds1742.o
arch/mips/jmr3927/common/prom.c 0 → 100644
View file @ 60409e5c
/*
* BRIEF MODULE DESCRIPTION
* PROM library initialisation code, assuming a version of
* pmon is the boot code.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* Based on arch/mips/au1000/common/prom.c
*
* This file was derived from Carsten Langgaard's
* arch/mips/mips-boards/xx files.
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
/* #define DEBUG_CMDLINE */
char arcs_cmdline[CL_SIZE];
extern int prom_argc;
extern char **prom_argv, **prom_envp;
typedef struct
{
char *name;
/* char *val; */
}t_env_var;
char * __init prom_getcmdline(void)
{
return &(arcs_cmdline[0]);
}
void __init prom_init_cmdline(void)
{
char *cp;
int actr;
actr = 1; /* Always ignore argv[0] */
cp = &(arcs_cmdline[0]);
while(actr < prom_argc) {
strcpy(cp, prom_argv[actr]);
cp += strlen(prom_argv[actr]);
*cp++ = ' ';
actr++;
}
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
--cp;
*cp = '\0';
}
int __init page_is_ram(unsigned long pagenr)
{
return 1;
}
void prom_free_prom_memory (void)
{
}
arch/mips/jmr3927/common/puts.c 0 → 100644
View file @ 60409e5c
/*
*
* BRIEF MODULE DESCRIPTION
* Low level uart routines to directly access a TX[34]927 SIO.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com or source@mvista.com
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* Based on arch/mips/au1000/common/puts.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h>
#define TIMEOUT 0xffffff
#define SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif
void
putch(const unsigned char c)
{
int i = 0;
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = c;
return;
}
unsigned char getch(void)
{
int i = 0;
int dicr;
char c;
/* diable RX int. */
dicr = tx3927_sioptr(1)->dicr;
tx3927_sioptr(1)->dicr = 0;
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (tx3927_sioptr(1)->disr & TXx927_SIDISR_UVALID)
;
c = tx3927_sioptr(1)->rfifo;
/* clear RX int. status */
tx3927_sioptr(1)->disr &= ~TXx927_SIDISR_RDIS;
/* enable RX int. */
tx3927_sioptr(1)->dicr = dicr;
return c;
}
void
do_jmr3927_led_set(char n)
{
/* and with current leds */
jmr3927_led_and_set(n);
}
void
puts(unsigned char *cp)
{
int i = 0;
while (*cp) {
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = *cp++;
}
putch('\r');
putch('\n');
}
void
fputs(unsigned char *cp)
{
int i = 0;
while (*cp) {
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(1)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(1)->tfifo = *cp++;
}
}
void
put64(uint64_t ul)
{
int cnt;
unsigned ch;
cnt = 16; /* 16 nibbles in a 64 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
void
put32(unsigned u)
{
int cnt;
unsigned ch;
cnt = 8; /* 8 nibbles in a 32 bit long */
putch('0');
putch('x');
do {
cnt--;
ch = (unsigned char)(u >> cnt * 4) & 0x0F;
putch(digits[ch]);
} while (cnt > 0);
}
arch/mips/jmr3927/common/rtc_ds1742.c 0 → 100644
View file @ 60409e5c
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* arch/mips/jmr3927/common/rtc_ds1742.c
* Based on arch/mips/ddb5xxx/common/rtc_ds1386.c
* low-level RTC hookups for s for Dallas 1742 chip.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/*
* This file exports a function, rtc_ds1386_init(), which expects an
* uncached base address as the argument. It will set the two function
* pointers expected by the MIPS generic timer code.
*/
#include <linux/bcd.h>
#include <linux/types.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <asm/time.h>
#include <asm/addrspace.h>
#include <asm/jmr3927/ds1742rtc.h>
#include <asm/debug.h>
#define EPOCH 2000
static unsigned long rtc_base;
static unsigned long
rtc_ds1742_get_time(void)
{
unsigned int year, month, day, hour, minute, second;
unsigned int century;
CMOS_WRITE(RTC_READ, RTC_CONTROL);
second = BCD2BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
minute = BCD2BIN(CMOS_READ(RTC_MINUTES));
hour = BCD2BIN(CMOS_READ(RTC_HOURS));
day = BCD2BIN(CMOS_READ(RTC_DATE));
month = BCD2BIN(CMOS_READ(RTC_MONTH));
year = BCD2BIN(CMOS_READ(RTC_YEAR));
century = BCD2BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK);
CMOS_WRITE(0, RTC_CONTROL);
year += century * 100;
return mktime(year, month, day, hour, minute, second);
}
extern void to_tm(unsigned long tim, struct rtc_time * tm);
static int
rtc_ds1742_set_time(unsigned long t)
{
struct rtc_time tm;
u8 year, month, day, hour, minute, second;
u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second;
int cmos_century;
CMOS_WRITE(RTC_READ, RTC_CONTROL);
cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
cmos_minute = (u8)CMOS_READ(RTC_MINUTES);
cmos_hour = (u8)CMOS_READ(RTC_HOURS);
cmos_day = (u8)CMOS_READ(RTC_DATE);
cmos_month = (u8)CMOS_READ(RTC_MONTH);
cmos_year = (u8)CMOS_READ(RTC_YEAR);
cmos_century = CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK;
CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
/* convert */
to_tm(t, &tm);
/* check each field one by one */
year = BIN2BCD(tm.tm_year - EPOCH);
if (year != cmos_year) {
CMOS_WRITE(year,RTC_YEAR);
}
month = BIN2BCD(tm.tm_mon);
if (month != (cmos_month & 0x1f)) {
CMOS_WRITE((month & 0x1f) | (cmos_month & ~0x1f),RTC_MONTH);
}
day = BIN2BCD(tm.tm_mday);
if (day != cmos_day) {
CMOS_WRITE(day, RTC_DATE);
}
if (cmos_hour & 0x40) {
/* 12 hour format */
hour = 0x40;
if (tm.tm_hour > 12) {
hour |= 0x20 | (BIN2BCD(hour-12) & 0x1f);
} else {
hour |= BIN2BCD(tm.tm_hour);
}
} else {
/* 24 hour format */
hour = BIN2BCD(tm.tm_hour) & 0x3f;
}
if (hour != cmos_hour) CMOS_WRITE(hour, RTC_HOURS);
minute = BIN2BCD(tm.tm_min);
if (minute != cmos_minute) {
CMOS_WRITE(minute, RTC_MINUTES);
}
second = BIN2BCD(tm.tm_sec);
if (second != cmos_second) {
CMOS_WRITE(second & RTC_SECONDS_MASK,RTC_SECONDS);
}
/* RTC_CENTURY and RTC_CONTROL share same address... */
CMOS_WRITE(cmos_century, RTC_CONTROL);
return 0;
}
void
rtc_ds1742_init(unsigned long base)
{
u8 cmos_second;
/* remember the base */
rtc_base = base;
db_assert((rtc_base & 0xe0000000) == KSEG1);
/* set the function pointers */
rtc_get_time = rtc_ds1742_get_time;
rtc_set_time = rtc_ds1742_set_time;
/* clear oscillator stop bit */
CMOS_WRITE(RTC_READ, RTC_CONTROL);
cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
CMOS_WRITE(RTC_WRITE, RTC_CONTROL);
CMOS_WRITE(cmos_second, RTC_SECONDS); /* clear msb */
CMOS_WRITE(0, RTC_CONTROL);
}
arch/mips/jmr3927/rbhma3100/Makefile 0 → 100644
View file @ 60409e5c
#
# Makefile for TOSHIBA JMR-TX3927 board
#
obj-y += init.o int-handler.o irq.o setup.o rtc.o
obj-$(CONFIG_RUNTIME_DEBUG) += debug.o
obj-$(CONFIG_KGDB) += kgdb_io.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/jmr3927/rbhma3100/init.c 0 → 100644
View file @ 60409e5c
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* arch/mips/jmr3927/common/init.c
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
***********************************************************************
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/jmr3927/jmr3927.h>
int prom_argc;
char **prom_argv, **prom_envp;
extern void __init prom_init_cmdline(void);
extern char *prom_getenv(char *envname);
unsigned long mips_nofpu = 0;
const char *get_system_type(void)
{
return "Toshiba"
#ifdef CONFIG_TOSHIBA_JMR3927
" JMR_TX3927"
#endif
;
}
extern void puts(unsigned char *cp);
int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
{
#ifdef CONFIG_TOSHIBA_JMR3927
/* CCFG */
if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
puts("Warning: TX3927 TLB off\n");
#endif
prom_argc = argc;
prom_argv = argv;
prom_envp = envp;
mips_machgroup = MACH_GROUP_TOSHIBA;
#ifdef CONFIG_TOSHIBA_JMR3927
mips_machtype = MACH_TOSHIBA_JMR3927;
#endif
prom_init_cmdline();
add_memory_region(0, JMR3927_SDRAM_SIZE, BOOT_MEM_RAM);
return 0;
}
arch/mips/jmr3927/rbhma3100/int-handler.S 0 → 100644
View file @ 60409e5c
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* Based on arch/mips/tsdb/kernel/int-handler.S
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/jmr3927/jmr3927.h>
/* A lot of complication here is taken away because:
*
* 1) We handle one interrupt and return, sitting in a loop
* and moving across all the pending IRQ bits in the cause
* register is _NOT_ the answer, the common case is one
* pending IRQ so optimize in that direction.
*
* 2) We need not check against bits in the status register
* IRQ mask, that would make this routine slow as hell.
*
* 3) Linux only thinks in terms of all IRQs on or all IRQs
* off, nothing in between like BSD spl() brain-damage.
*
*/
/* Flush write buffer (needed?)
* NOTE: TX39xx performs "non-blocking load", so explicitly use the target
* register of LBU to flush immediately.
*/
#define FLUSH_WB(tmp) \
la tmp, JMR3927_IOC_REV_ADDR; \
lbu tmp, (tmp); \
move tmp, zero;
.text
.set noreorder
.set noat
.align 5
NESTED(jmr3927_IRQ, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
jal jmr3927_irc_irqdispatch
move a0, sp
FLUSH_WB(t0)
j ret_from_irq
nop
END(jmr3927_IRQ)
arch/mips/jmr3927/rbhma3100/irq.c 0 → 100644
View file @ 60409e5c
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/irq.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/smp_lock.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/jmr3927/irq.h>
#include <asm/debug.h>
#include <asm/jmr3927/jmr3927.h>
#if JMR3927_IRQ_END > NR_IRQS
#error JMR3927_IRQ_END > NR_IRQS
#endif
struct tb_irq_space* tb_irq_spaces;
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
static int jmr3927_irq_base=-1;
#ifdef CONFIG_PCI
static int jmr3927_gen_iack(void)
{
/* generate ACK cycle */
#ifdef __BIG_ENDIAN
return (tx3927_pcicptr->iiadp >> 24) & 0xff;
#else
return tx3927_pcicptr->iiadp & 0xff;
#endif
}
#endif
extern asmlinkage void jmr3927_IRQ(void);
#define irc_dlevel 0
#define irc_elevel 1
static unsigned char irc_level[TX3927_NUM_IR] = {
5, 5, 5, 5, 5, 5, /* INT[5:0] */
7, 7, /* SIO */
5, 5, 5, 0, 0, /* DMA, PIO, PCI */
6, 6, 6 /* TMR */
};
static inline void mask_irq(unsigned int irq_nr)
{
struct tb_irq_space* sp;
for (sp = tb_irq_spaces; sp; sp = sp->next) {
if (sp->start_irqno <= irq_nr &&
irq_nr < sp->start_irqno + sp->nr_irqs) {
if (sp->mask_func)
sp->mask_func(irq_nr - sp->start_irqno,
sp->space_id);
break;
}
}
}
static inline void unmask_irq(unsigned int irq_nr)
{
struct tb_irq_space* sp;
for (sp = tb_irq_spaces; sp; sp = sp->next) {
if (sp->start_irqno <= irq_nr &&
irq_nr < sp->start_irqno + sp->nr_irqs) {
if (sp->unmask_func)
sp->unmask_func(irq_nr - sp->start_irqno,
sp->space_id);
break;
}
}
}
static void jmr3927_irq_disable(unsigned int irq_nr);
static void jmr3927_irq_enable(unsigned int irq_nr);
static unsigned int jmr3927_irq_startup(unsigned int irq)
{
jmr3927_irq_enable(irq);
return 0;
}
#define jmr3927_irq_shutdown jmr3927_irq_disable
static void jmr3927_irq_ack(unsigned int irq)
{
db_assert(jmr3927_irq_base != -1);
db_assert(irq >= jmr3927_irq_base);
db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
if (irq == JMR3927_IRQ_IRC_TMR0) {
jmr3927_tmrptr->tisr = 0; /* ack interrupt */
}
jmr3927_irq_disable(irq);
}
static void jmr3927_irq_end(unsigned int irq)
{
db_assert(jmr3927_irq_base != -1);
db_assert(irq >= jmr3927_irq_base);
db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
jmr3927_irq_enable(irq);
}
static void jmr3927_irq_disable(unsigned int irq_nr)
{
unsigned long flags;
db_assert(jmr3927_irq_base != -1);
db_assert(irq >= jmr3927_irq_base);
db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
local_irq_save(flags);
mask_irq(irq_nr);
local_irq_restore(flags);
}
static void jmr3927_irq_enable(unsigned int irq_nr)
{
unsigned long flags;
db_assert(jmr3927_irq_base != -1);
db_assert(irq >= jmr3927_irq_base);
db_assert(irq < jmr3927_irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC);
local_irq_save(flags);
unmask_irq(irq_nr);
local_irq_restore(flags);
}
/*
* CP0_STATUS is a thread's resource (saved/restored on context switch).
* So disable_irq/enable_irq MUST handle IOC/ISAC/IRC registers.
*/
static void mask_irq_isac(int irq_nr, int space_id)
{
/* 0: mask */
unsigned char imask =
jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
unsigned int bit = 1 << irq_nr;
jmr3927_isac_reg_out(imask & ~bit, JMR3927_ISAC_INTM_ADDR);
/* flush write buffer */
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_isac(int irq_nr, int space_id)
{
/* 0: mask */
unsigned char imask =
jmr3927_isac_reg_in(JMR3927_ISAC_INTM_ADDR);
unsigned int bit = 1 << irq_nr;
jmr3927_isac_reg_out(imask | bit, JMR3927_ISAC_INTM_ADDR);
/* flush write buffer */
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void mask_irq_ioc(int irq_nr, int space_id)
{
/* 0: mask */
unsigned char imask =
jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
unsigned int bit = 1 << irq_nr;
jmr3927_ioc_reg_out(imask & ~bit, JMR3927_IOC_INTM_ADDR);
/* flush write buffer */
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void unmask_irq_ioc(int irq_nr, int space_id)
{
/* 0: mask */
unsigned char imask =
jmr3927_ioc_reg_in(JMR3927_IOC_INTM_ADDR);
unsigned int bit = 1 << irq_nr;
jmr3927_ioc_reg_out(imask | bit, JMR3927_IOC_INTM_ADDR);
/* flush write buffer */
(void)jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR);
}
static void mask_irq_irc(int irq_nr, int space_id)
{
volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
if (irq_nr & 1)
*ilrp = (*ilrp & 0x00ff) | (irc_dlevel << 8);
else
*ilrp = (*ilrp & 0xff00) | irc_dlevel;
/* update IRCSR */
tx3927_ircptr->imr = 0;
tx3927_ircptr->imr = irc_elevel;
}
static void unmask_irq_irc(int irq_nr, int space_id)
{
volatile unsigned long *ilrp = &tx3927_ircptr->ilr[irq_nr / 2];
if (irq_nr & 1)
*ilrp = (*ilrp & 0x00ff) | (irc_level[irq_nr] << 8);
else
*ilrp = (*ilrp & 0xff00) | irc_level[irq_nr];
/* update IRCSR */
tx3927_ircptr->imr = 0;
tx3927_ircptr->imr = irc_elevel;
}
struct tb_irq_space jmr3927_isac_irqspace = {
.next = NULL,
.start_irqno = JMR3927_IRQ_ISAC,
nr_irqs : JMR3927_NR_IRQ_ISAC,
.mask_func = mask_irq_isac,
.unmask_func = unmask_irq_isac,
.name = "ISAC",
.space_id = 0,
can_share : 0
};
struct tb_irq_space jmr3927_ioc_irqspace = {
.next = NULL,
.start_irqno = JMR3927_IRQ_IOC,
nr_irqs : JMR3927_NR_IRQ_IOC,
.mask_func = mask_irq_ioc,
.unmask_func = unmask_irq_ioc,
.name = "IOC",
.space_id = 0,
can_share : 1
};
struct tb_irq_space jmr3927_irc_irqspace = {
.next = NULL,
.start_irqno = JMR3927_IRQ_IRC,
nr_irqs : JMR3927_NR_IRQ_IRC,
.mask_func = mask_irq_irc,
.unmask_func = unmask_irq_irc,
.name = "on-chip",
.space_id = 0,
can_share : 0
};
void jmr3927_spurious(struct pt_regs *regs)
{
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
tx_branch_likely_bug_fixup(regs);
#endif
printk(KERN_WARNING "spurious interrupt (cause 0x%lx, pc 0x%lx, ra 0x%lx).\n",
regs->cp0_cause, regs->cp0_epc, regs->regs[31]);
}
void jmr3927_irc_irqdispatch(struct pt_regs *regs)
{
int irq;
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
tx_branch_likely_bug_fixup(regs);
#endif
if ((regs->cp0_cause & CAUSEF_IP7) == 0) {
#if 0
jmr3927_spurious(regs);
#endif
return;
}
irq = (regs->cp0_cause >> CAUSEB_IP2) & 0x0f;
do_IRQ(irq + JMR3927_IRQ_IRC, regs);
}
static void jmr3927_ioc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned char istat = jmr3927_ioc_reg_in(JMR3927_IOC_INTS2_ADDR);
int i;
for (i = 0; i < JMR3927_NR_IRQ_IOC; i++) {
if (istat & (1 << i)) {
irq = JMR3927_IRQ_IOC + i;
do_IRQ(irq, regs);
}
}
}
static struct irqaction ioc_action = {
jmr3927_ioc_interrupt, 0, 0, "IOC", NULL, NULL,
};
static void jmr3927_isac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned char istat = jmr3927_isac_reg_in(JMR3927_ISAC_INTS2_ADDR);
int i;
for (i = 0; i < JMR3927_NR_IRQ_ISAC; i++) {
if (istat & (1 << i)) {
irq = JMR3927_IRQ_ISAC + i;
do_IRQ(irq, regs);
}
}
}
static struct irqaction isac_action = {
jmr3927_isac_interrupt, 0, 0, "ISAC", NULL, NULL,
};
static void jmr3927_isaerr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
{
printk(KERN_WARNING "ISA error interrupt (irq 0x%x).\n", irq);
}
static struct irqaction isaerr_action = {
jmr3927_isaerr_interrupt, 0, 0, "ISA error", NULL, NULL,
};
static void jmr3927_pcierr_interrupt(int irq, void * dev_id, struct pt_regs * regs)
{
printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
printk(KERN_WARNING "pcistat:%02x, lbstat:%04lx\n",
tx3927_pcicptr->pcistat, tx3927_pcicptr->lbstat);
}
static struct irqaction pcierr_action = {
jmr3927_pcierr_interrupt, 0, 0, "PCI error", NULL, NULL,
};
int jmr3927_ether1_irq = 0;
void jmr3927_irq_init(u32 irq_base);
void jmr3927_irq_setup(void)
{
/* look for io board's presence */
int have_isac = jmr3927_have_isac();
/* Now, interrupt control disabled, */
/* all IRC interrupts are masked, */
/* all IRC interrupt mode are Low Active. */
if (have_isac) {
/* ETHER1 (NE2000 compatible 10M-Ether) parameter setup */
/* temporary enable interrupt control */
tx3927_ircptr->cer = 1;
/* ETHER1 Int. Is High-Active. */
if (tx3927_ircptr->ssr & (1 << 0))
jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT0;
#if 0 /* INT3 may be asserted by ether0 (even after reboot...) */
else if (tx3927_ircptr->ssr & (1 << 3))
jmr3927_ether1_irq = JMR3927_IRQ_IRC_INT3;
#endif
/* disable interrupt control */
tx3927_ircptr->cer = 0;
/* Ether1: High Active */
if (jmr3927_ether1_irq) {
int ether1_irc = jmr3927_ether1_irq - JMR3927_IRQ_IRC;
tx3927_ircptr->cr[ether1_irc / 8] |=
TX3927_IRCR_HIGH << ((ether1_irc % 8) * 2);
}
}
/* mask all IOC interrupts */
jmr3927_ioc_reg_out(0, JMR3927_IOC_INTM_ADDR);
/* setup IOC interrupt mode (SOFT:High Active, Others:Low Active) */
jmr3927_ioc_reg_out(JMR3927_IOC_INTF_SOFT, JMR3927_IOC_INTP_ADDR);
if (have_isac) {
/* mask all ISAC interrupts */
jmr3927_isac_reg_out(0, JMR3927_ISAC_INTM_ADDR);
/* setup ISAC interrupt mode (ISAIRQ3,ISAIRQ5:Low Active ???) */
jmr3927_isac_reg_out(JMR3927_ISAC_INTF_IRQ3|JMR3927_ISAC_INTF_IRQ5, JMR3927_ISAC_INTP_ADDR);
}
/* clear PCI Soft interrupts */
jmr3927_ioc_reg_out(0, JMR3927_IOC_INTS1_ADDR);
/* clear PCI Reset interrupts */
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
/* enable interrupt control */
tx3927_ircptr->cer = TX3927_IRCER_ICE;
tx3927_ircptr->imr = irc_elevel;
jmr3927_irq_init(NR_ISA_IRQS);
set_except_vector(0, jmr3927_IRQ);
/* setup irq space */
add_tb_irq_space(&jmr3927_isac_irqspace);
add_tb_irq_space(&jmr3927_ioc_irqspace);
add_tb_irq_space(&jmr3927_irc_irqspace);
/* setup IOC interrupt 1 (PCI, MODEM) */
setup_irq(JMR3927_IRQ_IOCINT, &ioc_action);
if (have_isac) {
setup_irq(JMR3927_IRQ_ISACINT, &isac_action);
setup_irq(JMR3927_IRQ_ISAC_ISAER, &isaerr_action);
}
#ifdef CONFIG_PCI
setup_irq(JMR3927_IRQ_IRC_PCI, &pcierr_action);
#endif
/* enable all CPU interrupt bits. */
set_c0_status(ST0_IM); /* IE bit is still 0. */
}
void (*irq_setup)(void);
void __init init_IRQ(void)
{
#ifdef CONFIG_KGDB
extern void breakpoint(void);
extern void set_debug_traps(void);
puts("Wait for gdb client connection ...\n");
set_debug_traps();
breakpoint();
#endif
/* invoke board-specific irq setup */
irq_setup();
}
hw_irq_controller jmr3927_irq_controller = {
"jmr3927_irq",
jmr3927_irq_startup,
jmr3927_irq_shutdown,
jmr3927_irq_enable,
jmr3927_irq_disable,
jmr3927_irq_ack,
jmr3927_irq_end,
NULL /* no affinity stuff for UP */
};
void
jmr3927_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &jmr3927_irq_controller;
}
jmr3927_irq_base = irq_base;
}
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
static int tx_branch_likely_bug_count = 0;
static int have_tx_branch_likely_bug = 0;
void tx_branch_likely_bug_fixup(struct pt_regs *regs)
{
/* TX39/49-BUG: Under this condition, the insn in delay slot
of the branch likely insn is executed (not nullified) even
the branch condition is false. */
if (!have_tx_branch_likely_bug)
return;
if ((regs->cp0_epc & 0xfff) == 0xffc &&
KSEGX(regs->cp0_epc) != KSEG0 &&
KSEGX(regs->cp0_epc) != KSEG1) {
unsigned int insn = *(unsigned int*)(regs->cp0_epc - 4);
/* beql,bnel,blezl,bgtzl */
/* bltzl,bgezl,blezall,bgezall */
/* bczfl, bcztl */
if ((insn & 0xf0000000) == 0x50000000 ||
(insn & 0xfc0e0000) == 0x04020000 ||
(insn & 0xf3fe0000) == 0x41020000) {
regs->cp0_epc -= 4;
tx_branch_likely_bug_count++;
printk(KERN_INFO
"fix branch-likery bug in %s (insn %08x)\n",
current->comm, insn);
}
}
}
#endif
arch/mips/jmr3927/rbhma3100/kgdb_io.c 0 → 100644
View file @ 60409e5c
/*
* BRIEF MODULE DESCRIPTION
* Low level uart routines to directly access a TX[34]927 SIO.
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com or source@mvista.com
*
* Based on arch/mips/ddb5xxx/ddb5477/kgdb_io.c
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/types.h>
#include <asm/jmr3927/txx927.h>
#include <asm/jmr3927/tx3927.h>
#include <asm/jmr3927/jmr3927.h>
#define TIMEOUT 0xffffff
#define SLOW_DOWN
static const char digits[16] = "0123456789abcdef";
#ifdef SLOW_DOWN
#define slow_down() { int k; for (k=0; k<10000; k++); }
#else
#define slow_down()
#endif
static int remoteDebugInitialized = 0;
int putDebugChar(unsigned char c)
{
int i = 0;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(38400);
}
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (!(tx3927_sioptr(0)->cisr & TXx927_SICISR_TXALS));
tx3927_sioptr(0)->tfifo = c;
return 1;
}
unsigned char getDebugChar(void)
{
int i = 0;
int dicr;
char c;
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(38400);
}
/* diable RX int. */
dicr = tx3927_sioptr(0)->dicr;
tx3927_sioptr(0)->dicr = 0;
do {
slow_down();
i++;
if (i>TIMEOUT) {
break;
}
} while (tx3927_sioptr(0)->disr & TXx927_SIDISR_UVALID)
;
c = tx3927_sioptr(0)->rfifo;
/* clear RX int. status */
tx3927_sioptr(0)->disr &= ~TXx927_SIDISR_RDIS;
/* enable RX int. */
tx3927_sioptr(0)->dicr = dicr;
return c;
}
void debugInit(int baud)
{
/*
volatile unsigned long lcr;
volatile unsigned long dicr;
volatile unsigned long disr;
volatile unsigned long cisr;
volatile unsigned long fcr;
volatile unsigned long flcr;
volatile unsigned long bgr;
volatile unsigned long tfifo;
volatile unsigned long rfifo;
*/
tx3927_sioptr(0)->lcr = 0x020;
tx3927_sioptr(0)->dicr = 0;
tx3927_sioptr(0)->disr = 0x4100;
tx3927_sioptr(0)->cisr = 0x014;
tx3927_sioptr(0)->fcr = 0;
tx3927_sioptr(0)->flcr = 0x02;
tx3927_sioptr(0)->bgr = ((JMR3927_BASE_BAUD + baud / 2) / baud) |
TXx927_SIBGR_BCLK_T0;
#if 0
/*
* Reset the UART.
*/
tx3927_sioptr(0)->fcr = TXx927_SIFCR_SWRST;
while (tx3927_sioptr(0)->fcr & TXx927_SIFCR_SWRST)
;
/*
* and set the speed of the serial port
* (currently hardwired to 9600 8N1
*/
tx3927_sioptr(0)->lcr = TXx927_SILCR_UMODE_8BIT |
TXx927_SILCR_USBL_1BIT |
TXx927_SILCR_SCS_IMCLK_BG;
tx3927_sioptr(0)->bgr =
((JMR3927_BASE_BAUD + baud / 2) / baud) |
TXx927_SIBGR_BCLK_T0;
/* HW RTS/CTS control */
if (ser->flags & ASYNC_HAVE_CTS_LINE)
tx3927_sioptr(0)->flcr = TXx927_SIFLCR_RCS | TXx927_SIFLCR_TES |
TXx927_SIFLCR_RTSTL_MAX /* 15 */;
/* Enable RX/TX */
tx3927_sioptr(0)->flcr &= ~(TXx927_SIFLCR_RSDE | TXx927_SIFLCR_TSDE);
#endif
}
arch/mips/jmr3927/rbhma3100/rtc.c 0 → 100644
View file @ 60409e5c
/*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* RTC routines for Dallas chip.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 200-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <asm/mc146818rtc.h> /* bad name... */
#include <asm/jmr3927/jmr3927.h>
static unsigned char jmr3927_rtc_read_data(unsigned long addr)
{
return jmr3927_nvram_in(addr);
}
static void jmr3927_rtc_write_data(unsigned char data, unsigned long addr)
{
jmr3927_nvram_out(data, addr);
}
static int jmr3927_rtc_bcd_mode(void)
{
return 1;
}
struct rtc_ops jmr3927_rtc_ops = {
&jmr3927_rtc_read_data,
&jmr3927_rtc_write_data,
&jmr3927_rtc_bcd_mode
};
arch/mips/jmr3927/rbhma3100/setup.c 0 → 100644
View file @ 60409e5c
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* Based on arch/mips/ddb5xxx/ddb5477/setup.c
*
* Setup file for JMR3927.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
***********************************************************************
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/console.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ide.h>
#include <linux/ioport.h>
#include <linux/param.h> /* for HZ */
#include <linux/delay.h>
#include <asm/addrspace.h>
#include <asm/time.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/jmr3927/jmr3927.h>
#include <asm/mipsregs.h>
#include <asm/traps.h>
/* Tick Timer divider */
#define JMR3927_TIMER_CCD 0 /* 1/2 */
#define JMR3927_TIMER_CLK (JMR3927_IMCLK / (2 << JMR3927_TIMER_CCD))
unsigned char led_state = 0xf;
struct {
struct resource ram0;
struct resource ram1;
struct resource pcimem;
struct resource iob;
struct resource ioc;
struct resource pciio;
struct resource jmy1394;
struct resource rom1;
struct resource rom0;
struct resource sio0;
struct resource sio1;
} jmr3927_resources = {
{ "RAM0", 0, 0x01FFFFFF, IORESOURCE_MEM },
{ "RAM1", 0x02000000, 0x03FFFFFF, IORESOURCE_MEM },
{ "PCIMEM", 0x08000000, 0x07FFFFFF, IORESOURCE_MEM },
{ "IOB", 0x10000000, 0x13FFFFFF },
{ "IOC", 0x14000000, 0x14FFFFFF },
{ "PCIIO", 0x15000000, 0x15FFFFFF },
{ "JMY1394", 0x1D000000, 0x1D3FFFFF },
{ "ROM1", 0x1E000000, 0x1E3FFFFF },
{ "ROM0", 0x1FC00000, 0x1FFFFFFF },
{ "SIO0", 0xFFFEF300, 0xFFFEF3FF },
{ "SIO1", 0xFFFEF400, 0xFFFEF4FF },
};
/* don't enable - see errata */
int jmr3927_ccfg_toeon = 0;
static inline void do_reset(void)
{
#ifdef CONFIG_TC35815
extern void tc35815_killall(void);
tc35815_killall();
#endif
#if 1 /* Resetting PCI bus */
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
(void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
mdelay(1);
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
#endif
jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
}
static void jmr3927_machine_restart(char *command)
{
cli();
puts("Rebooting...");
do_reset();
}
static void jmr3927_machine_halt(void)
{
puts("JMR-TX3927 halted.\n");
while (1);
}
static void jmr3927_machine_power_off(void)
{
puts("JMR-TX3927 halted. Please turn off the power.\n");
while (1);
}
#define USE_RTC_DS1742
#ifdef USE_RTC_DS1742
extern void rtc_ds1742_init(unsigned long base);
#endif
static void __init jmr3927_time_init(void)
{
#ifdef USE_RTC_DS1742
if (jmr3927_have_nvram()) {
rtc_ds1742_init(JMR3927_IOC_NVRAMB_ADDR);
}
#endif
}
unsigned long jmr3927_do_gettimeoffset(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init jmr3927_timer_setup(struct irqaction *irq)
{
do_gettimeoffset = jmr3927_do_gettimeoffset;
jmr3927_tmrptr->cpra = JMR3927_TIMER_CLK / HZ;
jmr3927_tmrptr->itmr = TXx927_TMTITMR_TIIE | TXx927_TMTITMR_TZCE;
jmr3927_tmrptr->ccdr = JMR3927_TIMER_CCD;
jmr3927_tmrptr->tcr =
TXx927_TMTCR_TCE | TXx927_TMTCR_CCDE | TXx927_TMTCR_TMODE_ITVL;
setup_irq(JMR3927_IRQ_TICK, irq);
}
#define USECS_PER_JIFFY (1000000/HZ)
unsigned long jmr3927_do_gettimeoffset(void)
{
unsigned long count;
unsigned long res = 0;
/* MUST read TRR before TISR. */
count = jmr3927_tmrptr->trr;
if (jmr3927_tmrptr->tisr & TXx927_TMTISR_TIIS) {
/* timer interrupt is pending. use Max value. */
res = USECS_PER_JIFFY - 1;
} else {
/* convert to usec */
/* res = count / (JMR3927_TIMER_CLK / 1000000); */
res = (count << 7) / ((JMR3927_TIMER_CLK << 7) / 1000000);
/*
* Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
res = USECS_PER_JIFFY-1;
}
return res;
}
#if defined(CONFIG_BLK_DEV_INITRD)
extern unsigned long __rd_start, __rd_end, initrd_start, initrd_end;
#endif
//#undef DO_WRITE_THROUGH
#define DO_WRITE_THROUGH
#define DO_ENABLE_CACHE
extern char * __init prom_getcmdline(void);
static void jmr3927_board_init(void);
extern void jmr3927_irq_setup(void);
extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;
void __init jmr3927_setup(void)
{
extern int panic_timeout;
char *argptr;
irq_setup = jmr3927_irq_setup;
set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
board_time_init = jmr3927_time_init;
board_timer_setup = jmr3927_timer_setup;
_machine_restart = jmr3927_machine_restart;
_machine_halt = jmr3927_machine_halt;
_machine_power_off = jmr3927_machine_power_off;
/*
* IO/MEM resources.
*/
ioport_resource.start = pci_io_resource.start;
ioport_resource.end = pci_io_resource.end;
iomem_resource.start = pci_mem_resource.start;
iomem_resource.end = pci_mem_resource.end;
/* Reboot on panic */
panic_timeout = 180;
{
unsigned int conf;
conf = read_c0_conf();
}
#if 1
/* cache setup */
{
unsigned int conf;
#ifdef DO_ENABLE_CACHE
int mips_ic_disable = 0, mips_dc_disable = 0;
#else
int mips_ic_disable = 1, mips_dc_disable = 1;
#endif
#ifdef DO_WRITE_THROUGH
int mips_config_cwfon = 0;
int mips_config_wbon = 0;
#else
int mips_config_cwfon = 1;
int mips_config_wbon = 1;
#endif
conf = read_c0_conf();
conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
write_c0_conf(conf);
write_c0_cache(0);
}
#endif
/* initialize board */
jmr3927_board_init();
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "toeon")) != NULL) {
jmr3927_ccfg_toeon = 1;
}
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "ip=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " ip=bootp");
}
#ifdef CONFIG_TXX927_SERIAL_CONSOLE
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "console=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " console=ttyS1,115200");
}
#endif
}
static void tx3927_setup(void);
#ifdef CONFIG_PCI
unsigned long mips_pci_io_base;
unsigned long mips_pci_io_size;
unsigned long mips_pci_mem_base;
unsigned long mips_pci_mem_size;
/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
unsigned long mips_pci_io_pciaddr = 0;
#endif
extern struct rtc_ops *rtc_ops;
extern struct rtc_ops jmr3927_rtc_ops;
static void __init jmr3927_board_init(void)
{
char *argptr;
#ifdef CONFIG_PCI
mips_pci_io_base = JMR3927_PCIIO;
mips_pci_io_size = JMR3927_PCIIO_SIZE;
mips_pci_mem_base = JMR3927_PCIMEM;
mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
#endif
tx3927_setup();
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
if (jmr3927_have_isac()) {
#ifdef CONFIG_FB_E1355
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "video=")) == NULL) {
argptr = prom_getcmdline();
strcat(argptr, " video=e1355fb:crt16h");
}
#endif
#ifdef CONFIG_BLK_DEV_IDE
/* overrides PCI-IDE */
#endif
}
#ifdef USE_RTC_DS1742
if (jmr3927_have_nvram()) {
rtc_ops = &jmr3927_rtc_ops;
}
#endif
/* SIO0 DTR on */
jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
jmr3927_led_set(0);
if (jmr3927_have_isac())
jmr3927_io_led_set(0);
printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
jmr3927_dipsw1(), jmr3927_dipsw2(),
jmr3927_dipsw3(), jmr3927_dipsw4());
if (jmr3927_have_isac())
printk("JMI-3927IO2 --- ISAC(Rev %d) DIPSW:%01x\n",
jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_REV_MASK,
jmr3927_io_dipsw());
}
static void __init tx3927_setup(void)
{
int i;
/* SDRAMC are configured by PROM */
/* ROMC */
tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
/* CCFG */
/* enable Timeout BusError */
if (jmr3927_ccfg_toeon)
tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
/* clear BusErrorOnWrite flag */
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
/* Disable PCI snoop */
tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
#ifdef DO_WRITE_THROUGH
/* Enable PCI SNOOP - with write through only */
tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
#endif
/* Pin selection */
tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
tx3927_ccfgptr->pcfg |=
TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
(TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
tx3927_ccfgptr->crir,
tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
/* IRC */
/* disable interrupt control */
tx3927_ircptr->cer = 0;
/* mask all IRC interrupts */
tx3927_ircptr->imr = 0;
for (i = 0; i < TX3927_NUM_IR / 2; i++) {
tx3927_ircptr->ilr[i] = 0;
}
/* setup IRC interrupt mode (Low Active) */
for (i = 0; i < TX3927_NUM_IR / 8; i++) {
tx3927_ircptr->cr[i] = 0;
}
/* TMR */
/* disable all timers */
for (i = 0; i < TX3927_NR_TMR; i++) {
tx3927_tmrptr(i)->tcr = TXx927_TMTCR_CRE;
tx3927_tmrptr(i)->tisr = 0;
tx3927_tmrptr(i)->cpra = 0xffffffff;
tx3927_tmrptr(i)->itmr = 0;
tx3927_tmrptr(i)->ccdr = 0;
tx3927_tmrptr(i)->pgmr = 0;
}
/* DMA */
tx3927_dmaptr->mcr = 0;
for (i = 0; i < sizeof(tx3927_dmaptr->ch) / sizeof(tx3927_dmaptr->ch[0]); i++) {
/* reset channel */
tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
tx3927_dmaptr->ch[i].ccr = 0;
}
/* enable DMA */
#ifdef __BIG_ENDIAN
tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
#else
tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
#endif
#ifdef CONFIG_PCI
/* PCIC */
printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
tx3927_pcicptr->did, tx3927_pcicptr->vid,
tx3927_pcicptr->rid);
if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
printk("External\n");
/* XXX */
} else {
printk("Internal\n");
/* Reset PCI Bus */
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
udelay(100);
jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
JMR3927_IOC_RESET_ADDR);
udelay(100);
jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
/* Disable External PCI Config. Access */
tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
#ifdef __BIG_ENDIAN
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
TX3927_PCIC_LBC_TIBSE |
TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
#endif
/* LB->PCI mappings */
tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
tx3927_pcicptr->ilbioma = mips_pci_io_base;
tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
tx3927_pcicptr->ilbmma = mips_pci_mem_base;
tx3927_pcicptr->ipbmma = mips_pci_mem_base;
/* PCI->LB mappings */
tx3927_pcicptr->iobas = 0xffffffff;
tx3927_pcicptr->ioba = 0;
tx3927_pcicptr->tlbioma = 0;
tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
tx3927_pcicptr->mba = 0;
tx3927_pcicptr->tlbmma = 0;
#ifndef JMR3927_INIT_INDIRECT_PCI
/* Enable Direct mapping Address Space Decoder */
tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
#endif
/* Clear All Local Bus Status */
tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
/* Enable All Local Bus Interrupts */
tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
/* Clear All PCI Status Error */
tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
/* Enable All PCI Status Error Interrupts */
tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
/* PCIC Int => IRC IRQ10 */
tx3927_pcicptr->il = TX3927_IR_PCI;
#if 1
/* Target Control (per errata) */
tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
#endif
/* Enable Bus Arbiter */
#if 0
tx3927_pcicptr->req_trace = 0x73737373;
#endif
tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY |
#if 1
PCI_COMMAND_IO |
#endif
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
}
#endif /* CONFIG_PCI */
/* PIO */
/* PIO[15:12] connected to LEDs */
tx3927_pioptr->dir = 0x0000f000;
tx3927_pioptr->maskcpu = 0;
tx3927_pioptr->maskext = 0;
{
unsigned int conf;
conf = read_c0_conf();
if (!(conf & TX39_CONF_ICE))
printk("TX3927 I-Cache disabled.\n");
if (!(conf & TX39_CONF_DCE))
printk("TX3927 D-Cache disabled.\n");
else if (!(conf & TX39_CONF_WBON))
printk("TX3927 D-Cache WriteThrough.\n");
else if (!(conf & TX39_CONF_CWFON))
printk("TX3927 D-Cache WriteBack.\n");
else
printk("TX3927 D-Cache WriteBack (CWF) .\n");
}
}
include/asm-mips/jmr3927/ds1742rtc.h 0 → 100644
View file @ 60409e5c
/*
* ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
*
* Based on include/asm-mips/ds1643rtc.h.
*
* Copyright (C) 1999-2001 Toshiba Corporation
* It was written to be part of the Linux operating system.
*/
/* permission is hereby granted to copy, modify and redistribute this code
* in terms of the GNU Library General Public License, Version 2 or later,
* at your option.
*/
#ifndef _DS1742RTC_H
#define _DS1742RTC_H
#include <linux/rtc.h>
#include <asm/mc146818rtc.h> /* bad name... */
#define RTC_BRAM_SIZE 0x800
#define RTC_OFFSET 0x7f8
/**********************************************************************
* register summary
**********************************************************************/
#define RTC_CONTROL (RTC_OFFSET + 0)
#define RTC_CENTURY (RTC_OFFSET + 0)
#define RTC_SECONDS (RTC_OFFSET + 1)
#define RTC_MINUTES (RTC_OFFSET + 2)
#define RTC_HOURS (RTC_OFFSET + 3)
#define RTC_DAY (RTC_OFFSET + 4)
#define RTC_DATE (RTC_OFFSET + 5)
#define RTC_MONTH (RTC_OFFSET + 6)
#define RTC_YEAR (RTC_OFFSET + 7)
#define RTC_CENTURY_MASK 0x3f
#define RTC_SECONDS_MASK 0x7f
#define RTC_DAY_MASK 0x07
/*
* Bits in the Control/Century register
*/
#define RTC_WRITE 0x80
#define RTC_READ 0x40
/*
* Bits in the Seconds register
*/
#define RTC_STOP 0x80
/*
* Bits in the Day register
*/
#define RTC_BATT_FLAG 0x80
#define RTC_FREQ_TEST 0x40
/*
* Conversion between binary and BCD.
*/
#ifndef BCD_TO_BIN
#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
#endif
#ifndef BIN_TO_BCD
#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
#endif
#endif /* _DS1742RTC_H */
include/asm-mips/jmr3927/irq.h 0 → 100644
View file @ 60409e5c
/*
* linux/include/asm-mips/tx3927/irq.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Toshiba Corporation
*/
#ifndef __ASM_TX3927_IRQ_H
#define __ASM_TX3927_IRQ_H
#ifndef __ASSEMBLY__
#include <linux/config.h>
#include <asm/irq.h>
struct tb_irq_space {
struct tb_irq_space* next;
int start_irqno;
int nr_irqs;
void (*mask_func)(int irq_nr, int space_id);
void (*unmask_func)(int irq_no, int space_id);
const char *name;
int space_id;
int can_share;
};
extern struct tb_irq_space* tb_irq_spaces;
static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
{
sp->next = tb_irq_spaces;
tb_irq_spaces = sp;
}
struct pt_regs;
extern void
toshibaboards_spurious(struct pt_regs *regs, int irq);
extern void
toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
extern struct irqaction *
toshibaboards_get_irq_action(int irq);
extern int
toshibaboards_setup_irq(int irq, struct irqaction * new);
#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
#endif
extern int (*toshibaboards_gen_iack)(void);
#endif /* !__ASSEMBLY__ */
#define NR_ISA_IRQS 16
#define TB_IRQ_IS_ISA(irq) \
(0 <= (irq) && (irq) < NR_ISA_IRQS)
#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
#endif /* __ASM_TX3927_IRQ_H */
include/asm-mips/jmr3927/jmr3927.h 0 → 100644
View file @ 60409e5c
/*
* Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000-2001 Toshiba Corporation
*/
#ifndef __ASM_TX3927_JMR3927_H
#define __ASM_TX3927_JMR3927_H
#include <asm/jmr3927/tx3927.h>
#include <asm/addrspace.h>
#include <asm/jmr3927/irq.h>
#ifndef __ASSEMBLY__
#include <asm/system.h>
#endif
/* CS */
#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
#define JMR3927_ROMCE1 0x1e000000 /* 4M */
#define JMR3927_ROMCE2 0x14000000 /* 16M */
#define JMR3927_ROMCE3 0x10000000 /* 64M */
#define JMR3927_ROMCE5 0x1d000000 /* 4M */
#define JMR3927_SDCS0 0x00000000 /* 32M */
#define JMR3927_SDCS1 0x02000000 /* 32M */
/* PCI Direct Mappings */
#define JMR3927_PCIMEM 0x08000000
#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
#define JMR3927_PCIIO 0x15000000
#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
#define JMR3927_PORT_BASE KSEG1
/* select indirect initiator access per errata */
#define JMR3927_INIT_INDIRECT_PCI
#define PCI_ISTAT_IDICC 0x1000
#define PCI_IPCIBE_IBE_LONG 0
#define PCI_IPCIBE_ICMD_IOREAD 2
#define PCI_IPCIBE_ICMD_IOWRITE 3
#define PCI_IPCIBE_ICMD_MEMREAD 6
#define PCI_IPCIBE_ICMD_MEMWRITE 7
#define PCI_IPCIBE_ICMD_SHIFT 4
/* Address map (virtual address) */
#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
/* Flash ROM */
#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
#define JMR3927_FLASH_SIZE 0x00400000
/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
#define JMR3927_IDT_MASK 0xfc
#define JMR3927_REV_MASK 0x03
#define JMR3927_IOC_IDT 0xe0
#define JMR3927_ISAC_IDT 0x20
/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
#define JMR3927_IOC_INTB_PCIA 0
#define JMR3927_IOC_INTB_PCIB 1
#define JMR3927_IOC_INTB_PCIC 2
#define JMR3927_IOC_INTB_PCID 3
#define JMR3927_IOC_INTB_MODEM 4
#define JMR3927_IOC_INTB_INT6 5
#define JMR3927_IOC_INTB_INT7 6
#define JMR3927_IOC_INTB_SOFT 7
#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
/* bits for IOC_RESET (high byte) */
#define JMR3927_IOC_RESET_CPU 1
#define JMR3927_IOC_RESET_PCI 2
/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
#define JMR3927_ISAC_EINTB_IOCHK 2
#define JMR3927_ISAC_EINTB_BWTH 4
#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
/* bits for ISAC_LED (high byte) */
#define JMR3927_ISAC_LED_ISALED 0x01
#define JMR3927_ISAC_LED_USRLED 0x02
/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
#define JMR3927_ISAC_INTB_IRQ5 0
#define JMR3927_ISAC_INTB_IRQKB 1
#define JMR3927_ISAC_INTB_IRQMOUSE 2
#define JMR3927_ISAC_INTB_IRQ4 3
#define JMR3927_ISAC_INTB_IRQ12 4
#define JMR3927_ISAC_INTB_IRQ3 5
#define JMR3927_ISAC_INTB_IRQ10 6
#define JMR3927_ISAC_INTB_ISAER 7
#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
#ifndef __ASSEMBLY__
#if 0
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
#else
#if defined(__BIG_ENDIAN)
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
#elif defined(__LITTLE_ENDIAN)
#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
#else
#error "No Endian"
#endif
#endif
#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
extern inline int jmr3927_have_isac(void)
{
unsigned char idt;
unsigned long flags;
unsigned long romcr3;
local_irq_save(flags);
romcr3 = tx3927_romcptr->cr[3];
tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
tx3927_romcptr->cr[3] = romcr3;
local_irq_restore(flags);
return idt == JMR3927_ISAC_IDT;
}
#define jmr3927_have_nvram() \
((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
/* NVRAM macro */
#define jmr3927_nvram_in(ofs) \
jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
#define jmr3927_nvram_out(d, ofs) \
jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
/* LED macro */
#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
/* DIPSW4 macro */
#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0)
#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
#endif /* !__ASSEMBLY__ */
/*
* UART defines for serial.h
*/
/* use Pre-scaler T0 (1/2) */
#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
#define UART0_ADDR 0xfffef300
#define UART1_ADDR 0xfffef400
#define UART0_INT JMR3927_IRQ_IRC_SIO0
#define UART1_INT JMR3927_IRQ_IRC_SIO1
#define UART0_FLAGS ASYNC_BOOT_AUTOCONF
#define UART1_FLAGS 0
/*
* IRQ mappings
*/
/* These are the virtual IRQ numbers, we divide all IRQ's into
* 'spaces', the 'space' determines where and how to enable/disable
* that particular IRQ on an JMR machine. Add new 'spaces' as new
* IRQ hardware is supported.
*/
#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
#define JMR3927_IRQ_IRC NR_ISA_IRQS
#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
#if 0 /* auto detect */
/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
#endif
/* IOC (PCI, MODEM) */
#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
/* Clock Tick (10ms) */
#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
/* I/O Ports */
/* RTL8019AS 10M Ether */
#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
/* Clocks */
#define JMR3927_CORECLK 132710400 /* 132.7MHz */
#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
/*
* TX3927 Pin Configuration:
*
* PCFG bits Avail Dead
* SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
* SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
* SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
* GDBGE* PIO[2:1]
* SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
* SELTMR[2:0]:000 TIMER[1:0]
* SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
* DMAREQ[1],DMAACK[1]
* SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
* SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
* SELDONE:1 DMADONE PIO[7]
*
* Usable pins are:
* RXD[1;0],TXD[1:0],CTS[0],RTS[0],
* DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
* INT[3:0]
*/
#endif /* __ASM_TX3927_JMR3927_H */
include/asm-mips/jmr3927/pci.h 0 → 100644
View file @ 60409e5c
/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ahennessy@mvista.com
*
* include/asm-mips/jmr3927/pci.h
* Based on include/asm-mips/ddb5xxx/pci.h
*
* This file essentially defines the interface between board
* specific PCI code and MIPS common PCI code. Should potentially put
* into include/asm/pci.h file.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*
***********************************************************************
*/
#ifndef __ASM_TX3927_PCI_H
#define __ASM_TX3927__PCI_H
#include <linux/ioport.h>
#include <linux/pci.h>
/*
* Each pci channel is a top-level PCI bus seem by CPU. A machine with
* multiple PCI channels may have multiple PCI host controllers or a
* single controller supporting multiple channels.
*/
struct pci_channel {
struct pci_ops *pci_ops;
struct resource *io_resource;
struct resource *mem_resource;
};
/*
* each board defines an array of pci_channels, that ends with all NULL entry
*/
extern struct pci_channel mips_pci_channels[];
/*
* board supplied pci irq fixup routine
*/
extern void pcibios_fixup_irqs(void);
#endif /* __ASM_TX3927_PCI_H */
include/asm-mips/jmr3927/tx3927.h 0 → 100644
View file @ 60409e5c
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Toshiba Corporation
*/
#ifndef __ASM_TX3927_H
#define __ASM_TX3927_H
#include <asm/jmr3927/txx927.h>
#define TX3927_SDRAMC_REG 0xfffe8000
#define TX3927_ROMC_REG 0xfffe9000
#define TX3927_DMA_REG 0xfffeb000
#define TX3927_IRC_REG 0xfffec000
#define TX3927_PCIC_REG 0xfffed000
#define TX3927_CCFG_REG 0xfffee000
#define TX3927_NR_TMR 3
#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100)
#define TX3927_NR_SIO 2
#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
#define TX3927_PIO_REG 0xfffef500
#ifndef __ASSEMBLY__
struct tx3927_sdramc_reg {
volatile unsigned long cr[8];
volatile unsigned long tr[3];
volatile unsigned long cmd;
volatile unsigned long smrs[2];
};
struct tx3927_romc_reg {
volatile unsigned long cr[8];
};
struct tx3927_dma_reg {
struct tx3927_dma_ch_reg {
volatile unsigned long cha;
volatile unsigned long sar;
volatile unsigned long dar;
volatile unsigned long cntr;
volatile unsigned long sair;
volatile unsigned long dair;
volatile unsigned long ccr;
volatile unsigned long csr;
} ch[4];
volatile unsigned long dbr[8];
volatile unsigned long tdhr;
volatile unsigned long mcr;
volatile unsigned long unused0;
};
struct tx3927_irc_reg {
volatile unsigned long cer;
volatile unsigned long cr[2];
volatile unsigned long unused0;
volatile unsigned long ilr[8];
volatile unsigned long unused1[4];
volatile unsigned long imr;
volatile unsigned long unused2[7];
volatile unsigned long scr;
volatile unsigned long unused3[7];
volatile unsigned long ssr;
volatile unsigned long unused4[7];
volatile unsigned long csr;
};
#include <asm/byteorder.h>
#ifdef __BIG_ENDIAN
#define endian_def_s2(e1,e2) \
volatile unsigned short e1,e2
#define endian_def_sb2(e1,e2,e3) \
volatile unsigned short e1;volatile unsigned char e2,e3
#define endian_def_b2s(e1,e2,e3) \
volatile unsigned char e1,e2;volatile unsigned short e3
#define endian_def_b4(e1,e2,e3,e4) \
volatile unsigned char e1,e2,e3,e4
#else
#define endian_def_s2(e1,e2) \
volatile unsigned short e2,e1
#define endian_def_sb2(e1,e2,e3) \
volatile unsigned char e3,e2;volatile unsigned short e1
#define endian_def_b2s(e1,e2,e3) \
volatile unsigned short e3;volatile unsigned char e2,e1
#define endian_def_b4(e1,e2,e3,e4) \
volatile unsigned char e4,e3,e2,e1
#endif
struct tx3927_pcic_reg {
endian_def_s2(did, vid);
endian_def_s2(pcistat, pcicmd);
endian_def_b4(cc, scc, rpli, rid);
endian_def_b4(unused0, ht, mlt, cls);
volatile unsigned long ioba; /* +10 */
volatile unsigned long mba;
volatile unsigned long unused1[5];
endian_def_s2(svid, ssvid);
volatile unsigned long unused2; /* +30 */
endian_def_sb2(unused3, unused4, capptr);
volatile unsigned long unused5;
endian_def_b4(ml, mg, ip, il);
volatile unsigned long unused6; /* +40 */
volatile unsigned long istat;
volatile unsigned long iim;
volatile unsigned long rrt;
volatile unsigned long unused7[3]; /* +50 */
volatile unsigned long ipbmma;
volatile unsigned long ipbioma; /* +60 */
volatile unsigned long ilbmma;
volatile unsigned long ilbioma;
volatile unsigned long unused8[9];
volatile unsigned long tc; /* +90 */
volatile unsigned long tstat;
volatile unsigned long tim;
volatile unsigned long tccmd;
volatile unsigned long pcirrt; /* +a0 */
volatile unsigned long pcirrt_cmd;
volatile unsigned long pcirrdt;
volatile unsigned long unused9[3];
volatile unsigned long tlboap;
volatile unsigned long tlbiap;
volatile unsigned long tlbmma; /* +c0 */
volatile unsigned long tlbioma;
volatile unsigned long sc_msg;
volatile unsigned long sc_be;
volatile unsigned long tbl; /* +d0 */
volatile unsigned long unused10[3];
volatile unsigned long pwmng; /* +e0 */
volatile unsigned long pwmngs;
volatile unsigned long unused11[6];
volatile unsigned long req_trace; /* +100 */
volatile unsigned long pbapmc;
volatile unsigned long pbapms;
volatile unsigned long pbapmim;
volatile unsigned long bm; /* +110 */
volatile unsigned long cpcibrs;
volatile unsigned long cpcibgs;
volatile unsigned long pbacs;
volatile unsigned long iobas; /* +120 */
volatile unsigned long mbas;
volatile unsigned long lbc;
volatile unsigned long lbstat;
volatile unsigned long lbim; /* +130 */
volatile unsigned long pcistatim;
volatile unsigned long ica;
volatile unsigned long icd;
volatile unsigned long iiadp; /* +140 */
volatile unsigned long iscdp;
volatile unsigned long mmas;
volatile unsigned long iomas;
volatile unsigned long ipciaddr; /* +150 */
volatile unsigned long ipcidata;
volatile unsigned long ipcibe;
};
struct tx3927_ccfg_reg {
volatile unsigned long ccfg;
volatile unsigned long crir;
volatile unsigned long pcfg;
volatile unsigned long tear;
volatile unsigned long pdcr;
};
#endif /* !__ASSEMBLY__ */
/*
* SDRAMC
*/
/*
* ROMC
*/
/*
* DMA
*/
/* bits for MCR */
#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
#define TX3927_DMA_MCR_RSFIF 0x00000080
#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
#define TX3927_DMA_MCR_LE 0x00000004
#define TX3927_DMA_MCR_RPRT 0x00000002
#define TX3927_DMA_MCR_MSTEN 0x00000001
/* bits for CCRn */
#define TX3927_DMA_CCR_DBINH 0x04000000
#define TX3927_DMA_CCR_SBINH 0x02000000
#define TX3927_DMA_CCR_CHRST 0x01000000
#define TX3927_DMA_CCR_RVBYTE 0x00800000
#define TX3927_DMA_CCR_ACKPOL 0x00400000
#define TX3927_DMA_CCR_REQPL 0x00200000
#define TX3927_DMA_CCR_EGREQ 0x00100000
#define TX3927_DMA_CCR_CHDN 0x00080000
#define TX3927_DMA_CCR_DNCTL 0x00060000
#define TX3927_DMA_CCR_EXTRQ 0x00010000
#define TX3927_DMA_CCR_INTRQD 0x0000e000
#define TX3927_DMA_CCR_INTENE 0x00001000
#define TX3927_DMA_CCR_INTENC 0x00000800
#define TX3927_DMA_CCR_INTENT 0x00000400
#define TX3927_DMA_CCR_CHNEN 0x00000200
#define TX3927_DMA_CCR_XFACT 0x00000100
#define TX3927_DMA_CCR_SNOP 0x00000080
#define TX3927_DMA_CCR_DSTINC 0x00000040
#define TX3927_DMA_CCR_SRCINC 0x00000020
#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
#define TX3927_DMA_CCR_MEMIO 0x00000002
#define TX3927_DMA_CCR_ONEAD 0x00000001
/* bits for CSRn */
#define TX3927_DMA_CSR_CHNACT 0x00000100
#define TX3927_DMA_CSR_ABCHC 0x00000080
#define TX3927_DMA_CSR_NCHNC 0x00000040
#define TX3927_DMA_CSR_NTRNFC 0x00000020
#define TX3927_DMA_CSR_EXTDN 0x00000010
#define TX3927_DMA_CSR_CFERR 0x00000008
#define TX3927_DMA_CSR_CHERR 0x00000004
#define TX3927_DMA_CSR_DESERR 0x00000002
#define TX3927_DMA_CSR_SORERR 0x00000001
/*
* IRC
*/
#define TX3927_IR_MAX_LEVEL 7
/* IRCER : Int. Control Enable */
#define TX3927_IRCER_ICE 0x00000001
/* IRCR : Int. Control */
#define TX3927_IRCR_LOW 0x00000000
#define TX3927_IRCR_HIGH 0x00000001
#define TX3927_IRCR_DOWN 0x00000002
#define TX3927_IRCR_UP 0x00000003
/* IRSCR : Int. Status Control */
#define TX3927_IRSCR_EIClrE 0x00000100
#define TX3927_IRSCR_EIClr_MASK 0x0000000f
/* IRCSR : Int. Current Status */
#define TX3927_IRCSR_IF 0x00010000
#define TX3927_IRCSR_ILV_MASK 0x00000700
#define TX3927_IRCSR_IVL_MASK 0x0000001f
#define TX3927_IR_INT0 0
#define TX3927_IR_INT1 1
#define TX3927_IR_INT2 2
#define TX3927_IR_INT3 3
#define TX3927_IR_INT4 4
#define TX3927_IR_INT5 5
#define TX3927_IR_SIO0 6
#define TX3927_IR_SIO1 7
#define TX3927_IR_SIO(ch) (6 + (ch))
#define TX3927_IR_DMA 8
#define TX3927_IR_PIO 9
#define TX3927_IR_PCI 10
#define TX3927_IR_TMR0 13
#define TX3927_IR_TMR1 14
#define TX3927_IR_TMR2 15
#define TX3927_NUM_IR 16
/*
* PCIC
*/
/* bits for PCICMD */
/* see PCI_COMMAND_XXX in linux/pci.h */
/* bits for PCISTAT */
/* see PCI_STATUS_XXX in linux/pci.h */
#define PCI_STATUS_NEW_CAP 0x0010
/* bits for TC */
#define TX3927_PCIC_TC_OF16E 0x00000020
#define TX3927_PCIC_TC_IF8E 0x00000010
#define TX3927_PCIC_TC_OF8E 0x00000008
/* bits for IOBA/MBA */
/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
/* bits for PBAPMC */
#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
/* bits for LBSTAT/LBIM */
#define TX3927_PCIC_LBIM_ALL 0x0000003e
/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
/* bits for LBC */
#define TX3927_PCIC_LBC_IBSE 0x00004000
#define TX3927_PCIC_LBC_TIBSE 0x00002000
#define TX3927_PCIC_LBC_TMFBSE 0x00001000
#define TX3927_PCIC_LBC_HRST 0x00000800
#define TX3927_PCIC_LBC_SRST 0x00000400
#define TX3927_PCIC_LBC_EPCAD 0x00000200
#define TX3927_PCIC_LBC_MSDSE 0x00000100
#define TX3927_PCIC_LBC_CRR 0x00000080
#define TX3927_PCIC_LBC_ILMDE 0x00000040
#define TX3927_PCIC_LBC_ILIDE 0x00000020
#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
/*
* CCFG
*/
/* CCFG : Chip Configuration */
#define TX3927_CCFG_TLBOFF 0x00020000
#define TX3927_CCFG_BEOW 0x00010000
#define TX3927_CCFG_WR 0x00008000
#define TX3927_CCFG_TOE 0x00004000
#define TX3927_CCFG_PCIXARB 0x00002000
#define TX3927_CCFG_PCI3 0x00001000
#define TX3927_CCFG_PSNP 0x00000800
#define TX3927_CCFG_PPRI 0x00000400
#define TX3927_CCFG_PLLM 0x00000030
#define TX3927_CCFG_ENDIAN 0x00000004
#define TX3927_CCFG_HALT 0x00000002
#define TX3927_CCFG_ACEHOLD 0x00000001
/* PCFG : Pin Configuration */
#define TX3927_PCFG_SYSCLKEN 0x08000000
#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
#define TX3927_PCFG_SELALL 0x0003ffff
#define TX3927_PCFG_SELCS 0x00020000
#define TX3927_PCFG_SELDSF 0x00010000
#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
#define TX3927_PCFG_SELSIO_ALL 0x00003000
#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
#define TX3927_PCFG_SELTMR_ALL 0x00000e00
#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
#define TX3927_PCFG_SELDONE 0x00000100
#define TX3927_PCFG_INTDMA_ALL 0x000000f0
#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
#define TX3927_PCFG_SELDMA_ALL 0x0000000f
#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
#ifndef __ASSEMBLY__
#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_TX3927_H */
include/asm-mips/jmr3927/txx927.h 0 → 100644
View file @ 60409e5c
/*
* Common definitions for TX3927/TX4927
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Toshiba Corporation
*/
#ifndef __ASM_TXX927_H
#define __ASM_TXX927_H
#ifndef __ASSEMBLY__
struct txx927_tmr_reg {
volatile unsigned long tcr;
volatile unsigned long tisr;
volatile unsigned long cpra;
volatile unsigned long cprb;
volatile unsigned long itmr;
volatile unsigned long unused0[3];
volatile unsigned long ccdr;
volatile unsigned long unused1[3];
volatile unsigned long pgmr;
volatile unsigned long unused2[3];
volatile unsigned long wtmr;
volatile unsigned long unused3[43];
volatile unsigned long trr;
};
struct txx927_sio_reg {
volatile unsigned long lcr;
volatile unsigned long dicr;
volatile unsigned long disr;
volatile unsigned long cisr;
volatile unsigned long fcr;
volatile unsigned long flcr;
volatile unsigned long bgr;
volatile unsigned long tfifo;
volatile unsigned long rfifo;
};
struct txx927_pio_reg {
volatile unsigned long dout;
volatile unsigned long din;
volatile unsigned long dir;
volatile unsigned long od;
volatile unsigned long flag[2];
volatile unsigned long pol;
volatile unsigned long intc;
volatile unsigned long maskcpu;
volatile unsigned long maskext;
};
#endif /* !__ASSEMBLY__ */
/*
* TMR
*/
/* TMTCR : Timer Control */
#define TXx927_TMTCR_TCE 0x00000080
#define TXx927_TMTCR_CCDE 0x00000040
#define TXx927_TMTCR_CRE 0x00000020
#define TXx927_TMTCR_ECES 0x00000008
#define TXx927_TMTCR_CCS 0x00000004
#define TXx927_TMTCR_TMODE_MASK 0x00000003
#define TXx927_TMTCR_TMODE_ITVL 0x00000000
/* TMTISR : Timer Int. Status */
#define TXx927_TMTISR_TPIBS 0x00000004
#define TXx927_TMTISR_TPIAS 0x00000002
#define TXx927_TMTISR_TIIS 0x00000001
/* TMTITMR : Interval Timer Mode */
#define TXx927_TMTITMR_TIIE 0x00008000
#define TXx927_TMTITMR_TZCE 0x00000001
/*
* SIO
*/
/* SILCR : Line Control */
#define TXx927_SILCR_SCS_MASK 0x00000060
#define TXx927_SILCR_SCS_IMCLK 0x00000000
#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
#define TXx927_SILCR_SCS_SCLK 0x00000040
#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
#define TXx927_SILCR_UEPS 0x00000010
#define TXx927_SILCR_UPEN 0x00000008
#define TXx927_SILCR_USBL_MASK 0x00000004
#define TXx927_SILCR_USBL_1BIT 0x00000004
#define TXx927_SILCR_USBL_2BIT 0x00000000
#define TXx927_SILCR_UMODE_MASK 0x00000003
#define TXx927_SILCR_UMODE_8BIT 0x00000000
#define TXx927_SILCR_UMODE_7BIT 0x00000001
/* SIDICR : DMA/Int. Control */
#define TXx927_SIDICR_TDE 0x00008000
#define TXx927_SIDICR_RDE 0x00004000
#define TXx927_SIDICR_TIE 0x00002000
#define TXx927_SIDICR_RIE 0x00001000
#define TXx927_SIDICR_SPIE 0x00000800
#define TXx927_SIDICR_CTSAC 0x00000600
#define TXx927_SIDICR_STIE_MASK 0x0000003f
#define TXx927_SIDICR_STIE_OERS 0x00000020
#define TXx927_SIDICR_STIE_CTSS 0x00000010
#define TXx927_SIDICR_STIE_RBRKD 0x00000008
#define TXx927_SIDICR_STIE_TRDY 0x00000004
#define TXx927_SIDICR_STIE_TXALS 0x00000002
#define TXx927_SIDICR_STIE_UBRKD 0x00000001
/* SIDISR : DMA/Int. Status */
#define TXx927_SIDISR_UBRK 0x00008000
#define TXx927_SIDISR_UVALID 0x00004000
#define TXx927_SIDISR_UFER 0x00002000
#define TXx927_SIDISR_UPER 0x00001000
#define TXx927_SIDISR_UOER 0x00000800
#define TXx927_SIDISR_ERI 0x00000400
#define TXx927_SIDISR_TOUT 0x00000200
#define TXx927_SIDISR_TDIS 0x00000100
#define TXx927_SIDISR_RDIS 0x00000080
#define TXx927_SIDISR_STIS 0x00000040
#define TXx927_SIDISR_RFDN_MASK 0x0000001f
/* SICISR : Change Int. Status */
#define TXx927_SICISR_OERS 0x00000020
#define TXx927_SICISR_CTSS 0x00000010
#define TXx927_SICISR_RBRKD 0x00000008
#define TXx927_SICISR_TRDY 0x00000004
#define TXx927_SICISR_TXALS 0x00000002
#define TXx927_SICISR_UBRKD 0x00000001
/* SIFCR : FIFO Control */
#define TXx927_SIFCR_SWRST 0x00008000
#define TXx927_SIFCR_RDIL_MASK 0x00000180
#define TXx927_SIFCR_RDIL_1 0x00000000
#define TXx927_SIFCR_RDIL_4 0x00000080
#define TXx927_SIFCR_RDIL_8 0x00000100
#define TXx927_SIFCR_RDIL_12 0x00000180
#define TXx927_SIFCR_RDIL_MAX 0x00000180
#define TXx927_SIFCR_TDIL_MASK 0x00000018
#define TXx927_SIFCR_TDIL_MASK 0x00000018
#define TXx927_SIFCR_TDIL_1 0x00000000
#define TXx927_SIFCR_TDIL_4 0x00000001
#define TXx927_SIFCR_TDIL_8 0x00000010
#define TXx927_SIFCR_TDIL_MAX 0x00000010
#define TXx927_SIFCR_TFRST 0x00000004
#define TXx927_SIFCR_RFRST 0x00000002
#define TXx927_SIFCR_FRSTE 0x00000001
#define TXx927_SIO_TX_FIFO 8
#define TXx927_SIO_RX_FIFO 16
/* SIFLCR : Flow Control */
#define TXx927_SIFLCR_RCS 0x00001000
#define TXx927_SIFLCR_TES 0x00000800
#define TXx927_SIFLCR_RTSSC 0x00000200
#define TXx927_SIFLCR_RSDE 0x00000100
#define TXx927_SIFLCR_TSDE 0x00000080
#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
#define TXx927_SIFLCR_TBRK 0x00000001
/* SIBGR : Baudrate Control */
#define TXx927_SIBGR_BCLK_MASK 0x00000300
#define TXx927_SIBGR_BCLK_T0 0x00000000
#define TXx927_SIBGR_BCLK_T2 0x00000100
#define TXx927_SIBGR_BCLK_T4 0x00000200
#define TXx927_SIBGR_BCLK_T6 0x00000300
#define TXx927_SIBGR_BRD_MASK 0x000000ff
/*
* PIO
*/
#endif /* __ASM_TXX927_H */
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