drm/i915/psr: Don't tell sink that main link will be active while is active PSR2

For PSR2 there is no register to tell HW to keep main link enabled
while PSR2 is active, so don't configure sink DPCD with a
misleading value.

v2: Moving the set of DP_PSR_CRC_VERIFICATION to the else block
of 'if (dev_priv->psr.psr2_enabled)' to another patch. (Rodrigo)

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181204003403.23361-2-jose.souza@intel.com
parent 7c5c641a
...@@ -395,10 +395,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) ...@@ -395,10 +395,11 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE); DP_ALPM_ENABLE);
dpcd_val |= DP_PSR_ENABLE_PSR2; dpcd_val |= DP_PSR_ENABLE_PSR2;
} } else {
if (dev_priv->psr.link_standby) if (dev_priv->psr.link_standby)
dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
}
if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)
dpcd_val |= DP_PSR_CRC_VERIFICATION; dpcd_val |= DP_PSR_CRC_VERIFICATION;
drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val);
......
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