drm/amd/display: send display_count msg so SMU can enter S0i2

SMU can future lower voltages in long idle case when all display is off.

If all display output is turned off via DPMS, send display_count = 0
after all output are turned off.

otherwise send display_count msg before turning on display to make sure
SMU exit S0i2 state.  before is not neccessary as we are out of S0i2
when driver execute code, but send message before anyways for correctness.
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc.c

@@ -389,12 +389,20 @@ void set_dpms(
 
 	if (stream->dpms_off != dpms_off) {
 		stream->dpms_off = dpms_off;
-		if (dpms_off)
+
+		if (dpms_off) {
 			core_link_disable_stream(pipe_ctx,
 					KEEP_ACQUIRED_RESOURCE);
-		else
+
+			dc->hwss.pplib_apply_display_requirements(
+					dc, dc->current_state);
+		} else {
+			dc->hwss.pplib_apply_display_requirements(
+					dc, dc->current_state);
+
 			core_link_enable_stream(dc->current_state, pipe_ctx);
 		}
+	}
 }
 
 static void allocate_dc_stream_funcs(struct dc  *dc)

drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

@@ -148,5 +148,7 @@ void dce100_hw_sequencer_construct(struct dc *dc)
 
 	dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
 	dc->hwss.set_bandwidth = dce100_set_bandwidth;
+	dc->hwss.pplib_apply_display_requirements =
+			dce100_pplib_apply_display_requirements;
 }
 

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

@@ -2595,6 +2595,10 @@ void dce110_fill_display_configs(
 
 		ASSERT(pipe_ctx != NULL);
 
+		/* only notify active stream */
+		if (stream->dpms_off)
+			continue;
+
 		num_cfgs++;
 		cfg->signal = pipe_ctx->stream->signal;
 		cfg->pipe_idx = pipe_ctx->pipe_idx;
@@ -3024,6 +3028,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
 	.ready_shared_resources = ready_shared_resources,
 	.optimize_shared_resources = optimize_shared_resources,
+	.pplib_apply_display_requirements = pplib_apply_display_requirements,
 	.edp_backlight_control = hwss_edp_backlight_control,
 	.edp_power_control = hwss_edp_power_control,
 };

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -2567,6 +2567,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
 	.ready_shared_resources = ready_shared_resources,
 	.optimize_shared_resources = optimize_shared_resources,
+	.pplib_apply_display_requirements =
+			dcn10_pplib_apply_display_requirements,
 	.edp_backlight_control = hwss_edp_backlight_control,
 	.edp_power_control = hwss_edp_power_control
 };

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

@@ -183,12 +183,16 @@ struct hw_sequencer_funcs {
 
 	void (*ready_shared_resources)(struct dc *dc, struct dc_state *context);
 	void (*optimize_shared_resources)(struct dc *dc);
+	void (*pplib_apply_display_requirements)(
+			struct dc *dc,
+			struct dc_state *context);
 	void (*edp_power_control)(
 			struct dc_link *link,
 			bool enable);
 	void (*edp_backlight_control)(
 			struct dc_link *link,
 			bool enable);
+
 };
 
 void color_space_to_black_color(