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Commit 64507fe3 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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ARM: dts: sun9i: Switch to new clock bindings 

Now that we have a full clock driver for sun9i, switch to it.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 783ab76a
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Showing with 107 additions and 297 deletions
arch/arm/boot/dts/sun9i-a80.dtsi
View file @ 64507fe3
...@@ -48,6 +48,13 @@ ...@@ -48,6 +48,13 @@
#include <dt-bindings/pinctrl/sun4i-a10.h> #include <dt-bindings/pinctrl/sun4i-a10.h>
#include <dt-bindings/clock/sun9i-a80-ccu.h>
#include <dt-bindings/clock/sun9i-a80-de.h>
#include <dt-bindings/clock/sun9i-a80-usb.h>
#include <dt-bindings/reset/sun9i-a80-ccu.h>
#include <dt-bindings/reset/sun9i-a80-de.h>
#include <dt-bindings/reset/sun9i-a80-usb.h>
/ { / {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
...@@ -159,228 +166,13 @@ osc32k: osc32k_clk { ...@@ -159,228 +166,13 @@ osc32k: osc32k_clk {
clock-output-names = "osc32k"; clock-output-names = "osc32k";
}; };
usb_mod_clk: clk@00a08000 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-mod-clk";
reg = <0x00a08000 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb0_ahb", "usb_ohci0",
"usb1_ahb", "usb_ohci1",
"usb2_ahb", "usb_ohci2";
};
usb_phy_clk: clk@00a08004 {
#clock-cells = <1>;
#reset-cells = <1>;
compatible = "allwinner,sun9i-a80-usb-phy-clk";
reg = <0x00a08004 0x4>;
clocks = <&ahb1_gates 1>;
clock-output-names = "usb_phy0", "usb_hsic1_480M",
"usb_phy1", "usb_hsic2_480M",
"usb_phy2", "usb_hsic_12M";
};
pll3: clk@06000008 {
/* placeholder until implemented */
#clock-cells = <0>;
compatible = "fixed-clock";
clock-rate = <0>;
clock-output-names = "pll3";
};
pll4: clk@0600000c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
reg = <0x0600000c 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll4";
};
pll12: clk@0600002c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-pll4-clk";
reg = <0x0600002c 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll12";
};
gt_clk: clk@0600005c {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-gt-clk";
reg = <0x0600005c 0x4>;
clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "gt";
};
ahb0: clk@06000060 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-ahb-clk";
reg = <0x06000060 0x4>;
clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "ahb0";
};
ahb1: clk@06000064 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-ahb-clk";
reg = <0x06000064 0x4>;
clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "ahb1";
};
ahb2: clk@06000068 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-ahb-clk";
reg = <0x06000068 0x4>;
clocks = <&gt_clk>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "ahb2";
};
apb0: clk@06000070 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-apb0-clk";
reg = <0x06000070 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "apb0";
};
apb1: clk@06000074 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-apb1-clk";
reg = <0x06000074 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "apb1";
};
cci400_clk: clk@06000078 {
#clock-cells = <0>;
compatible = "allwinner,sun9i-a80-gt-clk";
reg = <0x06000078 0x4>;
clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>;
clock-output-names = "cci400";
};
mmc0_clk: clk@06000410 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-clk";
reg = <0x06000410 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "mmc0", "mmc0_output",
"mmc0_sample";
};
mmc1_clk: clk@06000414 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-clk";
reg = <0x06000414 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "mmc1", "mmc1_output",
"mmc1_sample";
};
mmc2_clk: clk@06000418 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-clk";
reg = <0x06000418 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "mmc2", "mmc2_output",
"mmc2_sample";
};
mmc3_clk: clk@0600041c {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-mmc-clk";
reg = <0x0600041c 0x4>;
clocks = <&osc24M>, <&pll4>;
clock-output-names = "mmc3", "mmc3_output",
"mmc3_sample";
};
ahb0_gates: clk@06000580 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
clock-indices = <0>, <1>, <3>,
<5>, <8>, <12>,
<13>, <14>,
<15>, <16>, <18>,
<20>, <21>, <22>,
<23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
"ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts",
"ahb0_spi0", "ahb0_spi1", "ahb0_spi2",
"ahb0_spi3";
};
ahb1_gates: clk@06000584 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
clock-indices = <0>, <1>,
<17>, <21>,
<22>, <23>,
<24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
"ahb1_dma";
};
ahb2_gates: clk@06000588 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
clock-indices = <0>, <1>,
<2>, <4>, <5>,
<7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
};
apb0_gates: clk@06000590 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
clock-indices = <1>, <5>,
<11>, <12>, <13>,
<15>, <17>, <18>,
<19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
"apb0_cirtx";
};
apb1_gates: clk@06000594 {
#clock-cells = <1>;
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
clock-indices = <0>, <1>,
<2>, <3>, <4>,
<16>, <17>,
<18>, <19>,
<20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
"apb1_uart2", "apb1_uart3",
"apb1_uart4", "apb1_uart5";
};
cpus_clk: clk@08001410 { cpus_clk: clk@08001410 {
compatible = "allwinner,sun9i-a80-cpus-clk"; compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>; reg = <0x08001410 0x4>;
#clock-cells = <0>; #clock-cells = <0>;
clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>; clocks = <&osc32k>, <&osc24M>,
<&ccu CLK_PLL_PERIPH0>,
<&ccu CLK_PLL_AUDIO>;
clock-output-names = "cpus"; clock-output-names = "cpus";
}; };
...@@ -453,8 +245,8 @@ ehci0: usb@00a00000 { ...@@ -453,8 +245,8 @@ ehci0: usb@00a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>; reg = <0x00a00000 0x100>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_mod_clk 1>; clocks = <&usb_clocks CLK_BUS_HCI0>;
resets = <&usb_mod_clk 17>; resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>; phys = <&usbphy1>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
...@@ -464,8 +256,9 @@ ohci0: usb@00a00400 { ...@@ -464,8 +256,9 @@ ohci0: usb@00a00400 {
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a00400 0x100>; reg = <0x00a00400 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_mod_clk 1>, <&usb_mod_clk 2>; clocks = <&usb_clocks CLK_BUS_HCI0>,
resets = <&usb_mod_clk 17>; <&usb_clocks CLK_USB_OHCI0>;
resets = <&usb_clocks RST_USB0_HCI>;
phys = <&usbphy1>; phys = <&usbphy1>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
...@@ -474,9 +267,9 @@ ohci0: usb@00a00400 { ...@@ -474,9 +267,9 @@ ohci0: usb@00a00400 {
usbphy1: phy@00a00800 { usbphy1: phy@00a00800 {
compatible = "allwinner,sun9i-a80-usb-phy"; compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a00800 0x4>; reg = <0x00a00800 0x4>;
clocks = <&usb_phy_clk 1>; clocks = <&usb_clocks CLK_USB0_PHY>;
clock-names = "phy"; clock-names = "phy";
resets = <&usb_phy_clk 17>; resets = <&usb_clocks RST_USB0_PHY>;
reset-names = "phy"; reset-names = "phy";
status = "disabled"; status = "disabled";
#phy-cells = <0>; #phy-cells = <0>;
...@@ -486,8 +279,8 @@ ehci1: usb@00a01000 { ...@@ -486,8 +279,8 @@ ehci1: usb@00a01000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a01000 0x100>; reg = <0x00a01000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_mod_clk 3>; clocks = <&usb_clocks CLK_BUS_HCI1>;
resets = <&usb_mod_clk 18>; resets = <&usb_clocks RST_USB1_HCI>;
phys = <&usbphy2>; phys = <&usbphy2>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
...@@ -496,11 +289,16 @@ ehci1: usb@00a01000 { ...@@ -496,11 +289,16 @@ ehci1: usb@00a01000 {
usbphy2: phy@00a01800 { usbphy2: phy@00a01800 {
compatible = "allwinner,sun9i-a80-usb-phy"; compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>; reg = <0x00a01800 0x4>;
clocks = <&usb_phy_clk 2>, <&usb_phy_clk 10>, clocks = <&usb_clocks CLK_USB1_HSIC>,
<&usb_phy_clk 3>; <&usb_clocks CLK_USB_HSIC>,
clock-names = "hsic_480M", "hsic_12M", "phy"; <&usb_clocks CLK_USB1_PHY>;
resets = <&usb_phy_clk 18>, <&usb_phy_clk 19>; clock-names = "hsic_480M",
reset-names = "hsic", "phy"; "hsic_12M",
"phy";
resets = <&usb_clocks RST_USB1_HSIC>,
<&usb_clocks RST_USB1_PHY>;
reset-names = "hsic",
"phy";
status = "disabled"; status = "disabled";
#phy-cells = <0>; #phy-cells = <0>;
/* usb1 is always used with HSIC */ /* usb1 is always used with HSIC */
...@@ -511,8 +309,8 @@ ehci2: usb@00a02000 { ...@@ -511,8 +309,8 @@ ehci2: usb@00a02000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a02000 0x100>; reg = <0x00a02000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_mod_clk 5>; clocks = <&usb_clocks CLK_BUS_HCI2>;
resets = <&usb_mod_clk 19>; resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>; phys = <&usbphy3>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
...@@ -522,8 +320,9 @@ ohci2: usb@00a02400 { ...@@ -522,8 +320,9 @@ ohci2: usb@00a02400 {
compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
reg = <0x00a02400 0x100>; reg = <0x00a02400 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_mod_clk 5>, <&usb_mod_clk 6>; clocks = <&usb_clocks CLK_BUS_HCI2>,
resets = <&usb_mod_clk 19>; <&usb_clocks CLK_USB_OHCI2>;
resets = <&usb_clocks RST_USB2_HCI>;
phys = <&usbphy3>; phys = <&usbphy3>;
phy-names = "usb"; phy-names = "usb";
status = "disabled"; status = "disabled";
...@@ -532,20 +331,35 @@ ohci2: usb@00a02400 { ...@@ -532,20 +331,35 @@ ohci2: usb@00a02400 {
usbphy3: phy@00a02800 { usbphy3: phy@00a02800 {
compatible = "allwinner,sun9i-a80-usb-phy"; compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>; reg = <0x00a02800 0x4>;
clocks = <&usb_phy_clk 4>, <&usb_phy_clk 10>, clocks = <&usb_clocks CLK_USB2_HSIC>,
<&usb_phy_clk 5>; <&usb_clocks CLK_USB_HSIC>,
clock-names = "hsic_480M", "hsic_12M", "phy"; <&usb_clocks CLK_USB2_PHY>;
resets = <&usb_phy_clk 20>, <&usb_phy_clk 21>; clock-names = "hsic_480M",
reset-names = "hsic", "phy"; "hsic_12M",
"phy";
resets = <&usb_clocks RST_USB2_HSIC>,
<&usb_clocks RST_USB2_PHY>;
reset-names = "hsic",
"phy";
status = "disabled"; status = "disabled";
#phy-cells = <0>; #phy-cells = <0>;
}; };
usb_clocks: clock@00a08000 {
compatible = "allwinner,sun9i-a80-usb-clks";
reg = <0x00a08000 0x8>;
clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
clock-names = "bus", "hosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
mmc0: mmc@01c0f000 { mmc0: mmc@01c0f000 {
compatible = "allwinner,sun9i-a80-mmc"; compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>; reg = <0x01c0f000 0x1000>;
clocks = <&mmc_config_clk 0>, <&mmc0_clk 0>, clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
<&mmc0_clk 1>, <&mmc0_clk 2>; <&ccu CLK_MMC0_OUTPUT>,
<&ccu CLK_MMC0_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample"; clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 0>; resets = <&mmc_config_clk 0>;
reset-names = "ahb"; reset-names = "ahb";
...@@ -558,8 +372,9 @@ mmc0: mmc@01c0f000 { ...@@ -558,8 +372,9 @@ mmc0: mmc@01c0f000 {
mmc1: mmc@01c10000 { mmc1: mmc@01c10000 {
compatible = "allwinner,sun9i-a80-mmc"; compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c10000 0x1000>; reg = <0x01c10000 0x1000>;
clocks = <&mmc_config_clk 1>, <&mmc1_clk 0>, clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
<&mmc1_clk 1>, <&mmc1_clk 2>; <&ccu CLK_MMC1_OUTPUT>,
<&ccu CLK_MMC1_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample"; clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 1>; resets = <&mmc_config_clk 1>;
reset-names = "ahb"; reset-names = "ahb";
...@@ -572,8 +387,9 @@ mmc1: mmc@01c10000 { ...@@ -572,8 +387,9 @@ mmc1: mmc@01c10000 {
mmc2: mmc@01c11000 { mmc2: mmc@01c11000 {
compatible = "allwinner,sun9i-a80-mmc"; compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c11000 0x1000>; reg = <0x01c11000 0x1000>;
clocks = <&mmc_config_clk 2>, <&mmc2_clk 0>, clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
<&mmc2_clk 1>, <&mmc2_clk 2>; <&ccu CLK_MMC2_OUTPUT>,
<&ccu CLK_MMC2_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample"; clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 2>; resets = <&mmc_config_clk 2>;
reset-names = "ahb"; reset-names = "ahb";
...@@ -586,8 +402,9 @@ mmc2: mmc@01c11000 { ...@@ -586,8 +402,9 @@ mmc2: mmc@01c11000 {
mmc3: mmc@01c12000 { mmc3: mmc@01c12000 {
compatible = "allwinner,sun9i-a80-mmc"; compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c12000 0x1000>; reg = <0x01c12000 0x1000>;
clocks = <&mmc_config_clk 3>, <&mmc3_clk 0>, clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
<&mmc3_clk 1>, <&mmc3_clk 2>; <&ccu CLK_MMC3_OUTPUT>,
<&ccu CLK_MMC3_SAMPLE>;
clock-names = "ahb", "mmc", "output", "sample"; clock-names = "ahb", "mmc", "output", "sample";
resets = <&mmc_config_clk 3>; resets = <&mmc_config_clk 3>;
reset-names = "ahb"; reset-names = "ahb";
...@@ -600,9 +417,9 @@ mmc3: mmc@01c12000 { ...@@ -600,9 +417,9 @@ mmc3: mmc@01c12000 {
mmc_config_clk: clk@01c13000 { mmc_config_clk: clk@01c13000 {
compatible = "allwinner,sun9i-a80-mmc-config-clk"; compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>; reg = <0x01c13000 0x10>;
clocks = <&ahb0_gates 8>; clocks = <&ccu CLK_BUS_MMC>;
clock-names = "ahb"; clock-names = "ahb";
resets = <&ahb0_resets 8>; resets = <&ccu RST_BUS_MMC>;
reset-names = "ahb"; reset-names = "ahb";
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
...@@ -621,34 +438,27 @@ gic: interrupt-controller@01c41000 { ...@@ -621,34 +438,27 @@ gic: interrupt-controller@01c41000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
ahb0_resets: reset@060005a0 { de_clocks: clock@03000000 {
#reset-cells = <1>; compatible = "allwinner,sun9i-a80-de-clks";
compatible = "allwinner,sun6i-a31-clock-reset"; reg = <0x03000000 0x30>;
reg = <0x060005a0 0x4>; clocks = <&ccu CLK_DE>,
}; <&ccu CLK_SDRAM>,
<&ccu CLK_BUS_DE>;
ahb1_resets: reset@060005a4 { clock-names = "mod",
#reset-cells = <1>; "dram",
compatible = "allwinner,sun6i-a31-clock-reset"; "bus";
reg = <0x060005a4 0x4>; resets = <&ccu RST_BUS_DE>;
}; #clock-cells = <1>;
ahb2_resets: reset@060005a8 {
#reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x060005a8 0x4>;
};
apb0_resets: reset@060005b0 {
#reset-cells = <1>; #reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x060005b0 0x4>;
}; };
apb1_resets: reset@060005b4 { ccu: clock@06000000 {
compatible = "allwinner,sun9i-a80-ccu";
reg = <0x06000000 0x800>;
clocks = <&osc24M>, <&osc32k>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
compatible = "allwinner,sun6i-a31-clock-reset";
reg = <0x060005b4 0x4>;
}; };
timer@06000c00 { timer@06000c00 {
...@@ -678,7 +488,7 @@ pio: pinctrl@06000800 { ...@@ -678,7 +488,7 @@ pio: pinctrl@06000800 {
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 5>, <&osc24M>, <&osc32k>; clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc"; clock-names = "apb", "hosc", "losc";
gpio-controller; gpio-controller;
interrupt-controller; interrupt-controller;
...@@ -740,8 +550,8 @@ uart0: serial@07000000 { ...@@ -740,8 +550,8 @@ uart0: serial@07000000 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 16>; clocks = <&ccu CLK_BUS_UART0>;
resets = <&apb1_resets 16>; resets = <&ccu RST_BUS_UART0>;
status = "disabled"; status = "disabled";
}; };
...@@ -751,8 +561,8 @@ uart1: serial@07000400 { ...@@ -751,8 +561,8 @@ uart1: serial@07000400 {
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 17>; clocks = <&ccu CLK_BUS_UART1>;
resets = <&apb1_resets 17>; resets = <&ccu RST_BUS_UART1>;
status = "disabled"; status = "disabled";
}; };
...@@ -762,8 +572,8 @@ uart2: serial@07000800 { ...@@ -762,8 +572,8 @@ uart2: serial@07000800 {
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 18>; clocks = <&ccu CLK_BUS_UART2>;
resets = <&apb1_resets 18>; resets = <&ccu RST_BUS_UART2>;
status = "disabled"; status = "disabled";
}; };
...@@ -773,8 +583,8 @@ uart3: serial@07000c00 { ...@@ -773,8 +583,8 @@ uart3: serial@07000c00 {
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 19>; clocks = <&ccu CLK_BUS_UART3>;
resets = <&apb1_resets 19>; resets = <&ccu RST_BUS_UART3>;
status = "disabled"; status = "disabled";
}; };
...@@ -784,8 +594,8 @@ uart4: serial@07001000 { ...@@ -784,8 +594,8 @@ uart4: serial@07001000 {
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 20>; clocks = <&ccu CLK_BUS_UART4>;
resets = <&apb1_resets 20>; resets = <&ccu RST_BUS_UART4>;
status = "disabled"; status = "disabled";
}; };
...@@ -795,8 +605,8 @@ uart5: serial@07001400 { ...@@ -795,8 +605,8 @@ uart5: serial@07001400 {
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&apb1_gates 21>; clocks = <&ccu CLK_BUS_UART5>;
resets = <&apb1_resets 21>; resets = <&ccu RST_BUS_UART5>;
status = "disabled"; status = "disabled";
}; };
...@@ -804,8 +614,8 @@ i2c0: i2c@07002800 { ...@@ -804,8 +614,8 @@ i2c0: i2c@07002800 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002800 0x400>; reg = <0x07002800 0x400>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 0>; clocks = <&ccu CLK_BUS_I2C0>;
resets = <&apb1_resets 0>; resets = <&ccu RST_BUS_I2C0>;
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -815,8 +625,8 @@ i2c1: i2c@07002c00 { ...@@ -815,8 +625,8 @@ i2c1: i2c@07002c00 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07002c00 0x400>; reg = <0x07002c00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 1>; clocks = <&ccu CLK_BUS_I2C1>;
resets = <&apb1_resets 1>; resets = <&ccu RST_BUS_I2C1>;
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -826,8 +636,8 @@ i2c2: i2c@07003000 { ...@@ -826,8 +636,8 @@ i2c2: i2c@07003000 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003000 0x400>; reg = <0x07003000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 2>; clocks = <&ccu CLK_BUS_I2C2>;
resets = <&apb1_resets 2>; resets = <&ccu RST_BUS_I2C2>;
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -837,8 +647,8 @@ i2c3: i2c@07003400 { ...@@ -837,8 +647,8 @@ i2c3: i2c@07003400 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003400 0x400>; reg = <0x07003400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 3>; clocks = <&ccu CLK_BUS_I2C3>;
resets = <&apb1_resets 3>; resets = <&ccu RST_BUS_I2C3>;
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -848,8 +658,8 @@ i2c4: i2c@07003800 { ...@@ -848,8 +658,8 @@ i2c4: i2c@07003800 {
compatible = "allwinner,sun6i-a31-i2c"; compatible = "allwinner,sun6i-a31-i2c";
reg = <0x07003800 0x400>; reg = <0x07003800 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb1_gates 4>; clocks = <&ccu CLK_BUS_I2C4>;
resets = <&apb1_resets 4>; resets = <&ccu RST_BUS_I2C4>;
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
......
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