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Commit 64d3cfb4 authored by Anton Blanchard's avatar Anton Blanchard
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Merge samba.org:/scratch/anton/linux-2.5 

into samba.org:/scratch/anton/linux-2.5_ppc64
parents 79a5d877 3980957c
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Documentation/ide.txt
View file @ 64d3cfb4
ide.txt -- Information regarding the Enhanced IDE drive in Linux 2.2/2.3/2.4
===============================================================================
+-----------------------------------------------------------------+
| The hdparm utility for controlling various IDE features is |
| packaged separately. Look for it on popular linux FTP sites. |
+-----------------------------------------------------------------+
See description later on below for handling BIG IDE drives with >1024 cyls.
Major features of the 2.1/2.2 IDE driver ("NEW!" marks changes since 2.0.xx):
NEW! - support for IDE ATAPI *floppy* drives
- support for IDE ATAPI *tape* drives, courtesy of Gadi Oxman
(re-run MAKEDEV.ide to create the tape device entries in /dev/)
- support for up to *four* IDE interfaces on one or more IRQs
- support for any mix of up to *eight* IDE drives
- support for reading IDE ATAPI cdrom drives (NEC,MITSUMI,VERTOS,SONY)
- support for audio functions
- auto-detection of interfaces, drives, IRQs, and disk geometries
- "single" drives should be jumpered as "master", not "slave"
(both are now probed for)
- support for BIOSs which report "more than 16 heads" on disk drives
- uses LBA (slightly faster) on disk drives which support it
- support for lots of fancy (E)IDE drive functions with hdparm utility
- optional (compile time) support for 32-bit VLB data transfers
- support for IDE multiple (block) mode (same as hd.c)
- support for interrupt unmasking during I/O (better than hd.c)
- improved handshaking and error detection/recovery
- can co-exist with hd.c controlling the first interface
- run-time selectable 32bit interface support (using hdparm-2.3)
- support for reliable operation of buggy RZ1000 interfaces
- PCI support is automatic when rz1000 support is configured
- support for reliable operation of buggy CMD-640 interfaces
- PCI support is automatic when cmd640 support is configured
- for VLB, use kernel command line option: ide0=cmd640_vlb
- this support also enables the secondary i/f when needed
- interface PIO timing & prefetch parameter support
- experimental support for UMC 8672 interfaces
- support for secondary interface on the FGI/Holtek HT-6560B VLB i/f
- use kernel command line option: ide0=ht6560b
- experimental support for various IDE chipsets
- use appropriate kernel command line option from list below
- support for drives with a stuck WRERR_STAT bit
- support for removable devices, including door lock/unlock
- transparent support for DiskManager 6.0x and "Dynamic Disk Overlay"
- works with Linux fdisk, LILO, loadlin, bootln, etc..
- mostly transparent support for EZ-Drive disk translation software
- to use LILO with EZ, install LILO on the linux partition
rather than on the master boot record, and then mark the
linux partition as "bootable" or "active" using fdisk.
(courtesy of Juha Laiho <jlaiho@ichaos.nullnet.fi>).
- auto-detect of disk translations by examining partition table
- ide-cd.c now compiles separate from ide.c
- ide-cd.c now supports door locking and auto-loading.
- Also preliminary support for multisession
and direct reads of audio data.
- experimental support for Promise DC4030VL caching interface card
- email thanks/problems to: peterd@pnd-pc.demon.co.uk
- the hdparm-3.1 package can be used to set PIO modes for some chipsets.
NEW! - support for setting PIO modes with the OPTi 82C621, courtesy of Jaromir Koutek.
NEW! - support for loadable modules
NEW! - optional SCSI host adapter emulation for ATAPI devices
NEW! - generic PCI Bus-Master DMA support
NEW! - works with most Pentium PCI systems, chipsets, add-on cards
NEW! - works with regular DMA as well as Ultra DMA
NEW! - automatically probes for all PCI IDE interfaces
NEW! - generic support for using BIOS-configured Ultra-DMA (UDMA) transfers
Information regarding the Enhanced IDE drive in Linux 2.5
==============================================================================
The hdparm utility can be used to controll various IDE features on a
running system. It is packaged separately. Please Look for it on popular
linux FTP sites.
*** IMPORTANT NOTICES: BUGGY IDE CHIPSETS CAN CORRUPT DATA!!
......@@ -92,9 +37,9 @@ NEW! - generic support for using BIOS-configured Ultra-DMA (UDMA) transfers
***
*** Use of the "serialize" option is no longer necessary.
This is the multiple IDE interface driver, as evolved from hd.c.
It supports up to six IDE interfaces, on one or more IRQs (usually 14 & 15).
There can be up to two drives per interface, as per the ATA-2 spec.
This is the multiple IDE interface driver, as evolved from hd.c. It supports
up to 9 IDE interfaces per default, on one or more IRQs (usually 14 & 15).
There can be up to two drives per interface, as per the ATA-6 spec.
Primary: ide0, port 0x1f0; major=3; hda is minor=0; hdb is minor=64
Secondary: ide1, port 0x170; major=22; hdc is minor=0; hdd is minor=64
......@@ -103,16 +48,14 @@ Quaternary: ide3, port 0x168; major=34; hdg is minor=0; hdh is minor=64
fifth.. ide4, usually PCI, probed
sixth.. ide5, usually PCI, probed
To access devices on interfaces > ide0, device entries must first be
created in /dev for them. To create such entries, simply run the included
shell script: /usr/src/linux/scripts/MAKEDEV.ide
Apparently many older releases of Slackware had incorrect entries
in /dev for hdc* and hdd* -- this can also be corrected by running MAKEDEV.ide
To access devices on interfaces > ide0, device entries please make sure that
device files for them are present in /dev. If not, please create such
entries, by simply running the included shell script:
/usr/src/linux/scripts/MAKEDEV.ide
ide.c automatically probes for most IDE interfaces (including all PCI ones),
for the drives/geometries attached to those interfaces, and for the
IRQ numbers being used by the interfaces (normally 14, 15 for ide0/ide1).
This driver automatically probes for most IDE interfaces (including all PCI
ones), for the drives/geometries attached to those interfaces, and for the IRQ
lines being used by the interfaces (normally 14, 15 for ide0/ide1).
For special cases, interfaces may be specified using kernel "command line"
options. For example,
......@@ -170,11 +113,11 @@ or
hdc=768,16,32
hdc=noprobe
Note that when only one IDE device is attached to an interface,
it should be jumpered as "single" or "master", *not* "slave".
Many folks have had "trouble" with cdroms because of this requirement,
so ide.c now probes for both units, though success is more likely
when the drive is jumpered correctly.
Note that when only one IDE device is attached to an interface, it should be
jumpered as "single" or "master", *not* "slave". Many folks have had
"trouble" with cdroms because of this requirement, so the driver now probes
for both units, though success is more likely when the drive is jumpered
correctly.
Courtesy of Scott Snyder and others, the driver supports ATAPI cdrom drives
such as the NEC-260 and the new MITSUMI triple/quad speed drives.
......@@ -193,8 +136,8 @@ interface (/dev/hda) and an IDE cdrom drive on the secondary interface
(/dev/hdc). To mount a CD in the cdrom drive, one would use something like:
ln -sf /dev/hdc /dev/cdrom
mkdir /cd
mount /dev/cdrom /cd -t iso9660 -o ro
mkdir /mnt/cdrom
mount /dev/cdrom /mnt/cdrom -t iso9660 -o ro
If, after doing all of the above, mount doesn't work and you see
errors from the driver (with dmesg) complaining about `status=0xff',
......@@ -274,8 +217,6 @@ Summary of ide driver parameters for kernel "command line":
older/odd IDE drives.
"hdx=slow" : insert a huge pause after each access to the data
port. Should be used only as a last resort.
"hdx=swapdata" : when the drive is a disk, byte swap all data
"hdxlun=xx" : set the drive last logical unit
"idebus=xx" : inform IDE driver of VESA/PCI bus speed in MHz,
......@@ -307,8 +248,9 @@ Summary of ide driver parameters for kernel "command line":
"idex=reset" : reset interface after probe
"idex=dma" : automatically configure/use DMA if possible.
The following are valid ONLY on ide0,
and the defaults for the base,ctl ports must not be altered.
The following are valid ONLY on ide0, which usually corresponds to the first
ATA interface found on the particular host, and the defaults for the base,ctl
ports must not be altered.
"ide0=dtc2278" : probe/support DTC2278 interface
"ide0=ht6560b" : probe/support HT6560B interface
......@@ -329,179 +271,21 @@ Some Terminology
IDE = Integrated Drive Electronics, meaning that each drive has a built-in
controller, which is why an "IDE interface card" is not a "controller card".
IDE drives are designed to attach almost directly to the ISA bus of an AT-style
computer. The typical IDE interface card merely provides I/O port address
decoding and tri-state buffers, although several newer localbus cards go much
beyond the basics. When purchasing a localbus IDE interface, avoid cards with
an onboard BIOS and those which require special drivers. Instead, look for a
card which uses hardware switches/jumpers to select the interface timing speed,
to allow much faster data transfers than the original 8MHz ISA bus allows.
ATA = AT (the old IBM 286 computer) Attachment Interface, a draft American
National Standard for connecting hard drives to PCs. This is the official
name for "IDE".
The latest standards define some enhancements, known as the ATA-2 spec,
The latest standards define some enhancements, known as the ATA-6 spec,
which grew out of vendor-specific "Enhanced IDE" (EIDE) implementations.
ATAPI = ATA Packet Interface, a new protocol for controlling the drives,
similar to SCSI protocols, created at the same time as the ATA2 standard.
ATAPI is currently used for controlling CDROM and TAPE devices, and will
likely also soon be used for Floppy drives, removable R/W cartridges,
and for high capacity hard disk drives.
How To Use *Big* ATA/IDE drives with Linux
------------------------------------------
The ATA Interface spec for IDE disk drives allows a total of 28 bits
(8 bits for sector, 16 bits for cylinder, and 4 bits for head) for addressing
individual disk sectors of 512 bytes each (in "Linear Block Address" (LBA)
mode, there is still only a total of 28 bits available in the hardware).
This "limits" the capacity of an IDE drive to no more than 128GB (Giga-bytes).
All current day IDE drives are somewhat smaller than this upper limit, and
within a few years, ATAPI disk drives will raise the limit considerably.
All IDE disk drives "suffer" from a "16-heads" limitation: the hardware has
only a four bit field for head selection, restricting the number of "physical"
heads to 16 or less. Since the BIOS usually has a 63 sectors/track limit,
this means that all IDE drivers larger than 504MB (528Meg) must use a "physical"
geometry with more than 1024 cylinders.
(1024cyls * 16heads * 63sects * 512bytes/sector) / (1024 * 1024) == 504MB
(Some BIOSs (and controllers with onboard BIOS) pretend to allow "32" or "64"
heads per drive (discussed below), but can only do so by playing games with
the real (hidden) geometry, which is always limited to 16 or fewer heads).
This presents two problems to most systems:
1. The INT13 interface to the BIOS only allows 10-bits for cylinder
addresses, giving a limit of 1024cyls for programs which use it.
2. The physical geometry fields of the disk partition table only
allow 10-bits for cylinder addresses, giving a similar limit of 1024
cyls for operating systems that do not use the "sector count" fields
instead of the physical Cyl/Head/Sect (CHS) geometry fields.
Neither of these limitations affects Linux itself, as it (1) does not use the
BIOS for disk access, and it (2) is clever enough to use the "sector count"
fields of the partition table instead of the physical CHS geometry fields.
a) Most folks use LILO to load linux. LILO uses the INT13 interface
to the BIOS to load the kernel at boot time. Therefore, LILO can only
load linux if the files it needs (usually just the kernel images) are
located below the magic 1024 cylinder "boundary" (more on this later).
b) Many folks also like to have bootable DOS partitions on their
drive(s). DOS also uses the INT13 interface to the BIOS, not only
for booting, but also for operation after booting. Therefore, DOS
can normally only access partitions which are contained entirely below
the magic 1024 cylinder "boundary".
There are at least seven commonly used schemes for kludging DOS to work
around this "limitation". In the long term, the problem is being solved
by introduction of an alternative BIOS interface that does not have the
same limitations as the INT13 interface. New versions of DOS are expected
to detect and use this interface in systems whose BIOS provides it.
But in the present day, alternative solutions are necessary.
The most popular solution in newer systems is to have the BIOS shift bits
between the cylinder and head number fields. This is activated by entering
a translated logical geometry into the BIOS/CMOS setup for the drive.
Thus, if the drive has a geometry of 2100/16/63 (CHS), then the BIOS could
present a "logical" geometry of 525/64/63 by "shifting" two bits from the
cylinder number into the head number field for purposes of the partition table,
CMOS setup, and INT13 interfaces. Linux kernels 1.1.39 and higher detect and
"handle" this translation automatically, making this a rather painless solution
for the 1024 cyls problem. If for some reason Linux gets confused (unlikely),
then use the kernel command line parameters to pass the *logical* geometry,
as in: hda=525,64,63
If the BIOS does not support this form of drive translation, then several
options remain, listed below in order of popularity:
- use a partition below the 1024 cyl boundary to hold the linux
boot files (kernel images and /boot directory), and place the rest
of linux anywhere else on the drive. These files can reside in a DOS
partition, or in a tailor-made linux boot partition.
- use DiskManager software from OnTrack, supplied free with
many new hard drive purchases.
- use EZ-Drive software (similar to DiskManager). Note though,
that LILO must *not* use the MBR when EZ-Drive is present.
Instead, install LILO on the first sector of your linux partition,
and mark it as "active" or "bootable" with fdisk.
- boot from a floppy disk instead of the hard drive (takes 10 seconds).
If you cannot use drive translation, *and* your BIOS also restricts you to
entering no more than 1024 cylinders in the geometry field in the CMOS setup,
then just set it to 1024. As of v3.5 of this driver, Linux automatically
determines the *real* number of cylinders for fdisk to use, allowing easy
access to the full disk capacity without having to fiddle around.
Regardless of what you do, all DOS partitions *must* be contained entirely
within the first 1024 logical cylinders. For a 1Gig WD disk drive, here's
a good "half and half" partitioning scheme to start with:
geometry = 2100/16/63
/dev/hda1 from cyl 1 to 992 dos
/dev/hda2 from cyl 993 to 1023 swap
/dev/hda3 from cyl 1024 to 2100 linux
To ensure that LILO can boot linux, the boot files (kernel and /boot/*)
must reside within the first 1024 cylinders of the drive. If your linux
root partition is *not* completely within the first 1024 cyls (quite common),
then you can use LILO to boot linux from files on your DOS partition
by doing the following after installing Slackware (or whatever):
0. Boot from the "boot floppy" created during the installation
1. Mount your DOS partition as /dos (and stick it in /etc/fstab)
2. Move /boot to /dos/boot with: cp -a /boot /dos ; rm -r /boot
3. Create a symlink for LILO to use with: ln -s /dos/boot /boot
4. Move your kernel (/vmlinuz) to /boot/vmlinuz: mv /vmlinuz /boot
5. Edit /etc/lilo.conf to change /vmlinuz to /boot/vmlinuz
6. Re-run LILO with: lilo
A danger with this approach is that whenever an MS-DOS "defragmentation"
program is run (like Norton "speeddisk"), it may move the Linux boot
files around, confusing LILO and making the (Linux) system unbootable.
Be sure to keep a kernel "boot floppy" at hand for such circumstances.
A possible workaround is to mark the Linux files as S+H+R (System,
Hidden, Readonly), to prevent most defragmentation programs from
moving the files around.
If you "don't do DOS", then partition as you please, but remember to create
a small partition to hold the /boot directory (and vmlinuz) as described above
such that they stay within the first 1024 cylinders.
Note that when creating partitions that span beyond cylinder 1024,
Linux fdisk will complain about "Partition X has different physical/logical
endings" and emit messages such as "This is larger than 1024, and may cause
problems with some software". Ignore this for linux partitions. The "some
software" refers to DOS, the BIOS, and LILO, as described previously.
Western Digital ships a "DiskManager 6.03" diskette with all of their big
hard drives. Use BIOS translation instead of this if possible, as it is a
more generally compatible method of achieving the same results (DOS access
to the entire disk). However, if you must use DiskManager, it now works
with Linux 1.3.x in most cases. Let me know if you still have trouble.
My recommendations to anyone who asks about NEW systems are:
- buy a motherboard that uses the Intel Triton chipset -- very common.
- use IDE for the first two drives, placing them on separate interfaces.
- very fast 7200rpm drives are now available
(though many problems have been reported with Seagate ones).
- place the IDE cdrom drive as slave on either interface.
- if additional disks are to be connected, consider your needs:
- fileserver? Buy a SC200 SCSI adaptor for the next few drives.
- personal system? Use IDE for the next two drives.
- still not enough? Keep adding SC200 SCSI cards as needed.
Most manufacturers make both IDE and SCSI versions of each of their drives.
The IDE ones are usually as fast and cheaper, due to lower command overhead
and the higher data transfer speed of UDMA2. But fast/ultrawide/superlative
SCSI is still king of the heap, especially for servers, if you've got the bucks.
ATAPI is currently used for controlling CDROM, TAPE and FLOPPY (ZIP or
LS120/240) devices, removable R/W cartridges, and for high capacity hard disk
drives.
mlord@pobox.com
--
For current maintainers of this stuff, see the linux/MAINTAINERS file.
Wed Apr 17 22:52:44 CEST 2002 edited by Marcin Dalecki
For current maintainers of this stuff, please see the linux/MAINTAINERS file.
arch/cris/drivers/ide.c
View file @ 64d3cfb4
......@@ -280,7 +280,7 @@ init_e100_ide (void)
hwif->tuneproc = &tune_e100_ide;
hwif->dmaproc = &e100_dmaproc;
hwif->ata_read = e100_ide_input_data;
hwif->ata_write = e100_ide_input_data;
hwif->ata_write = e100_ide_output_data;
hwif->atapi_read = e100_atapi_read;
hwif->atapi_write = e100_atapi_write;
}
......@@ -560,32 +560,6 @@ e100_ide_output_data (ide_drive_t *drive, void *buffer, unsigned int wcount)
e100_atapi_write(drive, buffer, wcount << 2);
}
/*
* The multiplexor for ide_xxxput_data and atapi calls
*/
static void
e100_ideproc (ide_ide_action_t func, ide_drive_t *drive,
void *buffer, unsigned int length)
{
switch (func) {
case ideproc_ide_input_data:
e100_ide_input_data(drive, buffer, length);
break;
case ideproc_ide_output_data:
e100_ide_input_data(drive, buffer, length);
break;
case ideproc_atapi_read:
e100_atapi_read(drive, buffer, length);
break;
case ideproc_atapi_write:
e100_atapi_write(drive, buffer, length);
break;
default:
printk("e100_ideproc: unsupported func %d!\n", func);
break;
}
}
/* we only have one DMA channel on the chip for ATA, so we can keep these statically */
static etrax_dma_descr ata_descrs[MAX_DMA_DESCRS];
static unsigned int ata_tot_size;
......
arch/i386/kernel/io_apic.c
View file @ 64d3cfb4
......@@ -1659,6 +1659,7 @@ static inline void check_timer(void)
printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
timer_ack = 0;
init_8259A(0);
make_8259A_irq(0);
apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
......
drivers/ide/amd74xx.c
View file @ 64d3cfb4
......@@ -422,9 +422,10 @@ void __init ide_init_amd74xx(struct ata_channel *hwif)
hwif->speedproc = &amd_set_drive;
hwif->autodma = 0;
hwif->io_32bit = 1;
hwif->unmask = 1;
for (i = 0; i < 2; i++) {
hwif->drives[i].io_32bit = 1;
hwif->drives[i].unmask = 1;
hwif->drives[i].autotune = 1;
hwif->drives[i].dn = hwif->unit * 2 + i;
}
......
drivers/ide/cmd640.c
View file @ 64d3cfb4
......@@ -21,7 +21,7 @@
*
* A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
* bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
* chrisc@dbass.demon.co.uk, dalecki@evision-ventures.com,
* chrisc@dbass.demon.co.uk, martin@dalecki.de,
* derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
* flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
* j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
......@@ -403,19 +403,19 @@ void cmd640_dump_regs (void)
*/
static void __init check_prefetch (unsigned int index)
{
ide_drive_t *drive = cmd_drives[index];
struct ata_device *drive = cmd_drives[index];
byte b = get_cmd640_reg(prefetch_regs[index]);
if (b & prefetch_masks[index]) { /* is prefetch off? */
drive->no_unmask = 0;
drive->no_io_32bit = 1;
drive->io_32bit = 0;
drive->channel->no_unmask = 0;
drive->channel->no_io_32bit = 1;
drive->channel->io_32bit = 0;
} else {
#if CMD640_PREFETCH_MASKS
drive->no_unmask = 1;
drive->unmask = 0;
drive->channel->no_unmask = 1;
drive->channel->unmask = 0;
#endif
drive->no_io_32bit = 0;
drive->channel->no_io_32bit = 0;
}
}
......@@ -460,15 +460,15 @@ static void set_prefetch_mode (unsigned int index, int mode)
b = get_cmd640_reg(reg);
if (mode) { /* want prefetch on? */
#if CMD640_PREFETCH_MASKS
drive->no_unmask = 1;
drive->unmask = 0;
drive->channel->no_unmask = 1;
drive->channel->unmask = 0;
#endif
drive->no_io_32bit = 0;
drive->channel->no_io_32bit = 0;
b &= ~prefetch_masks[index]; /* enable prefetch */
} else {
drive->no_unmask = 0;
drive->no_io_32bit = 1;
drive->io_32bit = 0;
drive->channel->no_unmask = 0;
drive->channel->no_io_32bit = 1;
drive->channel->io_32bit = 0;
b |= prefetch_masks[index]; /* disable prefetch */
}
put_cmd640_reg(reg, b);
......@@ -827,7 +827,7 @@ int __init ide_probe_for_cmd640x(void)
retrieve_drive_counts (index);
check_prefetch (index);
printk("cmd640: drive%d timings/prefetch(%s) preserved",
index, drive->no_io_32bit ? "off" : "on");
index, drive->channel->no_io_32bit ? "off" : "on");
display_clocks(index);
}
#else
......@@ -836,7 +836,7 @@ int __init ide_probe_for_cmd640x(void)
*/
check_prefetch (index);
printk("cmd640: drive%d timings/prefetch(%s) preserved\n",
index, drive->no_io_32bit ? "off" : "on");
index, drive->channel->no_io_32bit ? "off" : "on");
#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
}
......
drivers/ide/dtc2278.c
View file @ 64d3cfb4
......@@ -88,8 +88,7 @@ static void tune_dtc2278 (ide_drive_t *drive, byte pio)
/*
* 32bit I/O has to be enabled for *both* drives at the same time.
*/
drive->io_32bit = 1;
drive->channel->drives[!drive->select.b.unit].io_32bit = 1;
drive->channel->io_32bit = 1;
}
void __init init_dtc2278 (void)
......@@ -120,10 +119,11 @@ void __init init_dtc2278 (void)
ide_hwifs[0].chipset = ide_dtc2278;
ide_hwifs[1].chipset = ide_dtc2278;
ide_hwifs[0].tuneproc = &tune_dtc2278;
ide_hwifs[0].drives[0].no_unmask = 1;
ide_hwifs[0].drives[1].no_unmask = 1;
ide_hwifs[1].drives[0].no_unmask = 1;
ide_hwifs[1].drives[1].no_unmask = 1;
/* FIXME: What about the following?!
ide_hwifs[1].tuneproc = &tune_dtc2278;
*/
ide_hwifs[0].no_unmask = 1;
ide_hwifs[1].no_unmask = 1;
ide_hwifs[0].unit = ATA_PRIMARY;
ide_hwifs[1].unit = ATA_SECONDARY;
}
drivers/ide/ht6560b.c
View file @ 64d3cfb4
......@@ -261,11 +261,11 @@ static void ht_set_prefetch(ide_drive_t *drive, byte state)
*/
if (state) {
drive->drive_data |= t; /* enable prefetch mode */
drive->no_unmask = 1;
drive->unmask = 0;
drive->channel->no_unmask = 1;
drive->channel->unmask = 0;
} else {
drive->drive_data &= ~t; /* disable prefetch mode */
drive->no_unmask = 0;
drive->channel->no_unmask = 0;
}
restore_flags (flags); /* all CPUs */
......
drivers/ide/ide-cd.c
View file @ 64d3cfb4
......@@ -669,6 +669,12 @@ static int cdrom_decode_status (ide_startstop_t *startstop, ide_drive_t *drive,
request or data protect error.*/
ide_dump_status (drive, "command error", stat);
cdrom_end_request(drive, 0);
} else if (sense_key == MEDIUM_ERROR) {
/* No point in re-trying a zillion times on a bad
* sector. The error is not correctable at all.
*/
ide_dump_status (drive, "media error (bad sector)", stat);
cdrom_end_request(drive, 0);
} else if ((err & ~ABRT_ERR) != 0) {
/* Go to the default handler
for other errors. */
......
drivers/ide/ide-disk.c
View file @ 64d3cfb4
......@@ -755,8 +755,6 @@ static void idedisk_pre_reset (ide_drive_t *drive)
drive->special.b.recalibrate = legacy;
if (OK_TO_RESET_CONTROLLER)
drive->mult_count = 0;
if (!drive->keep_settings && !drive->using_dma)
drive->mult_req = 0;
if (drive->mult_req != drive->mult_count)
drive->special.b.set_multmode = 1;
}
......@@ -1231,7 +1229,14 @@ static void idedisk_setup(ide_drive_t *drive)
drive->special.b.set_multmode = 1;
#endif
}
drive->no_io_32bit = id->dword_io ? 1 : 0;
/* FIXME: Nowadays there are many chipsets out there which *require* 32
* bit IO. Those will most propably not work properly with drives not
* supporting this. But right now we don't do anything about this. We
* dont' even *warn* the user!
*/
drive->channel->no_io_32bit = id->dword_io ? 1 : 0;
if (drive->id->cfs_enable_2 & 0x3000)
write_cache(drive, (id->cfs_enable_2 & 0x3000));
......
drivers/ide/ide-dma.c
View file @ 64d3cfb4
......@@ -599,13 +599,19 @@ int ide_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
printk("%s: DMA disabled\n", drive->name);
case ide_dma_off_quietly:
set_high = 0;
drive->using_tcq = 0;
outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
#ifdef CONFIG_BLK_DEV_IDE_TCQ
hwif->dmaproc(ide_dma_queued_off, drive);
#endif
case ide_dma_on:
ide_toggle_bounce(drive, set_high);
drive->using_dma = (func == ide_dma_on);
if (drive->using_dma)
if (drive->using_dma) {
outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
#ifdef CONFIG_BLK_DEV_IDE_TCQ_DEFAULT
hwif->dmaproc(ide_dma_queued_on, drive);
#endif
}
return 0;
case ide_dma_check:
return config_drive_for_dma (drive);
......
drivers/ide/ide-taskfile.c
View file @ 64d3cfb4
......@@ -156,7 +156,7 @@ void ata_read(ide_drive_t *drive, void *buffer, unsigned int wcount)
return;
}
io_32bit = drive->io_32bit;
io_32bit = drive->channel->io_32bit;
if (io_32bit) {
#if SUPPORT_VLB_SYNC
......@@ -167,7 +167,7 @@ void ata_read(ide_drive_t *drive, void *buffer, unsigned int wcount)
ata_read_32(drive, buffer, wcount);
} else {
#if SUPPORT_SLOW_DATA_PORTS
if (drive->slow)
if (drive->channel->slow)
ata_read_slow(drive, buffer, wcount);
else
#endif
......@@ -187,7 +187,7 @@ void ata_write(ide_drive_t *drive, void *buffer, unsigned int wcount)
return;
}
io_32bit = drive->io_32bit;
io_32bit = drive->channel->io_32bit;
if (io_32bit) {
#if SUPPORT_VLB_SYNC
......@@ -198,7 +198,7 @@ void ata_write(ide_drive_t *drive, void *buffer, unsigned int wcount)
ata_write_32(drive, buffer, wcount);
} else {
#if SUPPORT_SLOW_DATA_PORTS
if (drive->slow)
if (drive->channel->slow)
ata_write_slow(drive, buffer, wcount);
else
#endif
......@@ -413,6 +413,20 @@ ide_startstop_t ata_taskfile(ide_drive_t *drive,
struct hd_driveid *id = drive->id;
u8 HIHI = (drive->addressing) ? 0xE0 : 0xEF;
#if 0
printk("ata_taskfile ... %p\n", args->handler);
printk(" sector feature %02x\n", args->taskfile.feature);
printk(" sector count %02x\n", args->taskfile.sector_count);
printk(" drive/head %02x\n", args->taskfile.device_head);
printk(" command %02x\n", args->taskfile.command);
if (rq)
printk(" rq->nr_sectors %2li\n", rq->nr_sectors);
else
printk(" rq-> = null\n");
#endif
/* (ks/hs): Moved to start, do not use for multiple out commands */
if (args->handler != task_mulout_intr) {
if (IDE_CONTROL_REG)
......@@ -577,18 +591,22 @@ static ide_startstop_t task_in_intr (ide_drive_t *drive)
ata_read(drive, pBuf, SECTOR_WORDS);
ide_unmap_rq(rq, pBuf, &flags);
/*
* first segment of the request is complete. note that this does not
* necessarily mean that the entire request is done!! this is only
* true if ide_end_request() returns 0.
*/
if (--rq->current_nr_sectors <= 0) {
/* (hs): swapped next 2 lines */
DTF("Request Ended stat: %02x\n", GET_STAT());
if (ide_end_request(drive, 1)) {
ide_set_handler(drive, &task_in_intr, WAIT_CMD, NULL);
return ide_started;
if (!ide_end_request(drive, 1))
return ide_stopped;
}
} else {
/*
* still data left to transfer
*/
ide_set_handler(drive, &task_in_intr, WAIT_CMD, NULL);
return ide_started;
}
return ide_stopped;
}
static ide_startstop_t pre_task_out_intr(ide_drive_t *drive, struct request *rq)
......@@ -874,7 +892,6 @@ void ide_cmd_type_parser(struct ata_taskfile *args)
return;
case WIN_NOP:
args->command_type = IDE_DRIVE_TASK_NO_DATA;
return;
......@@ -904,11 +921,6 @@ int ide_raw_taskfile(ide_drive_t *drive, struct ata_taskfile *args, byte *buf)
struct ata_request star;
ata_ar_init(drive, &star);
/* Don't put this request on free_req list after usage.
*/
star.ar_flags |= ATA_AR_STATIC;
init_taskfile_request(&rq);
rq.buffer = buf;
......@@ -976,6 +988,7 @@ int ide_cmd_ioctl(ide_drive_t *drive, unsigned long arg)
if (argbuf == NULL)
return -ENOMEM;
memcpy(argbuf, vals, 4);
memset(argbuf + 4, 0, argsize - 4);
}
if (set_transfer(drive, &args)) {
......@@ -986,14 +999,8 @@ int ide_cmd_ioctl(ide_drive_t *drive, unsigned long arg)
/* Issue ATA command and wait for completion.
*/
/* FIXME: Do we really have to zero out the buffer?
*/
memset(argbuf, 4, SECTOR_WORDS * 4 * vals[3]);
ide_init_drive_cmd(&rq);
rq.buffer = argbuf;
memcpy(argbuf, vals, 4);
err = ide_do_drive_cmd(drive, &rq, ide_wait);
if (!err && xfer_rate) {
......
drivers/ide/ide-tcq.c
View file @ 64d3cfb4
......@@ -51,21 +51,17 @@
*/
#undef IDE_TCQ_FIDDLE_SI
/*
* wait for data phase before starting DMA or not
*/
#undef IDE_TCQ_WAIT_DATAPHASE
ide_startstop_t ide_dmaq_intr(ide_drive_t *drive);
ide_startstop_t ide_service(ide_drive_t *drive);
static inline void drive_ctl_nien(ide_drive_t *drive, int clear)
{
#ifdef IDE_TCQ_NIEN
if (IDE_CONTROL_REG) {
int mask = clear ? 0x00 : 0x02;
if (IDE_CONTROL_REG)
OUT_BYTE(drive->ctl | mask, IDE_CONTROL_REG);
}
#endif
}
......@@ -123,7 +119,6 @@ static void ide_tcq_invalidate_queue(ide_drive_t *drive)
init_taskfile_request(ar->ar_rq);
ar->ar_rq->rq_dev = mk_kdev(drive->channel->major, (drive->select.b.unit)<<PARTN_BITS);
ar->ar_rq->special = ar;
ar->ar_flags |= ATA_AR_RETURN;
_elv_add_request(q, ar->ar_rq, 0, 0);
/*
......@@ -222,7 +217,7 @@ ide_startstop_t ide_service(ide_drive_t *drive)
{
struct ata_request *ar;
byte feat, stat;
int tag;
int tag, ret;
TCQ_PRINTK("%s: started service\n", drive->name);
......@@ -272,9 +267,6 @@ ide_startstop_t ide_service(ide_drive_t *drive)
return ide_stopped;
}
/*
* start dma
*/
tag = feat >> 3;
IDE_SET_CUR_TAG(drive, tag);
......@@ -293,16 +285,16 @@ ide_startstop_t ide_service(ide_drive_t *drive)
*/
if (rq_data_dir(ar->ar_rq) == READ) {
TCQ_PRINTK("ide_service: starting READ %x\n", stat);
drive->channel->dmaproc(ide_dma_read_queued, drive);
ret = drive->channel->dmaproc(ide_dma_read_queued, drive);
} else {
TCQ_PRINTK("ide_service: starting WRITE %x\n", stat);
drive->channel->dmaproc(ide_dma_write_queued, drive);
ret = drive->channel->dmaproc(ide_dma_write_queued, drive);
}
/*
* dmaproc set intr handler
*/
return ide_started;
return !ret ? ide_started : ide_stopped;
}
ide_startstop_t ide_check_service(ide_drive_t *drive)
......@@ -410,14 +402,15 @@ ide_startstop_t ide_dmaq_intr(ide_drive_t *drive)
*/
static int ide_tcq_configure(ide_drive_t *drive)
{
int tcq_mask = 1 << 1 | 1 << 14;
int tcq_bits = tcq_mask | 1 << 15;
struct ata_taskfile args;
int tcq_supp = 1 << 1 | 1 << 14;
/*
* bit 14 and 1 must be set in word 83 of the device id to indicate
* support for dma queued protocol
* support for dma queued protocol, and bit 15 must be cleared
*/
if ((drive->id->command_set_2 & tcq_supp) != tcq_supp)
if ((drive->id->command_set_2 & tcq_bits) ^ tcq_mask)
return -EIO;
memset(&args, 0, sizeof(args));
......@@ -477,10 +470,13 @@ static int ide_tcq_configure(ide_drive_t *drive)
*/
static int ide_enable_queued(ide_drive_t *drive, int on)
{
int depth = drive->using_tcq ? drive->queue_depth : 0;
/*
* disable or adjust queue depth
*/
if (!on) {
if (drive->using_tcq)
printk("%s: TCQ disabled\n", drive->name);
drive->using_tcq = 0;
return 0;
......@@ -491,25 +487,33 @@ static int ide_enable_queued(ide_drive_t *drive, int on)
return 1;
}
/*
* possibly expand command list
*/
if (ide_build_commandlist(drive))
return 1;
if (depth != drive->queue_depth)
printk("%s: tagged command queueing enabled, command queue depth %d\n", drive->name, drive->queue_depth);
drive->using_tcq = 1;
/*
* clear stats
*/
drive->tcq->max_depth = 0;
return 0;
}
int ide_tcq_wait_dataphase(ide_drive_t *drive)
{
#ifdef IDE_TCQ_WAIT_DATAPHASE
ide_startstop_t foo;
if (ide_wait_stat(&startstop, drive, READY_STAT | DRQ_STAT, BUSY_STAT, WAIT_READY)) {
if (ide_wait_stat(&foo, drive, READY_STAT | DRQ_STAT, BUSY_STAT, WAIT_READY)) {
printk("%s: timeout waiting for data phase\n", drive->name);
return 1;
}
#endif
return 0;
}
......@@ -595,6 +599,8 @@ int ide_tcq_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
if (ide_start_dma(hwif, drive, func))
return ide_stopped;
TCQ_PRINTK("IMMED in queued_start\n");
/*
* need to arm handler before starting dma engine,
* transfer could complete right away
......@@ -612,6 +618,8 @@ int ide_tcq_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
case ide_dma_queued_off:
enable_tcq = 0;
case ide_dma_queued_on:
if (enable_tcq && !drive->using_dma)
return 1;
return ide_enable_queued(drive, enable_tcq);
default:
break;
......
drivers/ide/ide.c
View file @ 64d3cfb4
......@@ -479,12 +479,9 @@ static void ata_pre_reset(ide_drive_t *drive)
if (ata_ops(drive) && ata_ops(drive)->pre_reset)
ata_ops(drive)->pre_reset(drive);
if (!drive->keep_settings && !drive->using_dma) {
drive->unmask = 0;
drive->io_32bit = 0;
}
if (!drive->using_dma)
return;
if (drive->using_dma) {
/* check the DMA crc count */
if (drive->crc_count) {
drive->channel->dmaproc(ide_dma_off_quietly, drive);
......@@ -494,7 +491,6 @@ static void ata_pre_reset(ide_drive_t *drive)
drive->channel->dmaproc(ide_dma_on, drive);
} else
drive->channel->dmaproc(ide_dma_off, drive);
}
}
/*
......@@ -807,7 +803,6 @@ void ide_end_drive_cmd(ide_drive_t *drive, byte stat, byte err)
args->hobfile.high_cylinder = IN_BYTE(IDE_HCYL_REG);
}
}
if (ar->ar_flags & ATA_AR_RETURN)
ata_ar_put(drive, ar);
}
......@@ -905,17 +900,15 @@ byte ide_dump_status (ide_drive_t *drive, const char *msg, byte stat)
*/
static void try_to_flush_leftover_data (ide_drive_t *drive)
{
int i = (drive->mult_count ? drive->mult_count : 1);
int i;
if (drive->type != ATA_DISK)
return;
while (i > 0) {
for (i = (drive->mult_count ? drive->mult_count : 1); i > 0; --i) {
u32 buffer[SECTOR_WORDS];
unsigned int count = (i > 1) ? 1 : i;
ata_read(drive, buffer, count * SECTOR_WORDS);
i -= count;
ata_read(drive, buffer, SECTOR_WORDS);
}
}
......@@ -999,7 +992,7 @@ void ide_cmd(ide_drive_t *drive, byte cmd, byte nsect, ide_handler_t *handler)
/*
* Invoked on completion of a special DRIVE_CMD.
*/
static ide_startstop_t drive_cmd_intr (ide_drive_t *drive)
static ide_startstop_t drive_cmd_intr(ide_drive_t *drive)
{
struct request *rq = HWGROUP(drive)->rq;
u8 *args = rq->buffer;
......@@ -1008,11 +1001,7 @@ static ide_startstop_t drive_cmd_intr (ide_drive_t *drive)
ide__sti(); /* local CPU only */
if ((stat & DRQ_STAT) && args && args[3]) {
int io_32bit = drive->io_32bit;
drive->io_32bit = 0;
ata_read(drive, &args[4], args[3] * SECTOR_WORDS);
drive->io_32bit = io_32bit;
while (((stat = GET_STAT()) & BUSY_STAT) && retries--)
udelay(100);
......@@ -1824,7 +1813,7 @@ void ide_intr(int irq, void *dev_id, struct pt_regs *regs)
del_timer(&hwgroup->timer);
spin_unlock(&ide_lock);
if (drive->unmask)
if (hwif->unmask)
ide__sti(); /* local CPU only */
startstop = handler(drive); /* service this interrupt, may set handler for next interrupt */
spin_lock_irq(&ide_lock);
......@@ -2572,14 +2561,10 @@ int ide_write_setting (ide_drive_t *drive, ide_settings_t *setting, int val)
static int set_io_32bit(struct ata_device *drive, int arg)
{
if (drive->no_io_32bit)
if (drive->channel->no_io_32bit)
return -EIO;
drive->io_32bit = arg;
#ifdef CONFIG_BLK_DEV_DTC2278
if (drive->channel->chipset == ide_dtc2278)
drive->channel->drives[!drive->select.b.unit].io_32bit = arg;
#endif
drive->channel->io_32bit = arg;
return 0;
}
......@@ -2613,11 +2598,10 @@ static int set_pio_mode (ide_drive_t *drive, int arg)
void ide_add_generic_settings (ide_drive_t *drive)
{
/* drive setting name read/write access read ioctl write ioctl data type min max mul_factor div_factor data pointer set function */
ide_add_setting(drive, "io_32bit", drive->no_io_32bit ? SETTING_READ : SETTING_RW, HDIO_GET_32BIT, HDIO_SET_32BIT, TYPE_BYTE, 0, 1 + (SUPPORT_VLB_SYNC << 1), 1, 1, &drive->io_32bit, set_io_32bit);
ide_add_setting(drive, "keepsettings", SETTING_RW, HDIO_GET_KEEPSETTINGS, HDIO_SET_KEEPSETTINGS, TYPE_BYTE, 0, 1, 1, 1, &drive->keep_settings, NULL);
ide_add_setting(drive, "io_32bit", drive->channel->no_io_32bit ? SETTING_READ : SETTING_RW, HDIO_GET_32BIT, HDIO_SET_32BIT, TYPE_BYTE, 0, 1 + (SUPPORT_VLB_SYNC << 1), 1, 1, &drive->channel->io_32bit, set_io_32bit);
ide_add_setting(drive, "pio_mode", SETTING_WRITE, -1, HDIO_SET_PIO_MODE, TYPE_BYTE, 0, 255, 1, 1, NULL, set_pio_mode);
ide_add_setting(drive, "slow", SETTING_RW, -1, -1, TYPE_BYTE, 0, 1, 1, 1, &drive->slow, NULL);
ide_add_setting(drive, "unmaskirq", drive->no_unmask ? SETTING_READ : SETTING_RW, HDIO_GET_UNMASKINTR, HDIO_SET_UNMASKINTR, TYPE_BYTE, 0, 1, 1, 1, &drive->unmask, NULL);
ide_add_setting(drive, "slow", SETTING_RW, -1, -1, TYPE_BYTE, 0, 1, 1, 1, &drive->channel->slow, NULL);
ide_add_setting(drive, "unmaskirq", drive->channel->no_unmask ? SETTING_READ : SETTING_RW, HDIO_GET_UNMASKINTR, HDIO_SET_UNMASKINTR, TYPE_BYTE, 0, 1, 1, 1, &drive->channel->unmask, NULL);
ide_add_setting(drive, "using_dma", SETTING_RW, HDIO_GET_DMA, HDIO_SET_DMA, TYPE_BYTE, 0, 1, 1, 1, &drive->using_dma, set_using_dma);
ide_add_setting(drive, "ide_scsi", SETTING_RW, -1, -1, TYPE_BYTE, 0, 1, 1, 1, &drive->scsi, NULL);
ide_add_setting(drive, "init_speed", SETTING_RW, -1, -1, TYPE_BYTE, 0, 69, 1, 1, &drive->init_speed, NULL);
......@@ -3182,7 +3166,7 @@ int __init ide_setup (char *s)
drive->autotune = 2;
goto done;
case -8: /* "slow" */
drive->slow = 1;
hwif->slow = 1;
goto done;
case -9: /* "flash" */
drive->ata_flash = 1;
......
drivers/ide/pdc202xx.c
View file @ 64d3cfb4
......@@ -1268,11 +1268,8 @@ void __init ide_init_pdc202xx(struct ata_channel *hwif)
#undef CONFIG_PDC202XX_32_UNMASK
#ifdef CONFIG_PDC202XX_32_UNMASK
hwif->drives[0].io_32bit = 1;
hwif->drives[1].io_32bit = 1;
hwif->drives[0].unmask = 1;
hwif->drives[1].unmask = 1;
hwif->io_32bit = 1;
hwif->unmask = 1;
#endif
#ifdef CONFIG_BLK_DEV_IDEDMA
......
drivers/ide/pdc4030.c
View file @ 64d3cfb4
......@@ -250,11 +250,9 @@ int __init setup_pdc4030(struct ata_channel *hwif)
memcpy(hwif2->io_ports, hwif->hw.io_ports, sizeof(hwif2->io_ports));
hwif2->irq = hwif->irq;
hwif2->hw.irq = hwif->hw.irq = hwif->irq;
hwif->io_32bit = 3;
hwif2->io_32bit = 3;
for (i=0; i<2 ; i++) {
hwif->drives[i].io_32bit = 3;
hwif2->drives[i].io_32bit = 3;
hwif->drives[i].keep_settings = 1;
hwif2->drives[i].keep_settings = 1;
if (!ident.current_tm[i].cyl)
hwif->drives[i].noprobe = 1;
if (!ident.current_tm[i+2].cyl)
......@@ -634,7 +632,7 @@ ide_startstop_t do_pdc4030_io(ide_drive_t *drive, struct ata_taskfile *task)
"PROMISE_WRITE\n", drive->name);
return startstop;
}
if (!drive->unmask)
if (!drive->channel->unmask)
__cli(); /* local CPU only */
HWGROUP(drive)->wrq = *rq; /* scratchpad */
return promise_write(drive);
......
drivers/ide/piix.c
View file @ 64d3cfb4
......@@ -545,10 +545,9 @@ void __init ide_init_piix(struct ata_channel *hwif)
hwif->tuneproc = &piix_tune_drive;
hwif->speedproc = &piix_set_drive;
hwif->autodma = 0;
hwif->io_32bit = 1;
hwif->unmask = 1;
for (i = 0; i < 2; i++) {
hwif->drives[i].io_32bit = 1;
hwif->drives[i].unmask = 1;
hwif->drives[i].autotune = 1;
hwif->drives[i].dn = hwif->unit * 2 + i;
}
......
drivers/ide/qd65xx.c
View file @ 64d3cfb4
......@@ -370,8 +370,7 @@ int __init probe (int base)
hwif->config_data = config;
hwif->drives[0].drive_data =
hwif->drives[1].drive_data = QD6500_DEF_DATA;
hwif->drives[0].io_32bit =
hwif->drives[1].io_32bit = 1;
hwif->io_32bit = 1;
hwif->tuneproc = &qd6500_tune_drive;
return 1;
}
......@@ -403,8 +402,7 @@ int __init probe (int base)
hwif->config_data = config | (control <<8);
hwif->drives[0].drive_data =
hwif->drives[1].drive_data = QD6580_DEF_DATA;
hwif->drives[0].io_32bit =
hwif->drives[1].io_32bit = 1;
hwif->io_32bit = 1;
hwif->tuneproc = &qd6580_tune_drive;
qd_write_reg(QD_DEF_CONTR,QD_CONTROL_PORT);
......@@ -426,11 +424,11 @@ int __init probe (int base)
ide_hwifs[i].select_data = base;
ide_hwifs[i].config_data = config | (control <<8);
ide_hwifs[i].tuneproc = &qd6580_tune_drive;
ide_hwifs[i].io_32bit = 1;
for (j = 0; j < 2; j++) {
ide_hwifs[i].drives[j].drive_data =
i?QD6580_DEF_DATA2:QD6580_DEF_DATA;
ide_hwifs[i].drives[j].io_32bit = 1;
}
}
......
drivers/ide/rz1000.c
View file @ 64d3cfb4
......@@ -40,8 +40,7 @@ void __init ide_init_rz1000(struct ata_channel *hwif) /* called from ide-pci.c *
printk("%s: disabled chipset read-ahead (buggy RZ1000/RZ1001)\n", hwif->name);
} else {
hwif->serialized = 1;
hwif->drives[0].no_unmask = 1;
hwif->drives[1].no_unmask = 1;
hwif->no_unmask = 1;
printk("%s: serialized, disabled unmasking (buggy RZ1000/RZ1001)\n", hwif->name);
}
}
......
drivers/ide/via82cxxx.c
View file @ 64d3cfb4
......@@ -535,10 +535,10 @@ void __init ide_init_via82cxxx(struct ata_channel *hwif)
hwif->tuneproc = &via82cxxx_tune_drive;
hwif->speedproc = &via_set_drive;
hwif->autodma = 0;
hwif->io_32bit = 1;
hwif->unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
for (i = 0; i < 2; i++) {
hwif->drives[i].io_32bit = 1;
hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
hwif->drives[i].autotune = 1;
hwif->drives[i].dn = hwif->unit * 2 + i;
}
......
drivers/net/wan/dscc4.c
View file @ 64d3cfb4
/*
* drivers/net/wan/dscc4/dscc4_main.c: a DSCC4 HDLC driver for Linux
* drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
*
* This software may be used and distributed according to the terms of the
* GNU General Public License.
......@@ -21,6 +21,7 @@
* - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
* 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
* - Application Hint "Management of DSCC4 on-chip FIFO resources".
* - Errata sheet DS5 (courtesy of Michael Skerritt).
* Jens David has built an adapter based on the same chipset. Take a look
* at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
* driver.
......@@ -37,15 +38,13 @@
*
* III. Driver operation
*
* The rx/tx operations are based on a linked list of descriptor. I haven't
* tried the start/stop descriptor method as this one looks like the cheapest
* in terms of PCI manipulation.
* The rx/tx operations are based on a linked list of descriptors. The driver
* doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
* I tried to fix it, the more it started to look like (convoluted) software
* mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
* this a rfc2119 MUST.
*
* Tx direction
* Once the data section of the current descriptor processed, the next linked
* descriptor is loaded if the HOLD bit isn't set in the current descriptor.
* If HOLD is met, the transmission is stopped until the host unsets it and
* signals the change via TxPOLL.
* When the tx ring is full, the xmit routine issues a call to netdev_stop.
* The device is supposed to be enabled again during an ALLS irq (we could
* use HI but as it's easy to loose events, it's fscked).
......@@ -55,12 +54,6 @@
* I may implement it some day but it isn't the highest ranked item.
*
* IV. Notes
* The chipset is buggy. Typically, under some specific load patterns (I
* wouldn't call them "high"), the irq queues and the descriptors look like
* some event has been lost. Even assuming some fancy PCI feature, it won't
* explain the reproductible missing "C" bit in the descriptors. Faking an
* irq in the periodic timer isn't really elegant but at least it seems
* reliable.
* The current error (XDU, RFO) recovery code is untested.
* So far, RDO takes his RX channel down and the right sequence to enable it
* again is still a mistery. If RDO happens, plan a reboot. More details
......@@ -69,7 +62,7 @@
* suggest it for DCE either but at least one can get some messages instead
* of a complete instant freeze.
* Tests are done on Rev. 20 of the silicium. The RDO handling changes with
* the documentation/chipset releases. An on-line errata would be welcome.
* the documentation/chipset releases.
*
* TODO:
* - test X25.
......@@ -115,14 +108,13 @@
#include <linux/hdlc.h>
/* Version */
static const char version[] = "$Id: dscc4.c,v 1.158 2002/01/30 00:40:37 romieu Exp $\n";
static const char version[] = "$Id: dscc4.c,v 1.159 2002/04/10 22:05:17 romieu Exp $ for Linux\n";
static int debug;
static int quartz;
#define DRV_NAME "dscc4"
#undef DSCC4_POLLING
#define DEBUG
/* Module parameters */
......@@ -148,7 +140,7 @@ struct TxFD {
u32 next;
u32 data;
u32 complete;
u32 jiffies; /* more hack to come :o) */
u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
};
struct RxFD {
......@@ -159,23 +151,24 @@ struct RxFD {
u32 end;
};
#define DEBUG
#define DEBUG_PARANOIA
#define DUMMY_SKB_SIZE 64
#define TX_LOW 8
#define TX_RING_SIZE 32
#define RX_RING_SIZE 32
#define IRQ_RING_SIZE 64 /* Keep it A multiple of 32 */
#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
#define TX_TIMEOUT (HZ/10)
#define DSCC4_HZ_MAX 33000000
#define BRR_DIVIDER_MAX 64*0x00008000
#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
#define dev_per_card 4
#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
#define SOURCE_ID(flags) (((flags) >> 28 ) & 0x03)
#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
#define TO_STATE(len) cpu_to_le32(((len) & TxSizeMax) << 16)
#define RX_MAX(len) ((((len) >> 5) + 1)<< 5)
#define SCC_REG_START(id) SCC_START+(id)*SCC_OFFSET
#undef DEBUG
#define RX_MAX(len) ((((len) >> 5) + 1) << 5)
#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
struct dscc4_pci_priv {
u32 *iqcfg;
......@@ -197,21 +190,24 @@ struct dscc4_dev_priv {
u32 *iqrx;
u32 *iqtx;
/* FIXME: check all the volatile are required */
volatile u32 tx_current;
u32 rx_current;
u32 tx_current;
u32 iqrx_current;
u32 iqtx_current;
u32 iqrx_current;
u32 tx_dirty;
int bad_tx_frame;
int bad_rx_frame;
int rx_needs_refill;
volatile u32 tx_dirty;
volatile u32 ltda;
u32 rx_dirty;
u32 lrda;
dma_addr_t tx_fd_dma;
dma_addr_t rx_fd_dma;
dma_addr_t iqtx_dma;
dma_addr_t iqrx_dma;
volatile u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
struct timer_list timer;
struct dscc4_pci_priv *pci_priv;
......@@ -220,13 +216,12 @@ struct dscc4_dev_priv {
int dev_id;
volatile u32 flags;
u32 timer_help;
u32 hi_expected;
hdlc_device hdlc;
sync_serial_settings settings;
unsigned short encoding;
unsigned short parity;
u32 pad __attribute__ ((aligned (4)));
hdlc_device hdlc;
sync_serial_settings settings;
u32 __pad __attribute__ ((aligned (4)));
};
/* GLOBAL registers definitions */
......@@ -245,6 +240,10 @@ struct dscc4_dev_priv {
#define CH0CFG 0x50
#define CH0BRDA 0x54
#define CH0BTDA 0x58
#define CH0FRDA 0x98
#define CH0FTDA 0xb0
#define CH0LRDA 0xc8
#define CH0LTDA 0xe0
/* SCC registers definitions */
#define SCC_START 0x0100
......@@ -279,11 +278,13 @@ struct dscc4_dev_priv {
#define Ccr0ClockMask 0x0000003f
#define Ccr1LoopMask 0x00000200
#define IsrMask 0x000fffff
#define BrrExpMask 0x00000f00
#define BrrMultMask 0x0000003f
#define EncodingMask 0x00700000
#define Hold 0x40000000
#define SccBusy 0x10000000
#define PowerUp 0x80000000
#define FrameOk (FrameVfr | FrameCrc)
#define FrameVfr 0x80
#define FrameRdo 0x40
......@@ -303,10 +304,12 @@ struct dscc4_dev_priv {
#define TxEvt 0x0f000000
#define Alls 0x00040000
#define Xdu 0x00010000
#define Cts 0x00004000
#define Xmr 0x00002000
#define Xpr 0x00001000
#define Rdo 0x00000080
#define Rfs 0x00000040
#define Cd 0x00000004
#define Rfo 0x00000002
#define Flex 0x00000001
......@@ -338,7 +341,7 @@ static void dscc4_timer(unsigned long);
static void dscc4_tx_timeout(struct net_device *);
static void dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs);
static int dscc4_hdlc_attach(hdlc_device *, unsigned short, unsigned short);
static int dscc4_set_iface(struct net_device *);
static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
static inline int dscc4_set_quartz(struct dscc4_dev_priv *, int);
#ifdef DSCC4_POLLING
static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
......@@ -349,40 +352,96 @@ static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
return list_entry(dev, struct dscc4_dev_priv, hdlc.netdev);
}
static inline void dscc4_patch_register(u32 ioaddr, u32 mask, u32 value)
static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
struct net_device *dev, int offset)
{
u32 state;
state = readl(ioaddr);
/* Cf scc_writel for concern regarding thread-safety */
state = dpriv->scc_regs[offset];
state &= ~mask;
state |= value;
writel(state, ioaddr);
dpriv->scc_regs[offset] = state;
writel(state, dev->base_addr + SCC_REG_START(dpriv) + offset);
}
static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
struct net_device *dev, int offset)
{
/*
* Thread-UNsafe.
* As of 2002/02/16, there are no thread racing for access.
*/
dpriv->scc_regs[offset] = bits;
writel(bits, dev->base_addr + SCC_REG_START(dpriv) + offset);
}
static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
{
return dpriv->scc_regs[offset];
}
static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
{
/* Cf errata DS5 p.4 */
readl(dev->base_addr + SCC_REG_START(dpriv) + STAR);
return readl(dev->base_addr + SCC_REG_START(dpriv) + STAR);
}
static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
dpriv->ltda = dpriv->tx_fd_dma +
((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
writel(dpriv->ltda, dev->base_addr + CH0LTDA + dpriv->dev_id*4);
/* Flush posted writes *NOW* */
readl(dev->base_addr + CH0LTDA + dpriv->dev_id*4);
}
int state_check(u32 state, struct dscc4_dev_priv *dpriv,
struct net_device *dev, const char *msg)
static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
#ifdef DEBUG_PARANOIA
dpriv->lrda = dpriv->rx_fd_dma +
((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
writel(dpriv->lrda, dev->base_addr + CH0LRDA + dpriv->dev_id*4);
}
static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
{
return dpriv->tx_current == dpriv->tx_dirty;
}
static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
return readl(dev->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
}
int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev,
const char *msg)
{
int ret = 0;
if (debug > 1) {
if (SOURCE_ID(state) != dpriv->dev_id) {
printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
dev->name, msg, SOURCE_ID(state), state );
return -1;
ret = -1;
}
if (state & 0x0df80c00) {
printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
dev->name, msg, state);
return -1;
ret = -1;
}
return 0;
#else
return 1;
#endif
}
return ret;
}
void inline reset_TxFD(struct TxFD *tx_fd) {
/* FIXME: test with the last arg (size specification) = 0 */
tx_fd->state = FrameEnd | Hold | 0x00100000;
tx_fd->complete = 0x00000000;
void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv,
char *msg)
{
printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
}
static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
......@@ -393,10 +452,8 @@ static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
struct sk_buff **skbuff;
int i;
pci_free_consistent(pdev, TX_RING_SIZE*sizeof(struct TxFD), tx_fd,
dpriv->tx_fd_dma);
pci_free_consistent(pdev, RX_RING_SIZE*sizeof(struct RxFD), rx_fd,
dpriv->rx_fd_dma);
pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
skbuff = dpriv->tx_skbuff;
for (i = 0; i < TX_RING_SIZE; i++) {
......@@ -421,96 +478,145 @@ static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
}
}
void inline try_get_rx_skb(struct dscc4_dev_priv *priv, int cur, struct net_device *dev)
inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev)
{
unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
struct RxFD *rx_fd = dpriv->rx_fd + dirty;
struct sk_buff *skb;
int ret = 0;
skb = dev_alloc_skb(RX_MAX(HDLC_MAX_MRU));
priv->rx_skbuff[cur] = skb;
if (!skb) {
priv->rx_fd[cur--].data = (u32) NULL;
priv->rx_fd[cur%RX_RING_SIZE].state1 |= Hold;
priv->rx_needs_refill++;
return;
}
dpriv->rx_skbuff[dirty] = skb;
if (skb) {
skb->dev = dev;
skb->protocol = htons(ETH_P_IP);
skb->mac.raw = skb->data;
priv->rx_fd[cur].data = pci_map_single(priv->pci_priv->pdev, skb->data,
rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
skb->len, PCI_DMA_FROMDEVICE);
} else {
rx_fd->data = (u32) NULL;
ret = -1;
}
return ret;
}
/*
* IRQ/thread/whatever safe
*/
static int dscc4_wait_ack_cec(u32 ioaddr, struct net_device *dev, char *msg)
static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
struct net_device *dev, char *msg)
{
s16 i = 0;
s8 i = 0;
while (readl(ioaddr + STAR) & SccBusy) {
if (i++ < 0) {
printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
return -1;
do {
if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
msg, i);
goto done;
}
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(10);
rmb();
}
printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name, msg, i);
return 0;
} while (++i > 0);
printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
done:
return (i >= 0) ? i : -EAGAIN;
}
static int dscc4_do_action(struct net_device *dev, char *msg)
{
unsigned long ioaddr = dev->base_addr;
u32 state;
s16 i;
s16 i = 0;
writel(Action, ioaddr + GCMDR);
ioaddr += GSTAR;
for (i = 0; i >= 0; i++) {
state = readl(ioaddr);
if (state & Arf) {
do {
u32 state = readl(ioaddr);
if (state & ArAck) {
printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
writel(ArAck, ioaddr);
goto done;
} else if (state & Arf) {
printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
writel(Arf, ioaddr);
return -1;
} else if (state & ArAck) {
printk(KERN_DEBUG "%s: %s ack (%d try)\n",
dev->name, msg, i);
writel(ArAck, ioaddr);
return 0;
}
i = -1;
goto done;
}
rmb();
} while (++i > 0);
printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
return -1;
done:
return i;
}
static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
{
int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
s16 i = 0;
s8 i = 0;
do {
if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
(dpriv->iqtx[cur] & Xpr))
break;
smp_rmb();
} while (i++ >= 0);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(10);
} while (++i > 0);
return i;
return (i >= 0 ) ? i : -EAGAIN;
}
/* Requires protection against interrupt */
static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
{
/* Cf errata DS5 p.6 */
writel(0x00000000, dev->base_addr + CH0LRDA + dpriv->dev_id*4);
scc_writel(~PowerUp & scc_readl(dpriv, CCR0), dpriv, dev, CCR0);
readl(dev->base_addr + CH0LRDA + dpriv->dev_id*4);
writel(MTFi|Rdr, dev->base_addr + dpriv->dev_id*0x0c + CH0CFG);
writel(Action, dev->base_addr + GCMDR);
}
static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
{
u16 i = 0;
/* Cf errata DS5 p.7 */
scc_writel(~PowerUp & scc_readl(dpriv, CCR0), dpriv, dev, CCR0);
scc_writel(0x00050000, dpriv, dev, CCR2);
/*
* Must be longer than the time required to fill the fifo.
*/
while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
udelay(1);
wmb();
}
writel(MTFi|Rdt, dev->base_addr + dpriv->dev_id*0x0c + CH0CFG);
if (dscc4_do_action(dev, "Rdt") < 0)
printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
}
static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, int cur,
struct RxFD *rx_fd, struct net_device *dev)
/* TODO: (ab)use this function to refill a completely depleted RX ring. */
static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
struct net_device_stats *stats = &dev_to_hdlc(dev)->stats;
struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
struct net_device_stats *stats = &dpriv->hdlc.stats;
struct pci_dev *pdev = dpriv->pci_priv->pdev;
struct sk_buff *skb;
int pkt_len;
skb = dpriv->rx_skbuff[cur];
skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
if (!skb) {
printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__);
goto refill;
}
pkt_len = TO_SIZE(rx_fd->state2);
pci_dma_sync_single(pdev, rx_fd->data, pkt_len, PCI_DMA_FROMDEVICE);
if((skb->data[--pkt_len] & FrameOk) == FrameOk) {
pci_unmap_single(pdev, rx_fd->data, skb->len, PCI_DMA_FROMDEVICE);
pci_unmap_single(pdev, rx_fd->data, pkt_len, PCI_DMA_FROMDEVICE);
if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
stats->rx_packets++;
stats->rx_bytes += pkt_len;
skb->tail += pkt_len;
......@@ -519,29 +625,29 @@ static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, int cur,
skb->protocol = htons(ETH_P_HDLC);
skb->dev->last_rx = jiffies;
netif_rx(skb);
try_get_rx_skb(dpriv, cur, dev);
} else {
if(skb->data[pkt_len] & FrameRdo)
if (skb->data[pkt_len] & FrameRdo)
stats->rx_fifo_errors++;
else if(!(skb->data[pkt_len] | ~FrameCrc))
else if (!(skb->data[pkt_len] | ~FrameCrc))
stats->rx_crc_errors++;
else if(!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
stats->rx_length_errors++;
else
stats->rx_errors++;
dev_kfree_skb_irq(skb);
}
rx_fd->state1 |= Hold;
refill:
while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
if (try_get_rx_skb(dpriv, dev) < 0)
break;
dpriv->rx_dirty++;
}
dscc4_rx_update(dpriv, dev);
rx_fd->state2 = 0x00000000;
rx_fd->end = 0xbabeface;
if (!rx_fd->data)
return;
rx_fd--;
if (!cur)
rx_fd += RX_RING_SIZE;
rx_fd->state1 &= ~Hold;
}
static int __init dscc4_init_one (struct pci_dev *pdev,
static int __init dscc4_init_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct dscc4_pci_priv *priv;
......@@ -578,8 +684,8 @@ static int __init dscc4_init_one (struct pci_dev *pdev,
pci_resource_start(pdev, 0),
pci_resource_start(pdev, 1), pdev->irq);
/* No need for High PCI latency. Cf app. note. */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x10);
/* Cf errata DS5 p.2 */
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
pci_set_master(pdev);
if (dscc4_found1(pdev, ioaddr))
......@@ -592,8 +698,8 @@ static int __init dscc4_init_one (struct pci_dev *pdev,
goto err_out_iounmap;
}
/* power up/little endian/dma core controlled via hold bit */
writel(0x00000000, ioaddr + GMODE);
/* power up/little endian/dma core controlled via lrda/ltda */
writel(0x00000001, ioaddr + GMODE);
/* Shared interrupt queue */
{
u32 bits;
......@@ -680,28 +786,32 @@ static int __init dscc4_init_one (struct pci_dev *pdev,
* Let's hope the default values are decent enough to protect my
* feet from the user's gun - Ueimor
*/
static void dscc4_init_registers(u32 base_addr, int dev_id)
static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
u32 ioaddr = base_addr + SCC_REG_START(dev_id);
scc_writel(0x80001000, dpriv, dev, CCR0);
writel(0x80001000, ioaddr + CCR0);
scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
writel(LengthCheck | (HDLC_MAX_MRU >> 5), ioaddr + RLCR);
/* no address recognition/crc-CCITT/cts enabled */
writel(0x021c8000, ioaddr + CCR1);
/*
* No address recognition/crc-CCITT/cts enabled
* Shared flags transmission disabled - cf errata DS5 p.11
* Carrier detect disabled - cf errata p.14
*/
scc_writel(0x021c8000, dpriv, dev, CCR1);
/* crc not forwarded */
writel(0x00050008 & ~RxActivate, ioaddr + CCR2);
/* crc not forwarded - Cf errata DS5 p.11 */
scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
// crc forwarded
//writel(0x00250008 & ~RxActivate, ioaddr + CCR2);
//scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
/* Don't mask RDO. Ever. */
#ifdef DSCC4_POLLING
writel(0xfffeef7f, ioaddr + IMR); /* Interrupt mask */
scc_writel(0xfffeef7f, dpriv, dev, IMR); /* Interrupt mask */
#else
//writel(0xfffaef7f, ioaddr + IMR); /* Interrupt mask */
writel(0xfffaef7e, ioaddr + IMR); /* Interrupt mask */
//scc_writel(0xfffaef7f, dpriv, dev, IMR); /* Interrupt mask */
//scc_writel(0xfffaef7e, dpriv, dev, IMR); /* Interrupt mask */
scc_writel(0xfffa8f7a, dpriv, dev, IMR); /* Interrupt mask */
#endif
}
......@@ -754,7 +864,7 @@ static int dscc4_found1(struct pci_dev *pdev, unsigned long ioaddr)
}
hdlc->proto = IF_PROTO_HDLC;
SET_MODULE_OWNER(d);
dscc4_init_registers(ioaddr, i);
dscc4_init_registers(dpriv, d);
dpriv->parity = PARITY_CRC16_PR0_CCITT;
dpriv->encoding = ENCODING_NRZ;
}
......@@ -775,54 +885,15 @@ static int dscc4_found1(struct pci_dev *pdev, unsigned long ioaddr)
return -1;
};
/* FIXME: get rid of the unneeded code */
static void dscc4_timer(unsigned long data)
{
struct net_device *dev = (struct net_device *)data;
struct dscc4_dev_priv *dpriv;
struct dscc4_pci_priv *ppriv;
dpriv = dscc4_priv(dev);
if (netif_queue_stopped(dev) &&
((jiffies - dev->trans_start) > TX_TIMEOUT)) {
ppriv = dpriv->pci_priv;
if (dpriv->iqtx[dpriv->iqtx_current%IRQ_RING_SIZE]) {
u32 flags;
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
// struct dscc4_pci_priv *ppriv;
printk(KERN_DEBUG "%s: pending events\n", dev->name);
dev->trans_start = jiffies;
spin_lock_irqsave(&ppriv->lock, flags);
dscc4_tx_irq(ppriv, dpriv);
spin_unlock_irqrestore(&ppriv->lock, flags);
} else {
struct TxFD *tx_fd;
struct sk_buff *skb;
int i,j;
printk(KERN_DEBUG "%s: missing events\n", dev->name);
i = dpriv->tx_dirty%TX_RING_SIZE;
j = dpriv->tx_current - dpriv->tx_dirty;
dev_to_hdlc(dev)->stats.tx_dropped += j;
while(j--) {
skb = dpriv->tx_skbuff[i];
tx_fd = dpriv->tx_fd + i;
if (skb) {
dpriv->tx_skbuff[i] = NULL;
pci_unmap_single(ppriv->pdev, tx_fd->data, skb->len,
PCI_DMA_TODEVICE);
dev_kfree_skb_irq(skb);
} else
printk(KERN_INFO "%s: hardware on drugs!\n", dev->name);
tx_fd->data = 0; /* DEBUG */
tx_fd->complete &= ~DataComplete;
i++;
i %= TX_RING_SIZE;
}
dpriv->tx_dirty = dpriv->tx_current;
dev->trans_start = jiffies;
netif_wake_queue(dev);
printk(KERN_DEBUG "%s: re-enabled\n", dev->name);
}
}
goto done;
done:
dpriv->timer.expires = jiffies + TX_TIMEOUT;
add_timer(&dpriv->timer);
}
......@@ -850,7 +921,6 @@ static int dscc4_open(struct net_device *dev)
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
hdlc_device *hdlc = &dpriv->hdlc;
struct dscc4_pci_priv *ppriv;
u32 ioaddr;
int ret = -EAGAIN;
if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit)
......@@ -863,11 +933,9 @@ static int dscc4_open(struct net_device *dev)
ppriv = dpriv->pci_priv;
if (dscc4_init_ring(dev))
if ((ret = dscc4_init_ring(dev)))
goto err_out;
ioaddr = dev->base_addr + SCC_REG_START(dpriv->dev_id);
/* IDT+IDR during XPR */
dpriv->flags = NeedIDR | NeedIDT;
......@@ -878,15 +946,17 @@ static int dscc4_open(struct net_device *dev)
* power-down mode or..." and CCR2.RAC = 1 are two different
* situations.
*/
if (readl(ioaddr + STAR) & SccBusy) {
if (scc_readl_star(dpriv, dev) & SccBusy) {
printk(KERN_ERR "%s busy. Try later\n", dev->name);
ret = -EAGAIN;
goto err_free_ring;
}
} else
printk(KERN_INFO "%s: available. Good\n", dev->name);
/* Posted write is flushed in the busy-waiting loop */
writel(TxSccRes | RxSccRes, ioaddr + CMDR);
/* Posted write is flushed in the wait_ack loop */
scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
if (dscc4_wait_ack_cec(ioaddr, dev, "Cec"))
if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
goto err_free_ring;
/*
......@@ -896,11 +966,14 @@ static int dscc4_open(struct net_device *dev)
* WARNING, a really missing XPR usually means a hardware
* reset is needed. Suggestions anyone ?
*/
if (dscc4_xpr_ack(dpriv) < 0) {
if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
goto err_free_ring;
}
if (debug > 2)
dscc4_tx_print(dev, dpriv, "Open");
netif_start_queue(dev);
init_timer(&dpriv->timer);
......@@ -931,70 +1004,55 @@ static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
struct dscc4_pci_priv *ppriv;
struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
struct TxFD *tx_fd;
int cur, next;
int next;
ppriv = dpriv->pci_priv;
cur = dpriv->tx_current++%TX_RING_SIZE;
next = dpriv->tx_current%TX_RING_SIZE;
dpriv->tx_skbuff[next] = skb;
tx_fd = dpriv->tx_fd + next;
tx_fd->state = FrameEnd | Hold | TO_STATE(skb->len);
tx_fd->state = FrameEnd | TO_STATE(skb->len);
tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len,
PCI_DMA_TODEVICE);
tx_fd->complete = 0x00000000;
mb(); // FIXME: suppress ?
tx_fd->jiffies = jiffies;
mb();
#ifdef DSCC4_POLLING
spin_lock(&dpriv->lock);
while(dscc4_tx_poll(dpriv, dev));
while (dscc4_tx_poll(dpriv, dev));
spin_unlock(&dpriv->lock);
#endif
/*
* I know there's a window for a race in the following lines but
* dscc4_timer will take good care of it. The chipset eats events
* (especially the net_dev re-enabling ones) thus there is no
* reason to try and be smart.
*/
if ((dpriv->tx_dirty + 16) < dpriv->tx_current) {
netif_stop_queue(dev);
dpriv->hi_expected = 2;
}
tx_fd = dpriv->tx_fd + cur;
tx_fd->state &= ~Hold;
mb(); // FIXME: suppress ?
/*
* One may avoid some pci transactions during intense TX periods.
* Not sure it's worth the pain...
*/
writel((TxPollCmd << dpriv->dev_id) | NoAck, dev->base_addr + GCMDR);
dev->trans_start = jiffies;
if (debug > 2)
dscc4_tx_print(dev, dpriv, "Xmit");
/* To be cleaned(unsigned int)/optimized. Later, ok ? */
if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
netif_stop_queue(dev);
if (dscc4_tx_quiescent(dpriv, dev))
dscc4_do_tx(dpriv, dev);
return 0;
}
static int dscc4_close(struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
u32 ioaddr = dev->base_addr;
int dev_id;
hdlc_device *hdlc = dev_to_hdlc(dev);
unsigned long flags;
del_timer_sync(&dpriv->timer);
netif_stop_queue(dev);
dev_id = dpriv->dev_id;
spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
dscc4_rx_reset(dpriv, dev);
spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
writel(0x00050000, ioaddr + SCC_REG_START(dev_id) + CCR2);
writel(MTFi|Rdr|Rdt, ioaddr + CH0CFG + dev_id*0x0c); /* Reset Rx/Tx */
writel(0x00000001, ioaddr + GCMDR);
readl(ioaddr + GCMDR);
dscc4_tx_reset(dpriv, dev);
/*
* FIXME: wait for the command ack before returning the memory
* structures to the kernel.
*/
hdlc_close(hdlc);
dscc4_release_ring(dpriv);
......@@ -1016,6 +1074,7 @@ static inline int dscc4_check_clock_ability(int port)
static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
int ret = -1;
u32 brr;
*state &= ~Ccr0ClockMask;
......@@ -1025,9 +1084,9 @@ static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
xtal = dpriv->pci_priv->xtal_hz;
if (!xtal)
return -1;
goto done;
if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
return -1;
goto done;
divider = xtal / *bps;
if (divider > BRR_DIVIDER_MAX) {
divider >>= 4;
......@@ -1059,9 +1118,10 @@ static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
*/
brr = 0;
}
writel(brr, dev->base_addr + BRR + SCC_REG_START(dpriv->dev_id));
return 0;
scc_writel(brr, dpriv, dev, BRR);
ret = 0;
done:
return ret;
}
static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
......@@ -1085,12 +1145,12 @@ static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
break;
case IF_IFACE_SYNC_SERIAL:
if(!capable(CAP_NET_ADMIN))
if (!capable(CAP_NET_ADMIN))
return -EPERM;
if (copy_from_user(&dpriv->settings, &line->sync, size))
return -EFAULT;
ret = dscc4_set_iface(dev);
ret = dscc4_set_iface(dpriv, dev);
break;
default:
......@@ -1127,36 +1187,37 @@ static int dscc4_match(struct thingie *p, int value)
return i;
}
static int dscc4_clock_setting(struct net_device *dev)
static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
sync_serial_settings *settings = &dpriv->settings;
int ret = -EOPNOTSUPP;
u32 bps, state;
u32 ioaddr;
bps = settings->clock_rate;
ioaddr = dev->base_addr + CCR0 + SCC_REG_START(dpriv->dev_id);
state = readl(ioaddr);
if(dscc4_set_clock(dev, &bps, &state) < 0)
return -EOPNOTSUPP;
state = scc_readl(dpriv, CCR0);
if (dscc4_set_clock(dev, &bps, &state) < 0)
goto done;
if (bps) { /* DCE */
printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
if (settings->clock_rate != bps) {
settings->clock_rate = bps;
printk(KERN_DEBUG "%s: clock adjusted from %08d to %08d \n",
printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
dev->name, dpriv->settings.clock_rate, bps);
}
} else { /* DTE */
state = 0x80001000;
printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
}
writel(state, ioaddr);
return 0;
scc_writel(state, dpriv, dev, CCR0);
ret = 0;
done:
return ret;
}
static int dscc4_encoding_setting(struct net_device *dev)
static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
struct thingie encoding[] = {
{ ENCODING_NRZ, 0x00000000 },
{ ENCODING_NRZI, 0x00200000 },
......@@ -1168,24 +1229,20 @@ static int dscc4_encoding_setting(struct net_device *dev)
int i, ret = 0;
i = dscc4_match(encoding, dpriv->encoding);
if (i >= 0) {
u32 ioaddr;
ioaddr = dev->base_addr + CCR0 + SCC_REG_START(dpriv->dev_id);
dscc4_patch_register(ioaddr, EncodingMask, encoding[i].bits);
} else
if (i >= 0)
scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
else
ret = -EOPNOTSUPP;
return ret;
}
static int dscc4_loopback_setting(struct net_device *dev)
static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
sync_serial_settings *settings = &dpriv->settings;
u32 ioaddr, state;
u32 state;
ioaddr = dev->base_addr + CCR1 + SCC_REG_START(dpriv->dev_id);
state = readl(ioaddr);
state = scc_readl(dpriv, CCR1);
if (settings->loopback) {
printk(KERN_DEBUG "%s: loopback\n", dev->name);
state |= 0x00000100;
......@@ -1193,13 +1250,13 @@ static int dscc4_loopback_setting(struct net_device *dev)
printk(KERN_DEBUG "%s: normal\n", dev->name);
state &= ~0x00000100;
}
writel(state, ioaddr);
scc_writel(state, dpriv, dev, CCR1);
return 0;
}
static int dscc4_crc_setting(struct net_device *dev)
static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
struct thingie crc[] = {
{ PARITY_CRC16_PR0_CCITT, 0x00000010 },
{ PARITY_CRC16_PR1_CCITT, 0x00000000 },
......@@ -1209,20 +1266,17 @@ static int dscc4_crc_setting(struct net_device *dev)
int i, ret = 0;
i = dscc4_match(crc, dpriv->parity);
if (i >= 0) {
u32 ioaddr;
ioaddr = dev->base_addr + CCR1 + SCC_REG_START(dpriv->dev_id);
dscc4_patch_register(ioaddr, CrcMask, crc[i].bits);
} else
if (i >= 0)
scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
else
ret = -EOPNOTSUPP;
return ret;
}
static int dscc4_set_iface(struct net_device *dev)
static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
{
struct {
int (*action)(struct net_device *);
int (*action)(struct dscc4_dev_priv *, struct net_device *);
} *p, do_setting[] = {
{ dscc4_encoding_setting },
{ dscc4_clock_setting },
......@@ -1233,7 +1287,7 @@ static int dscc4_set_iface(struct net_device *dev)
int ret = 0;
for (p = do_setting; p->action; p++) {
if ((ret = p->action(dev)) < 0)
if ((ret = p->action(dpriv, dev)) < 0)
break;
}
return ret;
......@@ -1267,8 +1321,8 @@ static void dscc4_irq(int irq, void *token, struct pt_regs *ptregs)
}
state &= ~ArAck;
if (state & Cfg) {
if (debug)
printk(KERN_DEBUG "CfgIV\n");
if (debug > 0)
printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf)
printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
if (!(state &= ~Cfg))
......@@ -1292,7 +1346,8 @@ static void dscc4_irq(int irq, void *token, struct pt_regs *ptregs)
spin_unlock_irqrestore(&priv->lock, flags);
}
static inline void dscc4_tx_irq(struct dscc4_pci_priv *ppriv, struct dscc4_dev_priv *dpriv)
static inline void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
struct dscc4_dev_priv *dpriv)
{
struct net_device *dev = hdlc_to_dev(&dpriv->hdlc);
u32 state;
......@@ -1302,70 +1357,64 @@ static inline void dscc4_tx_irq(struct dscc4_pci_priv *ppriv, struct dscc4_dev_p
cur = dpriv->iqtx_current%IRQ_RING_SIZE;
state = dpriv->iqtx[cur];
if (!state) {
#ifdef DEBUG
if (loop > 1)
if ((debug > 1) && (loop > 1))
printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
#endif
if (loop && netif_queue_stopped(dev))
if ((dpriv->tx_dirty + 8) >= dpriv->tx_current)
if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
netif_wake_queue(dev);
if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
!dscc4_tx_done(dpriv))
dscc4_do_tx(dpriv, dev);
return;
}
loop++;
dpriv->iqtx[cur] = 0;
dpriv->iqtx_current++;
if (state_check(state, dpriv, dev, "Tx"))
if (state_check(state, dpriv, dev, "Tx") < 0)
return;
// state &= 0x0fffffff; /* Tracking the analyzed bits */
if (state & SccEvt) {
if (state & Alls) {
struct TxFD *tx_fd;
struct net_device_stats *stats = &dpriv->hdlc.stats;
struct sk_buff *skb;
struct TxFD *tx_fd;
if (debug > 2)
dscc4_tx_print(dev, dpriv, "Alls");
/*
* DataComplete can't be trusted for Tx completion.
* Cf errata DS5 p.8
*/
cur = dpriv->tx_dirty%TX_RING_SIZE;
tx_fd = dpriv->tx_fd + cur;
skb = dpriv->tx_skbuff[cur];
/* XXX: hideous kludge - to be removed "later" */
if (!skb) {
printk(KERN_ERR "%s: NULL skb in tx_irq at index %d\n", dev->name, cur);
goto try;
}
dpriv->tx_dirty++; // MUST be after skb test
/* Happens sometime. Don't know what triggers it */
if (!(tx_fd->complete & DataComplete)) {
u32 ioaddr, isr;
ioaddr = dev->base_addr +
SCC_REG_START(dpriv->dev_id) + ISR;
isr = readl(ioaddr);
printk(KERN_DEBUG
"%s: DataComplete=0 cur=%d isr=%08x state=%08x\n",
dev->name, cur, isr, state);
writel(isr, ioaddr);
dev_to_hdlc(dev)->stats.tx_dropped++;
} else {
tx_fd->complete &= ~DataComplete;
if (skb) {
pci_unmap_single(ppriv->pdev, tx_fd->data,
skb->len, PCI_DMA_TODEVICE);
if (tx_fd->state & FrameEnd) {
dev_to_hdlc(dev)->stats.tx_packets++;
dev_to_hdlc(dev)->stats.tx_bytes += skb->len;
stats->tx_packets++;
stats->tx_bytes += skb->len;
}
dev_kfree_skb_irq(skb);
dpriv->tx_skbuff[cur] = NULL;
++dpriv->tx_dirty;
} else {
if (debug > 1)
printk(KERN_ERR "%s Tx: NULL skb %d\n",
dev->name, cur);
}
/*
* If the driver ends sending crap on the wire, it
* will be way easier to diagnose than the (not so)
* random freeze induced by null sized tx frames.
*/
tx_fd->data = tx_fd->next;
tx_fd->state = FrameEnd | TO_STATE(2*DUMMY_SKB_SIZE);
tx_fd->complete = 0x00000000;
tx_fd->jiffies = 0;
dpriv->tx_skbuff[cur] = NULL;
pci_unmap_single(ppriv->pdev, tx_fd->data, skb->len,
PCI_DMA_TODEVICE);
tx_fd->data = 0; /* DEBUG */
dev_kfree_skb_irq(skb);
{ // DEBUG
cur = (dpriv->tx_dirty-1)%TX_RING_SIZE;
tx_fd = dpriv->tx_fd + cur;
tx_fd->state |= Hold;
}
if (!(state &= ~Alls))
goto try;
}
......@@ -1378,66 +1427,73 @@ static inline void dscc4_tx_irq(struct dscc4_pci_priv *ppriv, struct dscc4_dev_p
/* Tx reset */
writel(MTFi | Rdt,
dev->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
writel(0x00000001, dev->base_addr + GCMDR);
writel(Action, dev->base_addr + GCMDR);
return;
}
if (state & Cts) {
printk(KERN_INFO "%s: CTS transition\n", dev->name);
if (!(state &= ~Cts)) /* DEBUG */
goto try;
}
if (state & Xmr) {
/* Frame needs to be sent again - FIXME */
//dscc4_start_xmit(dpriv->tx_skbuff[dpriv->tx_dirty], dev);
if (!(state &= ~0x00002000)) /* DEBUG */
printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
if (!(state &= ~Xmr)) /* DEBUG */
goto try;
}
if (state & Xpr) {
unsigned long ioaddr = dev->base_addr;
unsigned long scc_offset;
u32 scc_addr;
u32 scc_addr, ring;
scc_offset = ioaddr + SCC_REG_START(dpriv->dev_id);
scc_addr = ioaddr + 0x0c*dpriv->dev_id;
if (readl(scc_offset + STAR) & SccBusy)
printk(KERN_DEBUG "%s busy. Fatal\n",
dev->name);
/*
* Keep this order: IDT before IDR
*/
if (scc_readl_star(dpriv, dev) & SccBusy)
printk(KERN_ERR "%s busy. Fatal\n", dev->name);
scc_addr = dev->base_addr + 0x0c*dpriv->dev_id;
/* Keep this order: IDT before IDR */
if (dpriv->flags & NeedIDT) {
writel(MTFi | Idt, scc_addr + CH0CFG);
writel(dpriv->tx_fd_dma +
if (debug > 2)
dscc4_tx_print(dev, dpriv, "Xpr");
ring = dpriv->tx_fd_dma +
(dpriv->tx_dirty%TX_RING_SIZE)*
sizeof(struct TxFD), scc_addr + CH0BTDA);
if(dscc4_do_action(dev, "IDT"))
sizeof(struct TxFD);
writel(ring, scc_addr + CH0BTDA);
dscc4_do_tx(dpriv, dev);
writel(MTFi | Idt, scc_addr + CH0CFG);
if (dscc4_do_action(dev, "IDT") < 0)
goto err_xpr;
dpriv->flags &= ~NeedIDT;
mb();
}
if (dpriv->flags & NeedIDR) {
writel(MTFi | Idr, scc_addr + CH0CFG);
writel(dpriv->rx_fd_dma +
ring = dpriv->rx_fd_dma +
(dpriv->rx_current%RX_RING_SIZE)*
sizeof(struct RxFD), scc_addr + CH0BRDA);
if(dscc4_do_action(dev, "IDR"))
sizeof(struct RxFD);
writel(ring, scc_addr + CH0BRDA);
dscc4_rx_update(dpriv, dev);
writel(MTFi | Idr, scc_addr + CH0CFG);
if (dscc4_do_action(dev, "IDR") < 0)
goto err_xpr;
dpriv->flags &= ~NeedIDR;
mb();
smp_wmb();
/* Activate receiver and misc */
writel(0x08050008, scc_offset + CCR2);
scc_writel(0x08050008, dpriv, dev, CCR2);
}
err_xpr:
if (!(state &= ~Xpr))
goto try;
}
if (state & Cd) {
printk(KERN_INFO "%s: CD transition\n", dev->name);
if (!(state &= ~Cd)) /* DEBUG */
goto try;
}
} else { /* ! SccEvt */
if (state & Hi) {
#ifdef DSCC4_POLLING
while(!dscc4_tx_poll(dpriv, dev));
while (!dscc4_tx_poll(dpriv, dev));
#endif
printk(KERN_INFO "%s: Tx Hi\n", dev->name);
state &= ~Hi;
}
/*
* FIXME: it may be avoided. Re-re-re-read the manual.
*/
if (state & Err) {
printk(KERN_ERR "%s (Tx): ERR\n", dev->name);
printk(KERN_INFO "%s: Tx ERR\n", dev->name);
dev_to_hdlc(dev)->stats.tx_errors++;
state &= ~Err;
}
......@@ -1460,7 +1516,7 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
dpriv->iqrx[cur] = 0;
dpriv->iqrx_current++;
if (state_check(state, dpriv, dev, "Tx"))
if (state_check(state, dpriv, dev, "Rx") < 0)
return;
if (!(state & SccEvt)){
......@@ -1468,8 +1524,8 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
state &= 0x00ffffff;
if (state & Err) { /* Hold or reset */
printk(KERN_DEBUG "%s (Rx): ERR\n", dev->name);
cur = dpriv->rx_current;
printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
cur = dpriv->rx_current%RX_RING_SIZE;
rx_fd = dpriv->rx_fd + cur;
/*
* Presume we're not facing a DMAC receiver reset.
......@@ -1482,15 +1538,15 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
* problem with latency. In this case, increasing
* RX_RING_SIZE may help.
*/
while (dpriv->rx_needs_refill) {
while(!(rx_fd->state1 & Hold)) {
//while (dpriv->rx_needs_refill) {
while (!(rx_fd->state1 & Hold)) {
rx_fd++;
cur++;
if (!(cur = cur%RX_RING_SIZE))
rx_fd = dpriv->rx_fd;
}
dpriv->rx_needs_refill--;
try_get_rx_skb(dpriv, cur, dev);
//dpriv->rx_needs_refill--;
try_get_rx_skb(dpriv, dev);
if (!rx_fd->data)
goto try;
rx_fd->state1 &= ~Hold;
......@@ -1500,64 +1556,64 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
goto try;
}
if (state & Fi) {
cur = dpriv->rx_current%RX_RING_SIZE;
rx_fd = dpriv->rx_fd + cur;
dscc4_rx_skb(dpriv, cur, rx_fd, dev);
dpriv->rx_current++;
dscc4_rx_skb(dpriv, dev);
goto try;
}
if (state & Hi ) { /* HI bit */
printk(KERN_INFO "%s: Rx Hi\n", dev->name);
state &= ~Hi;
goto try;
}
} else { /* ! SccEvt */
#ifdef DEBUG_PARANOIA
} else { /* SccEvt */
if (debug > 1) {
//FIXME: verifier la presence de tous les evenements
static struct {
u32 mask;
const char *irq_name;
} evts[] = {
{ 0x00008000, "TIN"},
{ 0x00004000, "CSC"},
{ 0x00000020, "RSC"},
{ 0x00000010, "PCE"},
{ 0x00000008, "PLLA"},
{ 0x00000004, "CDSC"},
{ 0, NULL}
}, *evt;
#endif /* DEBUG_PARANOIA */
state &= 0x00ffffff;
#ifdef DEBUG_PARANOIA
for (evt = evts; evt->irq_name; evt++) {
if (state & evt->mask) {
printk(KERN_DEBUG "%s: %s\n", dev->name,
evt->irq_name);
printk(KERN_DEBUG "%s: %s\n",
dev->name, evt->irq_name);
if (!(state &= ~evt->mask))
goto try;
}
}
#endif /* DEBUG_PARANOIA */
} else {
if (!(state &= ~0x0000c03c))
goto try;
}
if (state & Cts) {
printk(KERN_INFO "%s: CTS transition\n", dev->name);
if (!(state &= ~Cts)) /* DEBUG */
goto try;
}
/*
* Receive Data Overflow (FIXME: fscked)
*/
if (state & Rdo) {
u32 ioaddr, scc_offset, scc_addr;
struct RxFD *rx_fd;
u32 scc_addr;
int cur;
//if (debug)
// dscc4_rx_dump(dpriv);
ioaddr = dev->base_addr;
scc_addr = ioaddr + 0x0c*dpriv->dev_id;
scc_offset = ioaddr + SCC_REG_START(dpriv->dev_id);
scc_addr = dev->base_addr + 0x0c*dpriv->dev_id;
writel(readl(scc_offset + CCR2) & ~RxActivate,
scc_offset + CCR2);
scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
/*
* This has no effect. Why ?
* ORed with TxSccRes, one sees the CFG ack (for
* the TX part only).
*/
writel(RxSccRes, scc_offset + CMDR);
scc_writel(RxSccRes, dpriv, dev, CMDR);
dpriv->flags |= RdoSet;
/*
......@@ -1576,10 +1632,10 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
rx_fd->state2 = 0x00000000;
rx_fd->end = 0xbabeface;
} else
dscc4_rx_skb(dpriv, cur, rx_fd, dev);
dscc4_rx_skb(dpriv, dev);
} while (1);
if (debug) {
if (debug > 0) {
if (dpriv->flags & RdoSet)
printk(KERN_DEBUG
"%s: no RDO in Rx data\n", DRV_NAME);
......@@ -1588,34 +1644,30 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
/*
* FIXME: must the reset be this violent ?
*/
#warning "FIXME: CH0BRDA"
writel(dpriv->rx_fd_dma +
(dpriv->rx_current%RX_RING_SIZE)*
sizeof(struct RxFD), scc_addr + CH0BRDA);
writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
if(dscc4_do_action(dev, "RDR")) {
if (dscc4_do_action(dev, "RDR") < 0) {
printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
dev->name, "RDR");
goto rdo_end;
}
writel(MTFi|Idr, scc_addr + CH0CFG);
if(dscc4_do_action(dev, "IDR")) {
if (dscc4_do_action(dev, "IDR") < 0) {
printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
dev->name, "IDR");
goto rdo_end;
}
rdo_end:
#endif
writel(readl(scc_offset + CCR2) | RxActivate,
scc_offset + CCR2);
scc_patchl(0, RxActivate, dpriv, dev, CCR2);
goto try;
}
/* These will be used later */
if (state & Rfs) {
if (!(state &= ~Rfs))
goto try;
}
if (state & Rfo) {
if (!(state &= ~Rfo))
if (state & Cd) {
printk(KERN_INFO "%s: CD transition\n", dev->name);
if (!(state &= ~Cd)) /* DEBUG */
goto try;
}
if (state & Flex) {
......@@ -1626,85 +1678,91 @@ static inline void dscc4_rx_irq(struct dscc4_pci_priv *priv,
}
}
/*
* I had expected the following to work for the first descriptor
* (tx_fd->state = 0xc0000000)
* - Hold=1 (don't try and branch to the next descripto);
* - No=0 (I want an empty data section, i.e. size=0);
* - Fe=1 (required by No=0 or we got an Err irq and must reset).
* It failed and locked solid. Thus the introduction of a dummy skb.
* Problem is acknowledged in errata sheet DS5. Joy :o/
*/
struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
{
struct sk_buff *skb;
skb = dev_alloc_skb(DUMMY_SKB_SIZE);
if (skb) {
int last = dpriv->tx_dirty%TX_RING_SIZE;
struct TxFD *tx_fd = dpriv->tx_fd + last;
skb->len = DUMMY_SKB_SIZE;
memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE);
tx_fd->state = FrameEnd | TO_STATE(DUMMY_SKB_SIZE);
tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
DUMMY_SKB_SIZE, PCI_DMA_TODEVICE);
dpriv->tx_skbuff[last] = skb;
}
return skb;
}
static int dscc4_init_ring(struct net_device *dev)
{
struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
struct pci_dev *pdev = dpriv->pci_priv->pdev;
struct TxFD *tx_fd;
struct RxFD *rx_fd;
void *ring;
int i;
tx_fd = (struct TxFD *) pci_alloc_consistent(dpriv->pci_priv->pdev,
TX_RING_SIZE*sizeof(struct TxFD), &dpriv->tx_fd_dma);
if (!tx_fd)
ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
if (!ring)
goto err_out;
rx_fd = (struct RxFD *) pci_alloc_consistent(dpriv->pci_priv->pdev,
RX_RING_SIZE*sizeof(struct RxFD), &dpriv->rx_fd_dma);
if (!rx_fd)
goto err_free_dma_tx;
dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
dpriv->tx_fd = tx_fd;
dpriv->rx_fd = rx_fd;
dpriv->rx_current = 0;
dpriv->tx_current = 0;
dpriv->tx_dirty = 0;
ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
if (!ring)
goto err_free_dma_rx;
dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
/* the dma core of the dscc4 will be locked on the first desc */
for (i = 0; i < TX_RING_SIZE; ) {
reset_TxFD(tx_fd);
memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
dpriv->tx_dirty = 0xffffffff;
i = dpriv->tx_current = 0;
do {
tx_fd->state = FrameEnd | TO_STATE(2*DUMMY_SKB_SIZE);
tx_fd->complete = 0x00000000;
/* FIXME: NULL should be ok - to be tried */
tx_fd->data = dpriv->tx_fd_dma;
dpriv->tx_skbuff[i] = NULL;
i++;
tx_fd->next = (u32)(dpriv->tx_fd_dma + i*sizeof(struct TxFD));
tx_fd++;
}
(--tx_fd)->next = (u32)dpriv->tx_fd_dma;
{
/*
* XXX: I would expect the following to work for the first descriptor
* (tx_fd->state = 0xc0000000)
* - Hold=1 (don't try and branch to the next descripto);
* - No=0 (I want an empty data section, i.e. size=0);
* - Fe=1 (required by No=0 or we got an Err irq and must reset).
* Alas, it fails (and locks solid). Thus the introduction of a dummy
* skb to avoid No=0 (choose one: Ugly [ ] Tasteless [ ] VMS [ ]).
* 2002/01: errata sheet acknowledges the problem [X].
*/
struct sk_buff *skb;
(tx_fd++)->next = (u32)(dpriv->tx_fd_dma +
(++i%TX_RING_SIZE)*sizeof(*tx_fd));
} while (i < TX_RING_SIZE);
skb = dev_alloc_skb(32);
if (!skb)
if (dscc4_init_dummy_skb(dpriv) < 0)
goto err_free_dma_tx;
skb->len = 32;
memset(skb->data, 0xaa, 16);
tx_fd -= (TX_RING_SIZE - 1);
tx_fd->state = 0xc0000000;
tx_fd->state |= ((u32)(skb->len & TxSizeMax)) << 16;
tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data,
skb->len, PCI_DMA_TODEVICE);
dpriv->tx_skbuff[0] = skb;
}
for (i = 0; i < RX_RING_SIZE; ) {
memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
i = dpriv->rx_dirty = dpriv->rx_current = 0;
do {
/* size set by the host. Multiple of 4 bytes please */
rx_fd->state1 = HiDesc; /* Hi, no Hold */
rx_fd->state1 = HiDesc;
rx_fd->state2 = 0x00000000;
rx_fd->end = 0xbabeface;
rx_fd->state1 |= (RX_MAX(HDLC_MAX_MRU) << 16);
try_get_rx_skb(dpriv, i, dev);
i++;
rx_fd->next = (u32)(dpriv->rx_fd_dma + i*sizeof(struct RxFD));
rx_fd++;
}
(--rx_fd)->next = (u32)dpriv->rx_fd_dma;
rx_fd->state1 |= 0x40000000; /* Hold */
// FIXME: return value verifiee mais traitement suspect
if (try_get_rx_skb(dpriv, dev) >= 0)
dpriv->rx_dirty++;
(rx_fd++)->next = (u32)(dpriv->rx_fd_dma +
(++i%RX_RING_SIZE)*sizeof(*rx_fd));
} while (i < RX_RING_SIZE);
return 0;
err_free_dma_tx:
pci_free_consistent(dpriv->pci_priv->pdev, TX_RING_SIZE*sizeof(*tx_fd),
tx_fd, dpriv->tx_fd_dma);
pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
err_free_dma_rx:
pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
err_out:
return -1;
return -ENOMEM;
}
static void __exit dscc4_remove_one(struct pci_dev *pdev)
......@@ -1770,6 +1828,17 @@ static int dscc4_hdlc_attach(hdlc_device *hdlc, unsigned short encoding,
return 0;
}
static int __init dscc4_setup(char *str)
{
int *args[] = { &debug, &quartz, NULL }, **p = args;
while (*p && (get_option(&str, *p) == 2))
p++;
return 1;
}
__setup("dscc4.setup=", dscc4_setup);
static struct pci_device_id dscc4_pci_tbl[] __devinitdata = {
{ PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
PCI_ANY_ID, PCI_ANY_ID, },
......
drivers/scsi/aic7xxx/Makefile
View file @ 64d3cfb4
......@@ -3,27 +3,23 @@
#
O_TARGET := aic7xxx_drv.o
MOD_TARGET = aic7xxx.o
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx_mod.o
#EXTRA_CFLAGS += -g
# Core files
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx.o aic7xxx_93cx6.o aic7770.o
# Platform Specific Files
AIC7XXX_OBJS = aic7xxx_linux.o
AIC7XXX_OBJS += aic7xxx_proc.o aic7770_linux.o
#PCI Specific Platform Files
ifeq ($(CONFIG_PCI),y)
AIC7XXX_OBJS += aic7xxx_linux_pci.o
endif
# Core Files
AIC7XXX_OBJS += aic7xxx.o aic7xxx_93cx6.o aic7770.o
#PCI Specific Core Files
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx_linux.o aic7xxx_proc.o aic7770_linux.o
# PCI Specific Files
ifeq ($(CONFIG_PCI),y)
AIC7XXX_OBJS += aic7xxx_pci.o
# Core PCI files
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx_pci.o
# Platform Specific PCI Files
obj-$(CONFIG_SCSI_AIC7XXX) += aic7xxx_linux_pci.o
endif
# Override our module desitnation
MOD_TARGET = aic7xxx.o
#EXTRA_CFLAGS += -g
include $(TOPDIR)/Rules.make
......
fs/jfs/jfs_metapage.c
View file @ 64d3cfb4
......@@ -91,32 +91,6 @@ static inline void lock_metapage(struct metapage *mp)
__lock_metapage(mp);
}
/* We're currently re-evaluating the method we use to write metadata
* pages. Currently, we have to make sure there no dirty buffer_heads
* hanging around after we free the metadata page, since the same
* physical disk blocks may be used in a different address space and we
* can't write old data over the good data.
*
* The best way to do this now is with block_invalidate_page. However,
* this is only available in the newer kernels and is not exported
* to modules. block_flushpage is the next best, but it too is not exported
* to modules.
*
* In a module, about the best we have is generic_buffer_fdatasync. This
* synchronously writes any dirty buffers. This is not optimal, but it will
* keep old dirty buffers from overwriting newer data.
*/
static inline void invalidate_page(metapage_t *mp)
{
#ifdef MODULE
generic_buffer_fdatasync(mp->mapping->host, mp->index, mp->index + 1);
#else
lock_page(mp->page);
block_flushpage(mp->page, 0);
UnlockPage(mp->page);
#endif
}
int __init metapage_init(void)
{
int i;
......@@ -559,8 +533,11 @@ void release_metapage(metapage_t * mp)
clear_bit(META_sync, &mp->flag);
}
if (test_bit(META_discard, &mp->flag))
invalidate_page(mp);
if (test_bit(META_discard, &mp->flag)) {
lock_page(mp->page);
block_flushpage(mp->page, 0);
UnlockPage(mp->page);
}
page_cache_release(mp->page);
INCREMENT(mpStat.pagefree);
......@@ -593,9 +570,7 @@ void invalidate_metapages(struct inode *ip, unsigned long addr,
int l2BlocksPerPage = PAGE_CACHE_SHIFT - ip->i_sb->s_blocksize_bits;
struct address_space *mapping = ip->i_mapping;
metapage_t *mp;
#ifndef MODULE
struct page *page;
#endif
/*
* First, mark metapages to discard. They will eventually be
......@@ -612,27 +587,14 @@ void invalidate_metapages(struct inode *ip, unsigned long addr,
/*
* If in the metapage cache, we've got the page locked
*/
#ifdef MODULE
UnlockPage(mp->page);
generic_buffer_fdatasync(mp->mapping->host, mp->index,
mp->index+1);
lock_page(mp->page);
#else
block_flushpage(mp->page, 0);
#endif
} else {
spin_unlock(&meta_lock);
#ifdef MODULE
generic_buffer_fdatasync(ip, lblock << l2BlocksPerPage,
(lblock + 1) << l2BlocksPerPage);
#else
page = find_lock_page(mapping,
lblock >> l2BlocksPerPage);
page = find_lock_page(mapping, lblock>>l2BlocksPerPage);
if (page) {
block_flushpage(page, 0);
UnlockPage(page);
}
#endif
}
}
}
......
include/linux/hdreg.h
View file @ 64d3cfb4
......@@ -296,7 +296,6 @@ struct hd_big_geometry {
#define HDIO_GET_MULTCOUNT 0x0304 /* get current IDE blockmode setting */
#define HDIO_GET_QDMA 0x0305 /* get use-qdma flag */
#define HDIO_OBSOLETE_IDENTITY 0x0307 /* OBSOLETE, DO NOT USE: returns 142 bytes */
#define HDIO_GET_KEEPSETTINGS 0x0308 /* get keep-settings-on-reset flag */
#define HDIO_GET_32BIT 0x0309 /* get current io_32bit setting */
#define HDIO_GET_NOWERR 0x030a /* get ignore-write-error flag */
#define HDIO_GET_DMA 0x030b /* get use-dma flag */
......@@ -316,7 +315,6 @@ struct hd_big_geometry {
/* hd/ide ctl's that pass (arg) non-ptr values are numbered 0x032n/0x033n */
#define HDIO_SET_MULTCOUNT 0x0321 /* change IDE blockmode */
#define HDIO_SET_UNMASKINTR 0x0322 /* permit other irqs during I/O */
#define HDIO_SET_KEEPSETTINGS 0x0323 /* keep ioctl settings on reset */
#define HDIO_SET_32BIT 0x0324 /* change io_32bit flags */
#define HDIO_SET_NOWERR 0x0325 /* change ignore-write-error flag */
#define HDIO_SET_DMA 0x0326 /* change use-dma flag */
......
include/linux/ide.h
View file @ 64d3cfb4
......@@ -342,12 +342,10 @@ struct ata_device {
unsigned long PADAM_timeout; /* max time to wait for irq */
special_t special; /* special action flags */
byte keep_settings; /* restore settings after drive reset */
byte using_dma; /* disk is using dma for read/write */
byte using_tcq; /* disk is using queued dma operations*/
byte retry_pio; /* retrying dma capable host in pio */
byte state; /* retry state */
byte unmask; /* flag: okay to unmask other irqs */
byte dsc_overlap; /* flag: DSC overlap */
unsigned waiting_for_dma: 1; /* dma currently in progress */
......@@ -358,7 +356,6 @@ struct ata_device {
unsigned noprobe : 1; /* from: hdx=noprobe */
unsigned removable : 1; /* 1 if need to do check_media_change */
unsigned forced_geom : 1; /* 1 if hdx=c,h,s was given at boot */
unsigned no_unmask : 1; /* disallow setting unmask bit */
unsigned nobios : 1; /* flag: do not probe bios for drive */
unsigned revalidate : 1; /* request revalidation */
unsigned atapi_overlap : 1; /* flag: ATAPI overlap (not supported) */
......@@ -388,13 +385,6 @@ struct ata_device {
unsigned long long capacity48; /* total number of sectors */
unsigned int drive_data; /* for use by tuneproc/selectproc as needed */
/* FIXME: Those are properties of a channel and not a drive! Move them
* later there.
*/
byte slow; /* flag: slow data port */
unsigned no_io_32bit : 1; /* disallow enabling 32bit I/O */
byte io_32bit; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
wait_queue_head_t wqueue; /* used to wait for drive in open() */
struct hd_driveid *id; /* drive model identification info */
......@@ -523,6 +513,12 @@ struct ata_channel {
unsigned autodma : 1; /* automatically try to enable DMA at boot */
unsigned udma_four : 1; /* 1=ATA-66 capable, 0=default */
unsigned highmem : 1; /* can do full 32-bit dma */
byte slow; /* flag: slow data port */
unsigned no_io_32bit : 1; /* disallow enabling 32bit I/O */
byte io_32bit; /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
unsigned no_unmask : 1; /* disallow setting unmask bit */
byte unmask; /* flag: okay to unmask other irqs */
#if (DISK_RECOVERY_TIME > 0)
unsigned long last_time; /* time when previous rq was done */
#endif
......@@ -972,10 +968,9 @@ extern void revalidate_drives(void);
/*
* ata_request flag bits
*/
#define ATA_AR_QUEUED 1
#define ATA_AR_SETUP 2
#define ATA_AR_RETURN 4
#define ATA_AR_STATIC 8
#define ATA_AR_QUEUED 1 /* was queued */
#define ATA_AR_SETUP 2 /* dma table mapped */
#define ATA_AR_POOL 4 /* originated from drive pool */
/*
* if turn-around time is longer than this, halve queue depth
......@@ -1007,8 +1002,10 @@ static inline struct ata_request *ata_ar_get(ide_drive_t *drive)
if (!list_empty(&drive->free_req)) {
ar = list_ata_entry(drive->free_req.next);
list_del(&ar->ar_queue);
ata_ar_init(drive, ar);
ar->ar_flags |= ATA_AR_POOL;
}
return ar;
......@@ -1016,7 +1013,7 @@ static inline struct ata_request *ata_ar_get(ide_drive_t *drive)
static inline void ata_ar_put(ide_drive_t *drive, struct ata_request *ar)
{
if (!(ar->ar_flags & ATA_AR_STATIC))
if (ar->ar_flags & ATA_AR_POOL)
list_add(&ar->ar_queue, &drive->free_req);
if (ar->ar_flags & ATA_AR_QUEUED) {
......
kernel/ksyms.c
View file @ 64d3cfb4
......@@ -211,6 +211,7 @@ EXPORT_SYMBOL(unlock_buffer);
EXPORT_SYMBOL(__wait_on_buffer);
EXPORT_SYMBOL(___wait_on_page);
EXPORT_SYMBOL(generic_direct_IO);
EXPORT_SYMBOL(discard_bh_page);
EXPORT_SYMBOL(block_write_full_page);
EXPORT_SYMBOL(block_read_full_page);
EXPORT_SYMBOL(block_prepare_write);
......
kernel/sched.c
View file @ 64d3cfb4
......@@ -1672,10 +1672,9 @@ void set_cpus_allowed(task_t *p, unsigned long new_mask)
preempt_enable();
}
static volatile unsigned long migration_mask;
static int migration_thread(void * unused)
static int migration_thread(void * bind_cpu)
{
int cpu = cpu_logical_map((int) (long) bind_cpu);
struct sched_param param = { sched_priority: 99 };
runqueue_t *rq;
int ret;
......@@ -1683,36 +1682,20 @@ static int migration_thread(void * unused)
daemonize();
sigfillset(&current->blocked);
set_fs(KERNEL_DS);
ret = setscheduler(0, SCHED_FIFO, &param);
/*
* We have to migrate manually - there is no migration thread
* to do this for us yet :-)
*
* We use the following property of the Linux scheduler. At
* this point no other task is running, so by keeping all
* migration threads running, the load-balancer will distribute
* them between all CPUs equally. At that point every migration
* task binds itself to the current CPU.
* The first migration thread is started on CPU #0. This one can migrate
* the other migration threads to their destination CPUs.
*/
/* wait for all migration threads to start up. */
while (!migration_mask)
if (cpu != 0) {
while (!cpu_rq(cpu_logical_map(0))->migration_thread)
yield();
for (;;) {
preempt_disable();
if (test_and_clear_bit(smp_processor_id(), &migration_mask))
current->cpus_allowed = 1 << smp_processor_id();
if (test_thread_flag(TIF_NEED_RESCHED))
schedule();
if (!migration_mask)
break;
preempt_enable();
set_cpus_allowed(current, 1UL << cpu);
}
printk("migration_task %d on cpu=%d\n",cpu,smp_processor_id());
ret = setscheduler(0, SCHED_FIFO, &param);
rq = this_rq();
rq->migration_thread = current;
preempt_enable();
sprintf(current->comm, "migration_CPU%d", smp_processor_id());
......@@ -1743,9 +1726,11 @@ static int migration_thread(void * unused)
cpu_src = p->thread_info->cpu;
rq_src = cpu_rq(cpu_src);
local_irq_save(flags);
double_rq_lock(rq_src, rq_dest);
if (p->thread_info->cpu != cpu_src) {
double_rq_unlock(rq_src, rq_dest);
local_irq_restore(flags);
goto repeat;
}
if (rq_src == rq) {
......@@ -1756,6 +1741,7 @@ static int migration_thread(void * unused)
}
}
double_rq_unlock(rq_src, rq_dest);
local_irq_restore(flags);
up(&req->sem);
}
......@@ -1763,33 +1749,18 @@ static int migration_thread(void * unused)
void __init migration_init(void)
{
unsigned long tmp, orig_cache_decay_ticks;
int cpu;
tmp = 0;
current->cpus_allowed = 1UL << cpu_logical_map(0);
for (cpu = 0; cpu < smp_num_cpus; cpu++) {
if (kernel_thread(migration_thread, NULL,
if (kernel_thread(migration_thread, (void *) (long) cpu,
CLONE_FS | CLONE_FILES | CLONE_SIGNAL) < 0)
BUG();
tmp |= (1UL << cpu_logical_map(cpu));
}
current->cpus_allowed = -1L;
migration_mask = tmp;
orig_cache_decay_ticks = cache_decay_ticks;
cache_decay_ticks = 0;
for (cpu = 0; cpu < smp_num_cpus; cpu++) {
int logical = cpu_logical_map(cpu);
while (!cpu_rq(logical)->migration_thread) {
set_current_state(TASK_INTERRUPTIBLE);
for (cpu = 0; cpu < smp_num_cpus; cpu++)
while (!cpu_rq(cpu)->migration_thread)
schedule_timeout(2);
}
}
if (migration_mask)
BUG();
cache_decay_ticks = orig_cache_decay_ticks;
}
#endif
lib/radix-tree.c
View file @ 64d3cfb4
......@@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/radix-tree.h>
#include <linux/slab.h>
#include <linux/string.h>
/*
* Radix tree node definition.
......
mm/filemap.c
View file @ 64d3cfb4
......@@ -797,9 +797,9 @@ struct page *find_trylock_page(struct address_space *mapping, unsigned long offs
}
/*
* Must be called with the pagecache lock held,
* will return with it held (but it may be dropped
* during blocking operations..
* Must be called with the mapping lock held for writing.
* Will return with it held for writing, but it may be dropped
* while locking the page.
*/
static struct page *__find_lock_page(struct address_space *mapping,
unsigned long offset)
......@@ -815,11 +815,11 @@ static struct page *__find_lock_page(struct address_space *mapping,
if (page) {
page_cache_get(page);
if (TryLockPage(page)) {
read_unlock(&mapping->page_lock);
write_unlock(&mapping->page_lock);
lock_page(page);
read_lock(&mapping->page_lock);
write_lock(&mapping->page_lock);
/* Has the page been re-allocated while we slept? */
/* Has the page been truncated while we slept? */
if (page->mapping != mapping || page->index != offset) {
UnlockPage(page);
page_cache_release(page);
......@@ -830,25 +830,53 @@ static struct page *__find_lock_page(struct address_space *mapping,
return page;
}
/**
* find_lock_page - locate, pin and lock a pagecache page
*
* @mapping - the address_space to search
* @offset - the page index
*
* Locates the desired pagecache page, locks it, increments its reference
* count and returns its address.
*
* Returns zero if the page was not present. find_lock_page() may sleep.
*/
/*
* Same as the above, but lock the page too, verifying that
* it's still valid once we own it.
* The write_lock is unfortunate, but __find_lock_page() requires that on
* behalf of find_or_create_page(). We could just clone __find_lock_page() -
* one for find_lock_page(), one for find_or_create_page()...
*/
struct page * find_lock_page(struct address_space *mapping, unsigned long offset)
struct page *find_lock_page(struct address_space *mapping,
unsigned long offset)
{
struct page *page;
read_lock(&mapping->page_lock);
write_lock(&mapping->page_lock);
page = __find_lock_page(mapping, offset);
read_unlock(&mapping->page_lock);
write_unlock(&mapping->page_lock);
return page;
}
/*
* Same as above, but create the page if required..
/**
* find_or_create_page - locate or add a pagecache page
*
* @mapping - the page's address_space
* @index - the page's index into the mapping
* @gfp_mask - page allocation mode
*
* Locates a page in the pagecache. If the page is not present, a new page
* is allocated using @gfp_mask and is added to the pagecache and to the VM's
* LRU list. The returned page is locked and has its reference count
* incremented.
*
* find_or_create_page() may sleep, even if @gfp_flags specifies an atomic
* allocation!
*
* find_or_create_page() returns the desired page's address, or zero on
* memory exhaustion.
*/
struct page * find_or_create_page(struct address_space *mapping,
struct page *find_or_create_page(struct address_space *mapping,
unsigned long index, unsigned int gfp_mask)
{
struct page *page;
......
mm/page_alloc.c
View file @ 64d3cfb4
......@@ -340,6 +340,8 @@ struct page * __alloc_pages(unsigned int gfp_mask, unsigned int order, zonelist_
zone = zonelist->zones;
classzone = *zone;
if (classzone == NULL)
return NULL;
min = 1UL << order;
for (;;) {
zone_t *z = *(zone++);
......
mm/vmalloc.c
View file @ 64d3cfb4
......@@ -78,11 +78,11 @@ static inline void free_area_pmd(pgd_t * dir, unsigned long address, unsigned lo
} while (address < end);
}
void vmfree_area_pages(unsigned long address, unsigned long size)
void vmfree_area_pages(unsigned long start, unsigned long size)
{
pgd_t * dir;
unsigned long start = address;
unsigned long end = address + size;
unsigned long address = start;
unsigned long end = start + size;
dir = pgd_offset_k(address);
flush_cache_all();
......
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