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Commit 64d62556 authored by Connor Abbott's avatar Connor Abbott Committed by Rob Clark
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drm/msm: More fully implement devcoredump for a7xx 

Use the vendor-provided snapshot headers to dump the contextless
registers, shader blocks, and cluster registers. Still unimplemented are
the GMU registers and "external core" registers, which would require
more work because they use register spaces we don't have described in
devicetree and dump registers from multiple spaces in a single list.
Signed-off-by: default avatarConnor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575919/Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent d98c220f
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Showing with 1462 additions and 632 deletions
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
View file @ 64d62556
......@@ -8,6 +8,17 @@
#include "a6xx_gpu_state.h"
#include "a6xx_gmu.xml.h"
/* Ignore diagnostics about register tables that we aren't using yet. We don't
* want to modify these headers too much from their original source.
*/
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-variable"
#include "adreno_gen7_0_0_snapshot.h"
#include "adreno_gen7_2_0_snapshot.h"
#pragma GCC diagnostic pop
struct a6xx_gpu_state_obj {
const void *handle;
u32 *data;
......@@ -322,12 +333,98 @@ static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg,
ptr += cx_debugbus_read(cxdbg, block->id, i, ptr);
}
static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
int nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
(a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
if (adreno_is_a650_family(to_adreno_gpu(gpu)))
nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks);
a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
sizeof(*a6xx_state->debugbus));
if (a6xx_state->debugbus) {
int i;
for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
a6xx_get_debugbus_block(gpu,
a6xx_state,
&a6xx_debugbus_blocks[i],
&a6xx_state->debugbus[i]);
a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
/*
* GBIF has same debugbus as of other GPU blocks, fall back to
* default path if GPU uses GBIF, also GBIF uses exactly same
* ID as of VBIF.
*/
if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
a6xx_get_debugbus_block(gpu, a6xx_state,
&a6xx_gbif_debugbus_block,
&a6xx_state->debugbus[i]);
a6xx_state->nr_debugbus += 1;
}
if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++)
a6xx_get_debugbus_block(gpu,
a6xx_state,
&a650_debugbus_blocks[i],
&a6xx_state->debugbus[i]);
}
}
}
static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int debugbus_blocks_count, total_debugbus_blocks;
const u32 *debugbus_blocks;
int i;
if (adreno_is_a730(adreno_gpu)) {
debugbus_blocks = gen7_0_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
debugbus_blocks = gen7_2_0_debugbus_blocks;
debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks);
}
total_debugbus_blocks = debugbus_blocks_count +
ARRAY_SIZE(a7xx_gbif_debugbus_blocks);
a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks,
sizeof(*a6xx_state->debugbus));
if (a6xx_state->debugbus) {
for (i = 0; i < debugbus_blocks_count; i++) {
a6xx_get_debugbus_block(gpu,
a6xx_state, &a7xx_debugbus_blocks[debugbus_blocks[i]],
&a6xx_state->debugbus[i]);
}
for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) {
a6xx_get_debugbus_block(gpu,
a6xx_state, &a7xx_gbif_debugbus_blocks[i],
&a6xx_state->debugbus[i + debugbus_blocks_count]);
}
}
}
static void a6xx_get_debugbus(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct resource *res;
void __iomem *cxdbg = NULL;
int nr_debugbus_blocks;
/* Set up the GX debug bus */
......@@ -382,51 +479,14 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
}
nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) +
(a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0);
if (adreno_is_a650_family(to_adreno_gpu(gpu)))
nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks);
a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks,
sizeof(*a6xx_state->debugbus));
if (a6xx_state->debugbus) {
int i;
for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++)
a6xx_get_debugbus_block(gpu,
a6xx_state,
&a6xx_debugbus_blocks[i],
&a6xx_state->debugbus[i]);
a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks);
/*
* GBIF has same debugbus as of other GPU blocks, fall back to
* default path if GPU uses GBIF, also GBIF uses exactly same
* ID as of VBIF.
*/
if (a6xx_has_gbif(to_adreno_gpu(gpu))) {
a6xx_get_debugbus_block(gpu, a6xx_state,
&a6xx_gbif_debugbus_block,
&a6xx_state->debugbus[i]);
a6xx_state->nr_debugbus += 1;
}
if (adreno_is_a650_family(to_adreno_gpu(gpu))) {
for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++)
a6xx_get_debugbus_block(gpu,
a6xx_state,
&a650_debugbus_blocks[i],
&a6xx_state->debugbus[i]);
}
if (adreno_is_a7xx(adreno_gpu)) {
a7xx_get_debugbus_blocks(gpu, a6xx_state);
} else {
a6xx_get_debugbus_blocks(gpu, a6xx_state);
}
/* Dump the VBIF debugbus on applicable targets */
if (!a6xx_has_gbif(to_adreno_gpu(gpu))) {
if (!a6xx_has_gbif(adreno_gpu)) {
a6xx_state->vbif_debugbus =
state_kcalloc(a6xx_state, 1,
sizeof(*a6xx_state->vbif_debugbus));
......@@ -437,22 +497,34 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu,
}
if (cxdbg) {
unsigned nr_cx_debugbus_blocks;
const struct a6xx_debugbus_block *cx_debugbus_blocks;
if (adreno_is_a7xx(adreno_gpu)) {
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
cx_debugbus_blocks = a7xx_cx_debugbus_blocks;
nr_cx_debugbus_blocks = ARRAY_SIZE(a7xx_cx_debugbus_blocks);
} else {
cx_debugbus_blocks = a6xx_cx_debugbus_blocks;
nr_cx_debugbus_blocks = ARRAY_SIZE(a6xx_cx_debugbus_blocks);
}
a6xx_state->cx_debugbus =
state_kcalloc(a6xx_state,
ARRAY_SIZE(a6xx_cx_debugbus_blocks),
nr_cx_debugbus_blocks,
sizeof(*a6xx_state->cx_debugbus));
if (a6xx_state->cx_debugbus) {
int i;
for (i = 0; i < ARRAY_SIZE(a6xx_cx_debugbus_blocks); i++)
for (i = 0; i < nr_cx_debugbus_blocks; i++)
a6xx_get_cx_debugbus_block(cxdbg,
a6xx_state,
&a6xx_cx_debugbus_blocks[i],
&cx_debugbus_blocks[i],
&a6xx_state->cx_debugbus[i]);
a6xx_state->nr_cx_debugbus =
ARRAY_SIZE(a6xx_cx_debugbus_blocks);
nr_cx_debugbus_blocks;
}
iounmap(cxdbg);
......@@ -508,6 +580,48 @@ static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu,
datasize);
}
static void a7xx_get_dbgahb_cluster(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const struct gen7_sptp_cluster_registers *dbgahb,
struct a6xx_gpu_state_obj *obj,
struct a6xx_crashdumper *dumper)
{
u64 *in = dumper->ptr;
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
size_t datasize;
int i, regcount = 0;
in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL,
A7XX_SP_READ_SEL_LOCATION(dbgahb->location_id) |
A7XX_SP_READ_SEL_PIPE(dbgahb->pipe_id) |
A7XX_SP_READ_SEL_STATETYPE(dbgahb->statetype));
for (i = 0; dbgahb->regs[i] != UINT_MAX; i += 2) {
int count = RANGE(dbgahb->regs, i);
u32 offset = REG_A7XX_SP_AHB_READ_APERTURE +
dbgahb->regs[i] - dbgahb->regbase;
in += CRASHDUMP_READ(in, offset, count, out);
out += count * sizeof(u32);
regcount += count;
}
CRASHDUMP_FINI(in);
datasize = regcount * sizeof(u32);
if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
return;
if (a6xx_crashdumper_run(gpu, dumper))
return;
obj->handle = dbgahb;
obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
datasize);
}
static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
......@@ -529,6 +643,39 @@ static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu,
&a6xx_state->dbgahb_clusters[i], dumper);
}
static void a7xx_get_dbgahb_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i;
const struct gen7_sptp_cluster_registers *dbgahb_clusters;
unsigned dbgahb_clusters_size;
if (adreno_is_a730(adreno_gpu)) {
dbgahb_clusters = gen7_0_0_sptp_clusters;
dbgahb_clusters_size = ARRAY_SIZE(gen7_0_0_sptp_clusters);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
dbgahb_clusters = gen7_2_0_sptp_clusters;
dbgahb_clusters_size = ARRAY_SIZE(gen7_2_0_sptp_clusters);
}
a6xx_state->dbgahb_clusters = state_kcalloc(a6xx_state,
dbgahb_clusters_size,
sizeof(*a6xx_state->dbgahb_clusters));
if (!a6xx_state->dbgahb_clusters)
return;
a6xx_state->nr_dbgahb_clusters = dbgahb_clusters_size;
for (i = 0; i < dbgahb_clusters_size; i++)
a7xx_get_dbgahb_cluster(gpu, a6xx_state,
&dbgahb_clusters[i],
&a6xx_state->dbgahb_clusters[i], dumper);
}
/* Read a data cluster from the CP aperture with the crashdumper */
static void a6xx_get_cluster(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -590,6 +737,51 @@ static void a6xx_get_cluster(struct msm_gpu *gpu,
datasize);
}
static void a7xx_get_cluster(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const struct gen7_cluster_registers *cluster,
struct a6xx_gpu_state_obj *obj,
struct a6xx_crashdumper *dumper)
{
u64 *in = dumper->ptr;
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
size_t datasize;
int i, regcount = 0;
/* Some clusters need a selector register to be programmed too */
if (cluster->sel)
in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val);
in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD,
A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) |
A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) |
A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id));
for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) {
int count = RANGE(cluster->regs, i);
in += CRASHDUMP_READ(in, cluster->regs[i],
count, out);
out += count * sizeof(u32);
regcount += count;
}
CRASHDUMP_FINI(in);
datasize = regcount * sizeof(u32);
if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
return;
if (a6xx_crashdumper_run(gpu, dumper))
return;
obj->handle = cluster;
obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
datasize);
}
static void a6xx_get_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
......@@ -609,6 +801,37 @@ static void a6xx_get_clusters(struct msm_gpu *gpu,
&a6xx_state->clusters[i], dumper);
}
static void a7xx_get_clusters(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i;
const struct gen7_cluster_registers *clusters;
unsigned clusters_size;
if (adreno_is_a730(adreno_gpu)) {
clusters = gen7_0_0_clusters;
clusters_size = ARRAY_SIZE(gen7_0_0_clusters);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
clusters = gen7_2_0_clusters;
clusters_size = ARRAY_SIZE(gen7_2_0_clusters);
}
a6xx_state->clusters = state_kcalloc(a6xx_state,
clusters_size, sizeof(*a6xx_state->clusters));
if (!a6xx_state->clusters)
return;
a6xx_state->nr_clusters = clusters_size;
for (i = 0; i < clusters_size; i++)
a7xx_get_cluster(gpu, a6xx_state, &clusters[i],
&a6xx_state->clusters[i], dumper);
}
/* Read a shader / debug block from the HLSQ aperture with the crashdumper */
static void a6xx_get_shader_block(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -617,6 +840,7 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu,
struct a6xx_crashdumper *dumper)
{
u64 *in = dumper->ptr;
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
size_t datasize = block->size * A6XX_NUM_SHADER_BANKS * sizeof(u32);
int i;
......@@ -629,6 +853,8 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu,
in += CRASHDUMP_READ(in, REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE,
block->size, dumper->iova + A6XX_CD_DATA_OFFSET);
out += block->size * sizeof(u32);
}
CRASHDUMP_FINI(in);
......@@ -641,6 +867,56 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu,
datasize);
}
static void a7xx_get_shader_block(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const struct gen7_shader_block *block,
struct a6xx_gpu_state_obj *obj,
struct a6xx_crashdumper *dumper)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
u64 *in = dumper->ptr;
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
size_t datasize = block->size * block->num_sps * block->num_usptps * sizeof(u32);
int i, j;
if (WARN_ON(datasize > A6XX_CD_DATA_SIZE))
return;
if (adreno_is_a730(adreno_gpu)) {
gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3);
}
for (i = 0; i < block->num_sps; i++) {
for (j = 0; j < block->num_usptps; j++) {
in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL,
A7XX_SP_READ_SEL_LOCATION(block->location) |
A7XX_SP_READ_SEL_PIPE(block->pipeid) |
A7XX_SP_READ_SEL_STATETYPE(block->statetype) |
A7XX_SP_READ_SEL_USPTP(j) |
A7XX_SP_READ_SEL_SPTP(i));
in += CRASHDUMP_READ(in, REG_A7XX_SP_AHB_READ_APERTURE,
block->size, out);
out += block->size * sizeof(u32);
}
}
CRASHDUMP_FINI(in);
if (a6xx_crashdumper_run(gpu, dumper))
goto out;
obj->handle = block;
obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
datasize);
out:
if (adreno_is_a730(adreno_gpu)) {
gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0);
}
}
static void a6xx_get_shaders(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
......@@ -660,6 +936,37 @@ static void a6xx_get_shaders(struct msm_gpu *gpu,
&a6xx_state->shaders[i], dumper);
}
static void a7xx_get_shaders(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const struct gen7_shader_block *shader_blocks;
unsigned num_shader_blocks;
int i;
if (adreno_is_a730(adreno_gpu)) {
shader_blocks = gen7_0_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks);
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
shader_blocks = gen7_2_0_shader_blocks;
num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks);
}
a6xx_state->shaders = state_kcalloc(a6xx_state,
num_shader_blocks, sizeof(*a6xx_state->shaders));
if (!a6xx_state->shaders)
return;
a6xx_state->nr_shaders = num_shader_blocks;
for (i = 0; i < num_shader_blocks; i++)
a7xx_get_shader_block(gpu, a6xx_state, &shader_blocks[i],
&a6xx_state->shaders[i], dumper);
}
/* Read registers from behind the HLSQ aperture with the crashdumper */
static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -741,6 +1048,44 @@ static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu,
regcount * sizeof(u32));
}
static void a7xx_get_crashdumper_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const struct gen7_reg_list *regs,
struct a6xx_gpu_state_obj *obj,
struct a6xx_crashdumper *dumper)
{
u64 *in = dumper->ptr;
u64 out = dumper->iova + A6XX_CD_DATA_OFFSET;
int i, regcount = 0;
/* Some blocks might need to program a selector register first */
if (regs->sel)
in += CRASHDUMP_WRITE(in, regs->sel->cd_reg, regs->sel->val);
for (i = 0; regs->regs[i] != UINT_MAX; i += 2) {
u32 count = RANGE(regs->regs, i);
in += CRASHDUMP_READ(in, regs->regs[i], count, out);
out += count * sizeof(u32);
regcount += count;
}
CRASHDUMP_FINI(in);
if (WARN_ON((regcount * sizeof(u32)) > A6XX_CD_DATA_SIZE))
return;
if (a6xx_crashdumper_run(gpu, dumper))
return;
obj->handle = regs->regs;
obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET,
regcount * sizeof(u32));
}
/* Read a block of registers via AHB */
static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -772,6 +1117,41 @@ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
}
}
static void a7xx_get_ahb_gpu_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const u32 *regs,
struct a6xx_gpu_state_obj *obj)
{
int i, regcount = 0, index = 0;
for (i = 0; regs[i] != UINT_MAX; i += 2)
regcount += RANGE(regs, i);
obj->handle = (const void *) regs;
obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32));
if (!obj->data)
return;
for (i = 0; regs[i] != UINT_MAX; i += 2) {
u32 count = RANGE(regs, i);
int j;
for (j = 0; j < count; j++)
obj->data[index++] = gpu_read(gpu, regs[i] + j);
}
}
static void a7xx_get_ahb_gpu_reglist(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
const struct gen7_reg_list *regs,
struct a6xx_gpu_state_obj *obj)
{
if (regs->sel)
gpu_write(gpu, regs->sel->host_reg, regs->sel->val);
a7xx_get_ahb_gpu_registers(gpu, a6xx_state, regs->regs, obj);
}
/* Read a block of GMU registers */
static void _a6xx_get_gmu_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
......@@ -902,20 +1282,11 @@ static void a6xx_get_registers(struct msm_gpu *gpu,
a6xx_state->nr_registers = count;
if (adreno_is_a7xx(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a7xx_ahb_reglist,
&a6xx_state->registers[index++]);
else
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_ahb_reglist,
&a6xx_state->registers[index++]);
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_ahb_reglist,
&a6xx_state->registers[index++]);
if (adreno_is_a7xx(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a7xx_gbif_reglist,
&a6xx_state->registers[index++]);
else if (a6xx_has_gbif(adreno_gpu))
if (a6xx_has_gbif(adreno_gpu))
a6xx_get_ahb_gpu_registers(gpu,
a6xx_state, &a6xx_gbif_reglist,
&a6xx_state->registers[index++]);
......@@ -951,6 +1322,80 @@ static void a6xx_get_registers(struct msm_gpu *gpu,
dumper);
}
#define A7XX_PRE_CRASHDUMPER_SIZE 1
#define A7XX_POST_CRASHDUMPER_SIZE 1
static void a7xx_get_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state,
struct a6xx_crashdumper *dumper)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i, count;
int index = 0;
const u32 *pre_crashdumper_regs;
const struct gen7_reg_list *reglist;
if (adreno_is_a730(adreno_gpu)) {
reglist = gen7_0_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
} else {
BUG_ON(!adreno_is_a740_family(adreno_gpu));
reglist = gen7_2_0_reg_list;
pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers;
}
count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE;
/* The downstream reglist contains registers in other memory regions
* (cx_misc/cx_mem and cx_dbgc) and we need to plumb through their
* offsets and map them to read them on the CPU. For now only read the
* first region which is the main one.
*/
if (dumper) {
for (i = 0; reglist[i].regs; i++)
count++;
} else {
count++;
}
a6xx_state->registers = state_kcalloc(a6xx_state,
count, sizeof(*a6xx_state->registers));
if (!a6xx_state->registers)
return;
a6xx_state->nr_registers = count;
a7xx_get_ahb_gpu_registers(gpu, a6xx_state, pre_crashdumper_regs,
&a6xx_state->registers[index++]);
if (!dumper) {
a7xx_get_ahb_gpu_reglist(gpu,
a6xx_state, &reglist[0],
&a6xx_state->registers[index++]);
return;
}
for (i = 0; reglist[i].regs; i++)
a7xx_get_crashdumper_registers(gpu,
a6xx_state, &reglist[i],
&a6xx_state->registers[index++],
dumper);
}
static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
const u32 *regs;
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
regs = gen7_0_0_post_crashdumper_registers;
a7xx_get_ahb_gpu_registers(gpu,
a6xx_state, regs,
&a6xx_state->registers[a6xx_state->nr_registers - 1]);
}
static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu)
{
/* The value at [16:31] is in 4dword units. Convert it to dwords */
......@@ -1045,8 +1490,10 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu,
static void a7xx_get_indexed_registers(struct msm_gpu *gpu,
struct a6xx_gpu_state *a6xx_state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
int i, indexed_count, mempool_count;
BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)));
indexed_count = ARRAY_SIZE(a7xx_indexed_reglist);
mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed);
......@@ -1109,13 +1556,10 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
return &a6xx_state->base;
/* Get the banks of indexed registers */
if (adreno_is_a7xx(adreno_gpu)) {
if (adreno_is_a7xx(adreno_gpu))
a7xx_get_indexed_registers(gpu, a6xx_state);
/* Further codeflow is untested on A7xx. */
return &a6xx_state->base;
}
a6xx_get_indexed_registers(gpu, a6xx_state);
else
a6xx_get_indexed_registers(gpu, a6xx_state);
/*
* Try to initialize the crashdumper, if we are not dumping state
......@@ -1128,14 +1572,28 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
dumper = &_dumper;
}
a6xx_get_registers(gpu, a6xx_state, dumper);
if (adreno_is_a7xx(adreno_gpu)) {
a7xx_get_registers(gpu, a6xx_state, dumper);
if (dumper) {
a6xx_get_shaders(gpu, a6xx_state, dumper);
a6xx_get_clusters(gpu, a6xx_state, dumper);
a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
if (dumper) {
a7xx_get_shaders(gpu, a6xx_state, dumper);
a7xx_get_clusters(gpu, a6xx_state, dumper);
a7xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
msm_gem_kernel_put(dumper->bo, gpu->aspace);
}
a7xx_get_post_crashdumper_registers(gpu, a6xx_state);
} else {
a6xx_get_registers(gpu, a6xx_state, dumper);
msm_gem_kernel_put(dumper->bo, gpu->aspace);
if (dumper) {
a6xx_get_shaders(gpu, a6xx_state, dumper);
a6xx_get_clusters(gpu, a6xx_state, dumper);
a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper);
msm_gem_kernel_put(dumper->bo, gpu->aspace);
}
}
if (snapshot_debugbus)
......@@ -1203,6 +1661,35 @@ static void a6xx_show_registers(const u32 *registers, u32 *data, size_t count,
}
}
static void a7xx_show_registers_indented(const u32 *registers, u32 *data,
struct drm_printer *p, unsigned indent)
{
int i, index = 0;
for (i = 0; registers[i] != UINT_MAX; i += 2) {
u32 count = RANGE(registers, i);
u32 offset = registers[i];
int j;
for (j = 0; j < count; index++, offset++, j++) {
int k;
if (data[index] == 0xdeafbead)
continue;
for (k = 0; k < indent; k++)
drm_printf(p, " ");
drm_printf(p, "- { offset: 0x%06x, value: 0x%08x }\n",
offset << 2, data[index]);
}
}
}
static void a7xx_show_registers(const u32 *registers, u32 *data, struct drm_printer *p)
{
a7xx_show_registers_indented(registers, data, p, 1);
}
static void print_ascii85(struct drm_printer *p, size_t len, u32 *data)
{
char out[ASCII85_BUFSZ];
......@@ -1258,6 +1745,36 @@ static void a6xx_show_shader(struct a6xx_gpu_state_obj *obj,
}
}
static void a7xx_show_shader(struct a6xx_gpu_state_obj *obj,
struct drm_printer *p)
{
const struct gen7_shader_block *block = obj->handle;
int i, j;
u32 *data = obj->data;
if (!obj->handle)
return;
print_name(p, " - type: ", a7xx_statetype_names[block->statetype]);
print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]);
for (i = 0; i < block->num_sps; i++) {
drm_printf(p, " - sp: %d\n", i);
for (j = 0; j < block->num_usptps; j++) {
drm_printf(p, " - usptp: %d\n", j);
drm_printf(p, " size: %d\n", block->size);
if (!obj->data)
continue;
print_ascii85(p, block->size << 2, data);
data += block->size;
}
}
}
static void a6xx_show_cluster_data(const u32 *registers, int size, u32 *data,
struct drm_printer *p)
{
......@@ -1308,6 +1825,34 @@ static void a6xx_show_cluster(struct a6xx_gpu_state_obj *obj,
}
}
static void a7xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj,
struct drm_printer *p)
{
const struct gen7_sptp_cluster_registers *dbgahb = obj->handle;
if (dbgahb) {
print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]);
print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]);
drm_printf(p, " - context: %d\n", dbgahb->context_id);
a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4);
}
}
static void a7xx_show_cluster(struct a6xx_gpu_state_obj *obj,
struct drm_printer *p)
{
const struct gen7_cluster_registers *cluster = obj->handle;
if (cluster) {
int context = (cluster->context_id == STATE_FORCE_CTXT_1) ? 1 : 0;
print_name(p, " - pipe: ", a7xx_pipe_names[cluster->pipe_id]);
print_name(p, " - cluster-name: ", a7xx_cluster_names[cluster->cluster_id]);
drm_printf(p, " - context: %d\n", context);
a7xx_show_registers_indented(cluster->regs, obj->data, p, 4);
}
}
static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj,
struct drm_printer *p)
{
......@@ -1369,6 +1914,7 @@ static void a6xx_show_debugbus(struct a6xx_gpu_state *a6xx_state,
void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
struct drm_printer *p)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
struct a6xx_gpu_state *a6xx_state = container_of(state,
struct a6xx_gpu_state, base);
int i;
......@@ -1421,12 +1967,17 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
drm_puts(p, "registers:\n");
for (i = 0; i < a6xx_state->nr_registers; i++) {
struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i];
const struct a6xx_registers *regs = obj->handle;
if (!obj->handle)
continue;
a6xx_show_registers(regs->registers, obj->data, regs->count, p);
if (adreno_is_a7xx(adreno_gpu)) {
a7xx_show_registers(obj->handle, obj->data, p);
} else {
const struct a6xx_registers *regs = obj->handle;
a6xx_show_registers(regs->registers, obj->data, regs->count, p);
}
}
drm_puts(p, "registers-gmu:\n");
......@@ -1445,15 +1996,27 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
a6xx_show_indexed_regs(&a6xx_state->indexed_regs[i], p);
drm_puts(p, "shader-blocks:\n");
for (i = 0; i < a6xx_state->nr_shaders; i++)
a6xx_show_shader(&a6xx_state->shaders[i], p);
for (i = 0; i < a6xx_state->nr_shaders; i++) {
if (adreno_is_a7xx(adreno_gpu))
a7xx_show_shader(&a6xx_state->shaders[i], p);
else
a6xx_show_shader(&a6xx_state->shaders[i], p);
}
drm_puts(p, "clusters:\n");
for (i = 0; i < a6xx_state->nr_clusters; i++)
a6xx_show_cluster(&a6xx_state->clusters[i], p);
for (i = 0; i < a6xx_state->nr_clusters; i++) {
if (adreno_is_a7xx(adreno_gpu))
a7xx_show_cluster(&a6xx_state->clusters[i], p);
else
a6xx_show_cluster(&a6xx_state->clusters[i], p);
}
for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++)
a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) {
if (adreno_is_a7xx(adreno_gpu))
a7xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
else
a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p);
}
drm_puts(p, "debugbus:\n");
a6xx_show_debugbus(a6xx_state, p);
......
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
View file @ 64d62556
// SPDX-License-Identifier: GPL-2.0
/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
/*
* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _A6XX_CRASH_DUMP_H_
#define _A6XX_CRASH_DUMP_H_
......@@ -51,6 +54,7 @@ static const u32 a6xx_pc_vs_cluster[] = {
#define CLUSTER_SP_PS 4
#define CLUSTER_PS 5
#define CLUSTER_VPC_PS 6
#define CLUSTER_NONE 7
#define CLUSTER(_id, _reg, _sel_reg, _sel_val) \
{ .id = _id, .name = #_id,\
......@@ -337,27 +341,6 @@ static const struct a6xx_registers a6xx_vbif_reglist =
static const struct a6xx_registers a6xx_gbif_reglist =
REGS(a6xx_gbif_registers, 0, 0);
static const u32 a7xx_ahb_registers[] = {
/* RBBM_STATUS */
0x210, 0x210,
/* RBBM_STATUS2-3 */
0x212, 0x213,
};
static const u32 a7xx_gbif_registers[] = {
0x3c00, 0x3c0b,
0x3c40, 0x3c42,
0x3c45, 0x3c47,
0x3c49, 0x3c4a,
0x3cc0, 0x3cd1,
};
static const struct a6xx_registers a7xx_ahb_reglist=
REGS(a7xx_ahb_registers, 0, 0);
static const struct a6xx_registers a7xx_gbif_reglist =
REGS(a7xx_gbif_registers, 0, 0);
static const u32 a6xx_gmu_gx_registers[] = {
/* GMU GX */
0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b,
......@@ -534,4 +517,288 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = {
DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100),
};
static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = {
DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100),
};
static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = {
DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100),
DEBUGBUS(A7XX_DBGBUS_CX, 0x100),
DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100),
};
#define STATE_NON_CONTEXT 0
#define STATE_TOGGLE_CTXT 1
#define STATE_FORCE_CTXT_0 2
#define STATE_FORCE_CTXT_1 3
struct gen7_sel_reg {
unsigned int host_reg;
unsigned int cd_reg;
unsigned int val;
};
struct gen7_cluster_registers {
/* cluster_id: Cluster identifier */
int cluster_id;
/* pipe_id: Pipe Identifier */
int pipe_id;
/* context_id: one of STATE_ that identifies the context to dump */
int context_id;
/* regs: Pointer to an array of register pairs */
const u32 *regs;
/* sel: Pointer to a selector register to write before reading */
const struct gen7_sel_reg *sel;
};
struct gen7_sptp_cluster_registers {
/* cluster_id: Cluster identifier */
enum a7xx_cluster cluster_id;
/* statetype: SP block state type for the cluster */
enum a7xx_statetype_id statetype;
/* pipe_id: Pipe identifier */
enum a7xx_pipe pipe_id;
/* context_id: Context identifier */
int context_id;
/* location_id: Location identifier */
enum a7xx_state_location location_id;
/* regs: Pointer to the list of register pairs to read */
const u32 *regs;
/* regbase: Dword offset of the register block in the GPu register space */
unsigned int regbase;
};
struct gen7_shader_block {
/* statetype: Type identifer for the block */
u32 statetype;
/* size: Size of the block (in dwords) */
u32 size;
/* num_sps: The SP id to dump */
u32 num_sps;
/* num_usptps: The number of USPTPs to dump */;
u32 num_usptps;
/* pipe_id: Pipe identifier for the block data */
u32 pipeid;
/* location: Location identifer for the block data */
u32 location;
};
struct gen7_reg_list {
const u32 *regs;
const struct gen7_sel_reg *sel;
};
/* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the
* list of debugbus blocks is global on a7xx.
*/
#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count },
static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = {
A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100)
A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100)
};
#define A7XX_NAME(enumval) [enumval] = #enumval
static const char *a7xx_statetype_names[] = {
A7XX_NAME(A7XX_TP0_NCTX_REG),
A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG),
A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG),
A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG),
A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG),
A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG),
A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG),
A7XX_NAME(A7XX_TP0_TMO_DATA),
A7XX_NAME(A7XX_TP0_SMO_DATA),
A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA),
A7XX_NAME(A7XX_SP_NCTX_REG),
A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG),
A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG),
A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG),
A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG),
A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG),
A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG),
A7XX_NAME(A7XX_SP_INST_DATA),
A7XX_NAME(A7XX_SP_INST_DATA_1),
A7XX_NAME(A7XX_SP_LB_0_DATA),
A7XX_NAME(A7XX_SP_LB_1_DATA),
A7XX_NAME(A7XX_SP_LB_2_DATA),
A7XX_NAME(A7XX_SP_LB_3_DATA),
A7XX_NAME(A7XX_SP_LB_4_DATA),
A7XX_NAME(A7XX_SP_LB_5_DATA),
A7XX_NAME(A7XX_SP_LB_6_DATA),
A7XX_NAME(A7XX_SP_LB_7_DATA),
A7XX_NAME(A7XX_SP_CB_RAM),
A7XX_NAME(A7XX_SP_LB_13_DATA),
A7XX_NAME(A7XX_SP_LB_14_DATA),
A7XX_NAME(A7XX_SP_INST_TAG),
A7XX_NAME(A7XX_SP_INST_DATA_2),
A7XX_NAME(A7XX_SP_TMO_TAG),
A7XX_NAME(A7XX_SP_SMO_TAG),
A7XX_NAME(A7XX_SP_STATE_DATA),
A7XX_NAME(A7XX_SP_HWAVE_RAM),
A7XX_NAME(A7XX_SP_L0_INST_BUF),
A7XX_NAME(A7XX_SP_LB_8_DATA),
A7XX_NAME(A7XX_SP_LB_9_DATA),
A7XX_NAME(A7XX_SP_LB_10_DATA),
A7XX_NAME(A7XX_SP_LB_11_DATA),
A7XX_NAME(A7XX_SP_LB_12_DATA),
A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META),
A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM),
A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD),
A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM),
A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM),
A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM),
A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM),
A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG),
A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG),
A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM),
A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM),
A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1),
A7XX_NAME(A7XX_HLSQ_INST_RAM),
A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM),
A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM),
A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM),
A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG),
A7XX_NAME(A7XX_HLSQ_INST_RAM_1),
A7XX_NAME(A7XX_HLSQ_STPROC_META),
A7XX_NAME(A7XX_HLSQ_BV_BE_META),
A7XX_NAME(A7XX_HLSQ_INST_RAM_2),
A7XX_NAME(A7XX_HLSQ_DATAPATH_META),
A7XX_NAME(A7XX_HLSQ_FRONTEND_META),
A7XX_NAME(A7XX_HLSQ_INDIRECT_META),
A7XX_NAME(A7XX_HLSQ_BACKEND_META),
};
static const char *a7xx_pipe_names[] = {
A7XX_NAME(A7XX_PIPE_NONE),
A7XX_NAME(A7XX_PIPE_BR),
A7XX_NAME(A7XX_PIPE_BV),
A7XX_NAME(A7XX_PIPE_LPAC),
};
static const char *a7xx_cluster_names[] = {
A7XX_NAME(A7XX_CLUSTER_NONE),
A7XX_NAME(A7XX_CLUSTER_FE),
A7XX_NAME(A7XX_CLUSTER_SP_VS),
A7XX_NAME(A7XX_CLUSTER_PC_VS),
A7XX_NAME(A7XX_CLUSTER_GRAS),
A7XX_NAME(A7XX_CLUSTER_SP_PS),
A7XX_NAME(A7XX_CLUSTER_VPC_PS),
A7XX_NAME(A7XX_CLUSTER_PS),
};
#endif
drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h
View file @ 64d62556
......@@ -6,161 +6,161 @@
#ifndef __ADRENO_GEN7_0_0_SNAPSHOT_H
#define __ADRENO_GEN7_0_0_SNAPSHOT_H
#include "adreno_gen7_snapshot.h"
#include "a6xx_gpu_state.h"
static const u32 gen7_0_0_debugbus_blocks[] = {
DEBUGBUS_CP_0_0,
DEBUGBUS_CP_0_1,
DEBUGBUS_RBBM,
DEBUGBUS_HLSQ,
DEBUGBUS_UCHE_0,
DEBUGBUS_TESS_BR,
DEBUGBUS_TESS_BV,
DEBUGBUS_PC_BR,
DEBUGBUS_PC_BV,
DEBUGBUS_VFDP_BR,
DEBUGBUS_VFDP_BV,
DEBUGBUS_VPC_BR,
DEBUGBUS_VPC_BV,
DEBUGBUS_TSE_BR,
DEBUGBUS_TSE_BV,
DEBUGBUS_RAS_BR,
DEBUGBUS_RAS_BV,
DEBUGBUS_VSC,
DEBUGBUS_COM_0,
DEBUGBUS_LRZ_BR,
DEBUGBUS_LRZ_BV,
DEBUGBUS_UFC_0,
DEBUGBUS_UFC_1,
DEBUGBUS_GMU_GX,
DEBUGBUS_DBGC,
DEBUGBUS_GPC_BR,
DEBUGBUS_GPC_BV,
DEBUGBUS_LARC,
DEBUGBUS_HLSQ_SPTP,
DEBUGBUS_RB_0,
DEBUGBUS_RB_1,
DEBUGBUS_RB_2,
DEBUGBUS_RB_3,
DEBUGBUS_UCHE_WRAPPER,
DEBUGBUS_CCU_0,
DEBUGBUS_CCU_1,
DEBUGBUS_CCU_2,
DEBUGBUS_CCU_3,
DEBUGBUS_VFD_BR_0,
DEBUGBUS_VFD_BR_1,
DEBUGBUS_VFD_BR_2,
DEBUGBUS_VFD_BR_3,
DEBUGBUS_VFD_BR_4,
DEBUGBUS_VFD_BR_5,
DEBUGBUS_VFD_BR_6,
DEBUGBUS_VFD_BR_7,
DEBUGBUS_VFD_BV_0,
DEBUGBUS_VFD_BV_1,
DEBUGBUS_VFD_BV_2,
DEBUGBUS_VFD_BV_3,
DEBUGBUS_USP_0,
DEBUGBUS_USP_1,
DEBUGBUS_USP_2,
DEBUGBUS_USP_3,
DEBUGBUS_TP_0,
DEBUGBUS_TP_1,
DEBUGBUS_TP_2,
DEBUGBUS_TP_3,
DEBUGBUS_TP_4,
DEBUGBUS_TP_5,
DEBUGBUS_TP_6,
DEBUGBUS_TP_7,
DEBUGBUS_USPTP_0,
DEBUGBUS_USPTP_1,
DEBUGBUS_USPTP_2,
DEBUGBUS_USPTP_3,
DEBUGBUS_USPTP_4,
DEBUGBUS_USPTP_5,
DEBUGBUS_USPTP_6,
DEBUGBUS_USPTP_7,
A7XX_DBGBUS_CP_0_0,
A7XX_DBGBUS_CP_0_1,
A7XX_DBGBUS_RBBM,
A7XX_DBGBUS_HLSQ,
A7XX_DBGBUS_UCHE_0,
A7XX_DBGBUS_TESS_BR,
A7XX_DBGBUS_TESS_BV,
A7XX_DBGBUS_PC_BR,
A7XX_DBGBUS_PC_BV,
A7XX_DBGBUS_VFDP_BR,
A7XX_DBGBUS_VFDP_BV,
A7XX_DBGBUS_VPC_BR,
A7XX_DBGBUS_VPC_BV,
A7XX_DBGBUS_TSE_BR,
A7XX_DBGBUS_TSE_BV,
A7XX_DBGBUS_RAS_BR,
A7XX_DBGBUS_RAS_BV,
A7XX_DBGBUS_VSC,
A7XX_DBGBUS_COM_0,
A7XX_DBGBUS_LRZ_BR,
A7XX_DBGBUS_LRZ_BV,
A7XX_DBGBUS_UFC_0,
A7XX_DBGBUS_UFC_1,
A7XX_DBGBUS_GMU_GX,
A7XX_DBGBUS_DBGC,
A7XX_DBGBUS_GPC_BR,
A7XX_DBGBUS_GPC_BV,
A7XX_DBGBUS_LARC,
A7XX_DBGBUS_HLSQ_SPTP,
A7XX_DBGBUS_RB_0,
A7XX_DBGBUS_RB_1,
A7XX_DBGBUS_RB_2,
A7XX_DBGBUS_RB_3,
A7XX_DBGBUS_UCHE_WRAPPER,
A7XX_DBGBUS_CCU_0,
A7XX_DBGBUS_CCU_1,
A7XX_DBGBUS_CCU_2,
A7XX_DBGBUS_CCU_3,
A7XX_DBGBUS_VFD_BR_0,
A7XX_DBGBUS_VFD_BR_1,
A7XX_DBGBUS_VFD_BR_2,
A7XX_DBGBUS_VFD_BR_3,
A7XX_DBGBUS_VFD_BR_4,
A7XX_DBGBUS_VFD_BR_5,
A7XX_DBGBUS_VFD_BR_6,
A7XX_DBGBUS_VFD_BR_7,
A7XX_DBGBUS_VFD_BV_0,
A7XX_DBGBUS_VFD_BV_1,
A7XX_DBGBUS_VFD_BV_2,
A7XX_DBGBUS_VFD_BV_3,
A7XX_DBGBUS_USP_0,
A7XX_DBGBUS_USP_1,
A7XX_DBGBUS_USP_2,
A7XX_DBGBUS_USP_3,
A7XX_DBGBUS_TP_0,
A7XX_DBGBUS_TP_1,
A7XX_DBGBUS_TP_2,
A7XX_DBGBUS_TP_3,
A7XX_DBGBUS_TP_4,
A7XX_DBGBUS_TP_5,
A7XX_DBGBUS_TP_6,
A7XX_DBGBUS_TP_7,
A7XX_DBGBUS_USPTP_0,
A7XX_DBGBUS_USPTP_1,
A7XX_DBGBUS_USPTP_2,
A7XX_DBGBUS_USPTP_3,
A7XX_DBGBUS_USPTP_4,
A7XX_DBGBUS_USPTP_5,
A7XX_DBGBUS_USPTP_6,
A7XX_DBGBUS_USPTP_7,
};
static struct gen7_shader_block gen7_0_0_shader_blocks[] = {
{TP0_TMO_DATA, 0x200, 4, 2, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 4, 2, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 4, 2, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA_2, 0x200, 4, 2, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 4, 2, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 4, 2, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 4, 2, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 4, 2, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 4, 2, PIPE_BR, USPTP},
{SP_LB_8_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 4, 2, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, HLSQ_STATE},
{A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_5_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_6_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_7_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_CB_RAM, 0x390, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_TAG, 0x90, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA_2, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_TMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_SMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_STATE_DATA, 0x40, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_HWAVE_RAM, 0x100, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_L0_INST_BUF, 0x50, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_8_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_9_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_10_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_11_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_12_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
};
static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] = {
......@@ -303,7 +303,7 @@ static const u32 gen7_0_0_noncontext_rb_rbp_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rbp_pipe_br_registers), 8));
/* Block: GRAS Cluster: CLUSTER_GRAS Pipeline: PIPE_BR */
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = {
0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
......@@ -313,7 +313,7 @@ static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_br_registers), 8));
/* Block: GRAS Cluster: CLUSTER_GRAS Pipeline: PIPE_BV */
/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = {
0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d,
0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa,
......@@ -323,7 +323,7 @@ static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_bv_registers), 8));
/* Block: PC Cluster: CLUSTER_FE Pipeline: PIPE_BR */
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = {
0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
0x09b00, 0x09b08,
......@@ -331,7 +331,7 @@ static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_br_registers), 8));
/* Block: PC Cluster: CLUSTER_FE Pipeline: PIPE_BV */
/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = {
0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886,
0x09b00, 0x09b08,
......@@ -339,7 +339,7 @@ static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_bv_registers), 8));
/* Block: RB_RAC Cluster: CLUSTER_PS Pipeline: PIPE_BR */
/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = {
0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811,
0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829,
......@@ -355,7 +355,7 @@ static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rac_cluster_ps_pipe_br_registers), 8));
/* Block: RB_RBP Cluster: CLUSTER_PS Pipeline: PIPE_BR */
/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = {
0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812,
0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a,
......@@ -370,7 +370,7 @@ static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_STATE */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = {
0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7,
0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba,
......@@ -381,7 +381,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_STATE */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = {
0x0a9b0, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc,
0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc,
......@@ -390,21 +390,21 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BR Location: HLSQ_DP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] = {
0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: HLSQ_DP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = {
0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BR Location: SP_TOP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = {
0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8,
0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5,
......@@ -414,7 +414,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: SP_TOP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = {
0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9e2, 0x0a9e3,
0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00,
......@@ -422,7 +422,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BR Location: uSPTP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: uSPTP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = {
0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae,
0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3,
......@@ -432,7 +432,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_LPAC Location: uSPTP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = {
0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3,
0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01,
......@@ -440,7 +440,7 @@ static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BR Location: HLSQ_STATE */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = {
0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
......@@ -453,7 +453,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BV Location: HLSQ_STATE */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = {
0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824,
0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a,
......@@ -466,7 +466,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BR Location: SP_TOP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: SP_TOP */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = {
0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
......@@ -477,7 +477,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BV Location: SP_TOP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = {
0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831,
0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d,
......@@ -488,7 +488,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BR Location: uSPTP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: uSPTP */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = {
0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
......@@ -498,7 +498,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_VS Pipeline: PIPE_BV Location: uSPTP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: uSPTP */
static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = {
0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833,
0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867,
......@@ -508,7 +508,7 @@ static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8));
/* Block: TPL1 Cluster: CLUSTER_SP_PS Pipeline: PIPE_BR */
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = {
0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307,
0x0b309, 0x0b309, 0x0b310, 0x0b310,
......@@ -516,35 +516,35 @@ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BV Location: HLSQ_STATE */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = {
0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BV Location: SP_TOP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: SP_TOP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] = {
0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers), 8));
/* Block: SP Cluster: CLUSTER_SP_PS Pipeline: PIPE_BV Location: uSPTP */
/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: uSPTP */
static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] = {
0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers), 8));
/* Block: TPL1 Cluster: CLUSTER_SP_PS Pipeline: PIPE_BV */
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] = {
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers), 8));
/* Block: TPL1 Cluster: CLUSTER_SP_PS Pipeline: PIPE_LPAC */
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */
static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = {
0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309,
0x0b310, 0x0b310,
......@@ -552,84 +552,84 @@ static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers), 8));
/* Block: TPL1 Cluster: CLUSTER_SP_VS Pipeline: PIPE_BR */
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] = {
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers), 8));
/* Block: TPL1 Cluster: CLUSTER_SP_VS Pipeline: PIPE_BV */
/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] = {
0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers), 8));
/* Block: VFD Cluster: CLUSTER_FE Pipeline: PIPE_BR */
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] = {
0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_br_registers), 8));
/* Block: VFD Cluster: CLUSTER_FE Pipeline: PIPE_BV */
/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] = {
0x0a000, 0x0a009, 0x0a00e, 0x0a0ef,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_bv_registers), 8));
/* Block: VPC Cluster: CLUSTER_FE Pipeline: PIPE_BR */
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] = {
0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_br_registers), 8));
/* Block: VPC Cluster: CLUSTER_FE Pipeline: PIPE_BV */
/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] = {
0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_bv_registers), 8));
/* Block: VPC Cluster: CLUSTER_PC_VS Pipeline: PIPE_BR */
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] = {
0x09101, 0x0910c, 0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers), 8));
/* Block: VPC Cluster: CLUSTER_PC_VS Pipeline: PIPE_BV */
/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] = {
0x09101, 0x0910c, 0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers), 8));
/* Block: VPC Cluster: CLUSTER_VPC_PS Pipeline: PIPE_BR */
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] = {
0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers), 8));
/* Block: VPC Cluster: CLUSTER_VPC_PS Pipeline: PIPE_BV */
/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */
static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] = {
0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: HLSQ_STATE */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] = {
0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae73,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: SP_TOP */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */
static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = {
0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f,
......@@ -638,7 +638,7 @@ static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_sp_top_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_BR Location: uSPTP */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */
static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = {
0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c,
0x0ae0f, 0x0ae0f, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3b,
......@@ -647,28 +647,28 @@ static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_usptp_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: HLSQ_STATE */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
0x0af88, 0x0af8a,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: SP_TOP */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] = {
0x0af80, 0x0af84,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers), 8));
/* Block: SP Cluster: noncontext Pipeline: PIPE_LPAC Location: uSPTP */
/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP */
static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = {
0x0af80, 0x0af84, 0x0af90, 0x0af92,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8));
/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_BR */
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */
static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c,
0x0b60f, 0x0b621, 0x0b630, 0x0b633,
......@@ -676,7 +676,7 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8));
/* Block: TPl1 Cluster: noncontext Pipeline: PIPE_LPAC */
/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */
static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
0x0b780, 0x0b780,
UINT_MAX, UINT_MAX,
......@@ -684,184 +684,184 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = {
static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8));
static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = {
.host_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_CD,
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
.val = 0x0,
};
static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = {
.host_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_CD,
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
.val = 0x9,
};
static struct gen7_cluster_registers gen7_0_0_clusters[] = {
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_0_0_noncontext_pipe_br_registers, },
{ CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
gen7_0_0_noncontext_pipe_bv_registers, },
{ CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
gen7_0_0_noncontext_pipe_lpac_registers, },
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_0_0_noncontext_rb_rac_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_0_0_noncontext_rb_rbp_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
{ CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_gras_cluster_gras_pipe_br_registers, },
{ CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
{ CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_gras_cluster_gras_pipe_br_registers, },
{ CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_gras_cluster_gras_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
{ CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
{ CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
{ CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
{ CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
{ CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
{ CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
{ CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
};
static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, HLSQ_STATE,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, SP_TOP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
{ CLUSTER_NONE, TP0_NCTX_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
{ CLUSTER_NONE, TP0_NCTX_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
};
......
drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h
View file @ 64d62556
......@@ -6,177 +6,177 @@
#ifndef __ADRENO_GEN7_2_0_SNAPSHOT_H
#define __ADRENO_GEN7_2_0_SNAPSHOT_H
#include "adreno_gen7_snapshot.h"
#include "a6xx_gpu_state.h"
static const u32 gen7_2_0_debugbus_blocks[] = {
DEBUGBUS_CP_0_0,
DEBUGBUS_CP_0_1,
DEBUGBUS_RBBM,
DEBUGBUS_HLSQ,
DEBUGBUS_UCHE_0,
DEBUGBUS_UCHE_1,
DEBUGBUS_TESS_BR,
DEBUGBUS_TESS_BV,
DEBUGBUS_PC_BR,
DEBUGBUS_PC_BV,
DEBUGBUS_VFDP_BR,
DEBUGBUS_VFDP_BV,
DEBUGBUS_VPC_BR,
DEBUGBUS_VPC_BV,
DEBUGBUS_TSE_BR,
DEBUGBUS_TSE_BV,
DEBUGBUS_RAS_BR,
DEBUGBUS_RAS_BV,
DEBUGBUS_VSC,
DEBUGBUS_COM_0,
DEBUGBUS_LRZ_BR,
DEBUGBUS_LRZ_BV,
DEBUGBUS_UFC_0,
DEBUGBUS_UFC_1,
DEBUGBUS_GMU_GX,
DEBUGBUS_DBGC,
DEBUGBUS_GPC_BR,
DEBUGBUS_GPC_BV,
DEBUGBUS_LARC,
DEBUGBUS_HLSQ_SPTP,
DEBUGBUS_RB_0,
DEBUGBUS_RB_1,
DEBUGBUS_RB_2,
DEBUGBUS_RB_3,
DEBUGBUS_RB_4,
DEBUGBUS_RB_5,
DEBUGBUS_UCHE_WRAPPER,
DEBUGBUS_CCU_0,
DEBUGBUS_CCU_1,
DEBUGBUS_CCU_2,
DEBUGBUS_CCU_3,
DEBUGBUS_CCU_4,
DEBUGBUS_CCU_5,
DEBUGBUS_VFD_BR_0,
DEBUGBUS_VFD_BR_1,
DEBUGBUS_VFD_BR_2,
DEBUGBUS_VFD_BR_3,
DEBUGBUS_VFD_BR_4,
DEBUGBUS_VFD_BR_5,
DEBUGBUS_VFD_BV_0,
DEBUGBUS_VFD_BV_1,
DEBUGBUS_USP_0,
DEBUGBUS_USP_1,
DEBUGBUS_USP_2,
DEBUGBUS_USP_3,
DEBUGBUS_USP_4,
DEBUGBUS_USP_5,
DEBUGBUS_TP_0,
DEBUGBUS_TP_1,
DEBUGBUS_TP_2,
DEBUGBUS_TP_3,
DEBUGBUS_TP_4,
DEBUGBUS_TP_5,
DEBUGBUS_TP_6,
DEBUGBUS_TP_7,
DEBUGBUS_TP_8,
DEBUGBUS_TP_9,
DEBUGBUS_TP_10,
DEBUGBUS_TP_11,
DEBUGBUS_USPTP_0,
DEBUGBUS_USPTP_1,
DEBUGBUS_USPTP_2,
DEBUGBUS_USPTP_3,
DEBUGBUS_USPTP_4,
DEBUGBUS_USPTP_5,
DEBUGBUS_USPTP_6,
DEBUGBUS_USPTP_7,
DEBUGBUS_USPTP_8,
DEBUGBUS_USPTP_9,
DEBUGBUS_USPTP_10,
DEBUGBUS_USPTP_11,
DEBUGBUS_CCHE_0,
DEBUGBUS_CCHE_1,
DEBUGBUS_CCHE_2,
A7XX_DBGBUS_CP_0_0,
A7XX_DBGBUS_CP_0_1,
A7XX_DBGBUS_RBBM,
A7XX_DBGBUS_HLSQ,
A7XX_DBGBUS_UCHE_0,
A7XX_DBGBUS_UCHE_1,
A7XX_DBGBUS_TESS_BR,
A7XX_DBGBUS_TESS_BV,
A7XX_DBGBUS_PC_BR,
A7XX_DBGBUS_PC_BV,
A7XX_DBGBUS_VFDP_BR,
A7XX_DBGBUS_VFDP_BV,
A7XX_DBGBUS_VPC_BR,
A7XX_DBGBUS_VPC_BV,
A7XX_DBGBUS_TSE_BR,
A7XX_DBGBUS_TSE_BV,
A7XX_DBGBUS_RAS_BR,
A7XX_DBGBUS_RAS_BV,
A7XX_DBGBUS_VSC,
A7XX_DBGBUS_COM_0,
A7XX_DBGBUS_LRZ_BR,
A7XX_DBGBUS_LRZ_BV,
A7XX_DBGBUS_UFC_0,
A7XX_DBGBUS_UFC_1,
A7XX_DBGBUS_GMU_GX,
A7XX_DBGBUS_DBGC,
A7XX_DBGBUS_GPC_BR,
A7XX_DBGBUS_GPC_BV,
A7XX_DBGBUS_LARC,
A7XX_DBGBUS_HLSQ_SPTP,
A7XX_DBGBUS_RB_0,
A7XX_DBGBUS_RB_1,
A7XX_DBGBUS_RB_2,
A7XX_DBGBUS_RB_3,
A7XX_DBGBUS_RB_4,
A7XX_DBGBUS_RB_5,
A7XX_DBGBUS_UCHE_WRAPPER,
A7XX_DBGBUS_CCU_0,
A7XX_DBGBUS_CCU_1,
A7XX_DBGBUS_CCU_2,
A7XX_DBGBUS_CCU_3,
A7XX_DBGBUS_CCU_4,
A7XX_DBGBUS_CCU_5,
A7XX_DBGBUS_VFD_BR_0,
A7XX_DBGBUS_VFD_BR_1,
A7XX_DBGBUS_VFD_BR_2,
A7XX_DBGBUS_VFD_BR_3,
A7XX_DBGBUS_VFD_BR_4,
A7XX_DBGBUS_VFD_BR_5,
A7XX_DBGBUS_VFD_BV_0,
A7XX_DBGBUS_VFD_BV_1,
A7XX_DBGBUS_USP_0,
A7XX_DBGBUS_USP_1,
A7XX_DBGBUS_USP_2,
A7XX_DBGBUS_USP_3,
A7XX_DBGBUS_USP_4,
A7XX_DBGBUS_USP_5,
A7XX_DBGBUS_TP_0,
A7XX_DBGBUS_TP_1,
A7XX_DBGBUS_TP_2,
A7XX_DBGBUS_TP_3,
A7XX_DBGBUS_TP_4,
A7XX_DBGBUS_TP_5,
A7XX_DBGBUS_TP_6,
A7XX_DBGBUS_TP_7,
A7XX_DBGBUS_TP_8,
A7XX_DBGBUS_TP_9,
A7XX_DBGBUS_TP_10,
A7XX_DBGBUS_TP_11,
A7XX_DBGBUS_USPTP_0,
A7XX_DBGBUS_USPTP_1,
A7XX_DBGBUS_USPTP_2,
A7XX_DBGBUS_USPTP_3,
A7XX_DBGBUS_USPTP_4,
A7XX_DBGBUS_USPTP_5,
A7XX_DBGBUS_USPTP_6,
A7XX_DBGBUS_USPTP_7,
A7XX_DBGBUS_USPTP_8,
A7XX_DBGBUS_USPTP_9,
A7XX_DBGBUS_USPTP_10,
A7XX_DBGBUS_USPTP_11,
A7XX_DBGBUS_CCHE_0,
A7XX_DBGBUS_CCHE_1,
A7XX_DBGBUS_CCHE_2,
};
static struct gen7_shader_block gen7_2_0_shader_blocks[] = {
{TP0_TMO_DATA, 0x200, 6, 2, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 6, 2, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 6, 2, PIPE_BR, USPTP},
{SP_LB_13_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_14_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_INST_TAG, 0xc0, 6, 2, PIPE_BR, USPTP},
{SP_INST_DATA_2, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 6, 2, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 6, 2, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 6, 2, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 6, 2, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 6, 2, PIPE_BR, USPTP},
{SP_LB_8_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x800, 6, 2, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM, 0x200, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_INST_RAM, 0x200, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_FRONTEND_META, 0x80, 1, 1, PIPE_LPAC, HLSQ_STATE},
{HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, HLSQ_STATE},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, HLSQ_STATE},
{A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_5_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_6_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_7_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_CB_RAM, 0x390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_13_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_14_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_TAG, 0xc0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_INST_DATA_2, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_TMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_SMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_STATE_DATA, 0x40, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_HWAVE_RAM, 0x100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_L0_INST_BUF, 0x50, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_8_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_9_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_10_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_11_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_SP_LB_12_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP},
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
{A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE},
{A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE},
};
static const u32 gen7_2_0_gpu_registers[] = {
......@@ -478,180 +478,180 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = {
static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8));
static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = {
.host_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_CD,
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
.val = 0x0,
};
static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = {
.host_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = GEN7_RB_SUB_BLOCK_SEL_CNTL_CD,
.host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST,
.cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD,
.val = 0x9,
};
static struct gen7_cluster_registers gen7_2_0_clusters[] = {
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_2_0_noncontext_pipe_br_registers, },
{ CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT,
gen7_2_0_noncontext_pipe_bv_registers, },
{ CLUSTER_NONE, PIPE_LPAC, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT,
gen7_0_0_noncontext_pipe_lpac_registers, },
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_2_0_noncontext_rb_rac_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
{ A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT,
gen7_2_0_noncontext_rb_rbp_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
{ CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_2_0_gras_cluster_gras_pipe_br_registers, },
{ CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
{ CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_2_0_gras_cluster_gras_pipe_br_registers, },
{ CLUSTER_GRAS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_2_0_gras_cluster_gras_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_pc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_pc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
{ CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vfd_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vfd_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_fe_pipe_br_registers, },
{ CLUSTER_FE, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_fe_pipe_bv_registers, },
{ CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
{ CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
{ CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, },
{ CLUSTER_PC_VS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, },
{ CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
{ CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_0,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0,
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
{ CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, },
{ CLUSTER_VPC_PS, PIPE_BV, STATE_FORCE_CTXT_1,
{ A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1,
gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, },
};
static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = {
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, HLSQ_STATE,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, SP_TOP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 },
{ CLUSTER_NONE, TP0_NCTX_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 },
{ CLUSTER_NONE, TP0_NCTX_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX1_3D_CPS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX2_3D_CPS_REG, PIPE_BR, 2, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX3_3D_CPS_REG, PIPE_BR, 3, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, HLSQ_DP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP,
gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, SP_TOP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 },
{ CLUSTER_SP_PS, SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX0_3D_CVS_REG, PIPE_BV, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, HLSQ_STATE,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, SP_TOP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 },
{ CLUSTER_SP_VS, SP_CTX1_3D_CVS_REG, PIPE_BV, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 },
{ CLUSTER_SP_PS, TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_PS, TP0_CTX0_3D_CPS_REG, PIPE_LPAC, 0, USPTP,
{ A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX0_3D_CVS_REG, PIPE_BV, 0, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 },
{ CLUSTER_SP_VS, TP0_CTX1_3D_CVS_REG, PIPE_BV, 1, USPTP,
{ A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP,
gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 },
};
......
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