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Commit 663a233e authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'drm-header-fixes' of https://github.com/GabrielL/linux into drm-next 

Fix all the problems with the header files and userspace builds
off them. I really care so little about this, but hey who am
I to stop progress.

* 'drm-header-fixes' of https://github.com/GabrielL/linux: (30 commits)
  drm: fix inclusion of drm.h in via_drm.h
  drm: fix inclusion of drm.h in vmwgfx_drm.h
  drm: fix inclusion of drm.h in virtgpu_drm.h
  drm: fix inclusion of drm.h in tegra_drm.h
  drm: fix inclusion of drm.h in savage_drm.h
  drm: fix inclusion of drm.h in r128_drm.h
  drm: fix inclusion of drm.h in qxl_drm.h
  drm: fix inclusion of drm.h in omap_drm.h
  drm: fix inclusion of drm.h in msm_drm.h
  drm: fix inclusion of drm.h in mga_drm.h
  drm: fix inclusion of drm.h in exynos_sarea.h
  drm: fix inclusion of drm.h in i810_drm.h
  drm: fix inclusion of drm.h in exynos_sarea.h
  drm: fix inclusion of drm.h in drm_sarea.h
  drm: drm_mode.h fix includes
  drm: drm_fourcc.h fix includes
  drm: include drm.h in armada_drm.h
  include/uapi/drm/amdgpu_drm.h: use __u32 and __u64 from <linux/types.h>
  drm: Kbuild: add admgpu_drm.h to the installed headers
  drm: use __u{32,64} instead of uint{32,64}_t in virtgpu_drm.h
  ...
parents e876b41a d7e12cd7
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include/uapi/drm/Kbuild
View file @ 663a233e
...@@ -3,6 +3,7 @@ header-y += drm.h ...@@ -3,6 +3,7 @@ header-y += drm.h
header-y += drm_fourcc.h header-y += drm_fourcc.h
header-y += drm_mode.h header-y += drm_mode.h
header-y += drm_sarea.h header-y += drm_sarea.h
header-y += amdgpu_drm.h
header-y += exynos_drm.h header-y += exynos_drm.h
header-y += i810_drm.h header-y += i810_drm.h
header-y += i915_drm.h header-y += i915_drm.h
......
include/uapi/drm/amdgpu_drm.h
View file @ 663a233e
...@@ -76,19 +76,19 @@ ...@@ -76,19 +76,19 @@
struct drm_amdgpu_gem_create_in { struct drm_amdgpu_gem_create_in {
/** the requested memory size */ /** the requested memory size */
uint64_t bo_size; __u64 bo_size;
/** physical start_addr alignment in bytes for some HW requirements */ /** physical start_addr alignment in bytes for some HW requirements */
uint64_t alignment; __u64 alignment;
/** the requested memory domains */ /** the requested memory domains */
uint64_t domains; __u64 domains;
/** allocation flags */ /** allocation flags */
uint64_t domain_flags; __u64 domain_flags;
}; };
struct drm_amdgpu_gem_create_out { struct drm_amdgpu_gem_create_out {
/** returned GEM object handle */ /** returned GEM object handle */
uint32_t handle; __u32 handle;
uint32_t _pad; __u32 _pad;
}; };
union drm_amdgpu_gem_create { union drm_amdgpu_gem_create {
...@@ -105,28 +105,28 @@ union drm_amdgpu_gem_create { ...@@ -105,28 +105,28 @@ union drm_amdgpu_gem_create {
struct drm_amdgpu_bo_list_in { struct drm_amdgpu_bo_list_in {
/** Type of operation */ /** Type of operation */
uint32_t operation; __u32 operation;
/** Handle of list or 0 if we want to create one */ /** Handle of list or 0 if we want to create one */
uint32_t list_handle; __u32 list_handle;
/** Number of BOs in list */ /** Number of BOs in list */
uint32_t bo_number; __u32 bo_number;
/** Size of each element describing BO */ /** Size of each element describing BO */
uint32_t bo_info_size; __u32 bo_info_size;
/** Pointer to array describing BOs */ /** Pointer to array describing BOs */
uint64_t bo_info_ptr; __u64 bo_info_ptr;
}; };
struct drm_amdgpu_bo_list_entry { struct drm_amdgpu_bo_list_entry {
/** Handle of BO */ /** Handle of BO */
uint32_t bo_handle; __u32 bo_handle;
/** New (if specified) BO priority to be used during migration */ /** New (if specified) BO priority to be used during migration */
uint32_t bo_priority; __u32 bo_priority;
}; };
struct drm_amdgpu_bo_list_out { struct drm_amdgpu_bo_list_out {
/** Handle of resource list */ /** Handle of resource list */
uint32_t list_handle; __u32 list_handle;
uint32_t _pad; __u32 _pad;
}; };
union drm_amdgpu_bo_list { union drm_amdgpu_bo_list {
...@@ -150,26 +150,26 @@ union drm_amdgpu_bo_list { ...@@ -150,26 +150,26 @@ union drm_amdgpu_bo_list {
struct drm_amdgpu_ctx_in { struct drm_amdgpu_ctx_in {
/** AMDGPU_CTX_OP_* */ /** AMDGPU_CTX_OP_* */
uint32_t op; __u32 op;
/** For future use, no flags defined so far */ /** For future use, no flags defined so far */
uint32_t flags; __u32 flags;
uint32_t ctx_id; __u32 ctx_id;
uint32_t _pad; __u32 _pad;
}; };
union drm_amdgpu_ctx_out { union drm_amdgpu_ctx_out {
struct { struct {
uint32_t ctx_id; __u32 ctx_id;
uint32_t _pad; __u32 _pad;
} alloc; } alloc;
struct { struct {
/** For future use, no flags defined so far */ /** For future use, no flags defined so far */
uint64_t flags; __u64 flags;
/** Number of resets caused by this context so far. */ /** Number of resets caused by this context so far. */
uint32_t hangs; __u32 hangs;
/** Reset status since the last call of the ioctl. */ /** Reset status since the last call of the ioctl. */
uint32_t reset_status; __u32 reset_status;
} state; } state;
}; };
...@@ -189,12 +189,12 @@ union drm_amdgpu_ctx { ...@@ -189,12 +189,12 @@ union drm_amdgpu_ctx {
#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
struct drm_amdgpu_gem_userptr { struct drm_amdgpu_gem_userptr {
uint64_t addr; __u64 addr;
uint64_t size; __u64 size;
/* AMDGPU_GEM_USERPTR_* */ /* AMDGPU_GEM_USERPTR_* */
uint32_t flags; __u32 flags;
/* Resulting GEM handle */ /* Resulting GEM handle */
uint32_t handle; __u32 handle;
}; };
/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
...@@ -226,28 +226,28 @@ struct drm_amdgpu_gem_userptr { ...@@ -226,28 +226,28 @@ struct drm_amdgpu_gem_userptr {
/** The same structure is shared for input/output */ /** The same structure is shared for input/output */
struct drm_amdgpu_gem_metadata { struct drm_amdgpu_gem_metadata {
/** GEM Object handle */ /** GEM Object handle */
uint32_t handle; __u32 handle;
/** Do we want get or set metadata */ /** Do we want get or set metadata */
uint32_t op; __u32 op;
struct { struct {
/** For future use, no flags defined so far */ /** For future use, no flags defined so far */
uint64_t flags; __u64 flags;
/** family specific tiling info */ /** family specific tiling info */
uint64_t tiling_info; __u64 tiling_info;
uint32_t data_size_bytes; __u32 data_size_bytes;
uint32_t data[64]; __u32 data[64];
} data; } data;
}; };
struct drm_amdgpu_gem_mmap_in { struct drm_amdgpu_gem_mmap_in {
/** the GEM object handle */ /** the GEM object handle */
uint32_t handle; __u32 handle;
uint32_t _pad; __u32 _pad;
}; };
struct drm_amdgpu_gem_mmap_out { struct drm_amdgpu_gem_mmap_out {
/** mmap offset from the vma offset manager */ /** mmap offset from the vma offset manager */
uint64_t addr_ptr; __u64 addr_ptr;
}; };
union drm_amdgpu_gem_mmap { union drm_amdgpu_gem_mmap {
...@@ -257,18 +257,18 @@ union drm_amdgpu_gem_mmap { ...@@ -257,18 +257,18 @@ union drm_amdgpu_gem_mmap {
struct drm_amdgpu_gem_wait_idle_in { struct drm_amdgpu_gem_wait_idle_in {
/** GEM object handle */ /** GEM object handle */
uint32_t handle; __u32 handle;
/** For future use, no flags defined so far */ /** For future use, no flags defined so far */
uint32_t flags; __u32 flags;
/** Absolute timeout to wait */ /** Absolute timeout to wait */
uint64_t timeout; __u64 timeout;
}; };
struct drm_amdgpu_gem_wait_idle_out { struct drm_amdgpu_gem_wait_idle_out {
/** BO status: 0 - BO is idle, 1 - BO is busy */ /** BO status: 0 - BO is idle, 1 - BO is busy */
uint32_t status; __u32 status;
/** Returned current memory domain */ /** Returned current memory domain */
uint32_t domain; __u32 domain;
}; };
union drm_amdgpu_gem_wait_idle { union drm_amdgpu_gem_wait_idle {
...@@ -278,18 +278,18 @@ union drm_amdgpu_gem_wait_idle { ...@@ -278,18 +278,18 @@ union drm_amdgpu_gem_wait_idle {
struct drm_amdgpu_wait_cs_in { struct drm_amdgpu_wait_cs_in {
/** Command submission handle */ /** Command submission handle */
uint64_t handle; __u64 handle;
/** Absolute timeout to wait */ /** Absolute timeout to wait */
uint64_t timeout; __u64 timeout;
uint32_t ip_type; __u32 ip_type;
uint32_t ip_instance; __u32 ip_instance;
uint32_t ring; __u32 ring;
uint32_t ctx_id; __u32 ctx_id;
}; };
struct drm_amdgpu_wait_cs_out { struct drm_amdgpu_wait_cs_out {
/** CS status: 0 - CS completed, 1 - CS still busy */ /** CS status: 0 - CS completed, 1 - CS still busy */
uint64_t status; __u64 status;
}; };
union drm_amdgpu_wait_cs { union drm_amdgpu_wait_cs {
...@@ -303,11 +303,11 @@ union drm_amdgpu_wait_cs { ...@@ -303,11 +303,11 @@ union drm_amdgpu_wait_cs {
/* Sets or returns a value associated with a buffer. */ /* Sets or returns a value associated with a buffer. */
struct drm_amdgpu_gem_op { struct drm_amdgpu_gem_op {
/** GEM object handle */ /** GEM object handle */
uint32_t handle; __u32 handle;
/** AMDGPU_GEM_OP_* */ /** AMDGPU_GEM_OP_* */
uint32_t op; __u32 op;
/** Input or return value */ /** Input or return value */
uint64_t value; __u64 value;
}; };
#define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_MAP 1
...@@ -326,18 +326,18 @@ struct drm_amdgpu_gem_op { ...@@ -326,18 +326,18 @@ struct drm_amdgpu_gem_op {
struct drm_amdgpu_gem_va { struct drm_amdgpu_gem_va {
/** GEM object handle */ /** GEM object handle */
uint32_t handle; __u32 handle;
uint32_t _pad; __u32 _pad;
/** AMDGPU_VA_OP_* */ /** AMDGPU_VA_OP_* */
uint32_t operation; __u32 operation;
/** AMDGPU_VM_PAGE_* */ /** AMDGPU_VM_PAGE_* */
uint32_t flags; __u32 flags;
/** va address to assign . Must be correctly aligned.*/ /** va address to assign . Must be correctly aligned.*/
uint64_t va_address; __u64 va_address;
/** Specify offset inside of BO to assign. Must be correctly aligned.*/ /** Specify offset inside of BO to assign. Must be correctly aligned.*/
uint64_t offset_in_bo; __u64 offset_in_bo;
/** Specify mapping size. Must be correctly aligned. */ /** Specify mapping size. Must be correctly aligned. */
uint64_t map_size; __u64 map_size;
}; };
#define AMDGPU_HW_IP_GFX 0 #define AMDGPU_HW_IP_GFX 0
...@@ -354,24 +354,24 @@ struct drm_amdgpu_gem_va { ...@@ -354,24 +354,24 @@ struct drm_amdgpu_gem_va {
#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
struct drm_amdgpu_cs_chunk { struct drm_amdgpu_cs_chunk {
uint32_t chunk_id; __u32 chunk_id;
uint32_t length_dw; __u32 length_dw;
uint64_t chunk_data; __u64 chunk_data;
}; };
struct drm_amdgpu_cs_in { struct drm_amdgpu_cs_in {
/** Rendering context id */ /** Rendering context id */
uint32_t ctx_id; __u32 ctx_id;
/** Handle of resource list associated with CS */ /** Handle of resource list associated with CS */
uint32_t bo_list_handle; __u32 bo_list_handle;
uint32_t num_chunks; __u32 num_chunks;
uint32_t _pad; __u32 _pad;
/** this points to uint64_t * which point to cs chunks */ /** this points to __u64 * which point to cs chunks */
uint64_t chunks; __u64 chunks;
}; };
struct drm_amdgpu_cs_out { struct drm_amdgpu_cs_out {
uint64_t handle; __u64 handle;
}; };
union drm_amdgpu_cs { union drm_amdgpu_cs {
...@@ -388,32 +388,32 @@ union drm_amdgpu_cs { ...@@ -388,32 +388,32 @@ union drm_amdgpu_cs {
#define AMDGPU_IB_FLAG_PREAMBLE (1<<1) #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
struct drm_amdgpu_cs_chunk_ib { struct drm_amdgpu_cs_chunk_ib {
uint32_t _pad; __u32 _pad;
/** AMDGPU_IB_FLAG_* */ /** AMDGPU_IB_FLAG_* */
uint32_t flags; __u32 flags;
/** Virtual address to begin IB execution */ /** Virtual address to begin IB execution */
uint64_t va_start; __u64 va_start;
/** Size of submission */ /** Size of submission */
uint32_t ib_bytes; __u32 ib_bytes;
/** HW IP to submit to */ /** HW IP to submit to */
uint32_t ip_type; __u32 ip_type;
/** HW IP index of the same type to submit to */ /** HW IP index of the same type to submit to */
uint32_t ip_instance; __u32 ip_instance;
/** Ring index to submit to */ /** Ring index to submit to */
uint32_t ring; __u32 ring;
}; };
struct drm_amdgpu_cs_chunk_dep { struct drm_amdgpu_cs_chunk_dep {
uint32_t ip_type; __u32 ip_type;
uint32_t ip_instance; __u32 ip_instance;
uint32_t ring; __u32 ring;
uint32_t ctx_id; __u32 ctx_id;
uint64_t handle; __u64 handle;
}; };
struct drm_amdgpu_cs_chunk_fence { struct drm_amdgpu_cs_chunk_fence {
uint32_t handle; __u32 handle;
uint32_t offset; __u32 offset;
}; };
struct drm_amdgpu_cs_chunk_data { struct drm_amdgpu_cs_chunk_data {
...@@ -486,83 +486,83 @@ struct drm_amdgpu_cs_chunk_data { ...@@ -486,83 +486,83 @@ struct drm_amdgpu_cs_chunk_data {
/* Input structure for the INFO ioctl */ /* Input structure for the INFO ioctl */
struct drm_amdgpu_info { struct drm_amdgpu_info {
/* Where the return value will be stored */ /* Where the return value will be stored */
uint64_t return_pointer; __u64 return_pointer;
/* The size of the return value. Just like "size" in "snprintf", /* The size of the return value. Just like "size" in "snprintf",
* it limits how many bytes the kernel can write. */ * it limits how many bytes the kernel can write. */
uint32_t return_size; __u32 return_size;
/* The query request id. */ /* The query request id. */
uint32_t query; __u32 query;
union { union {
struct { struct {
uint32_t id; __u32 id;
uint32_t _pad; __u32 _pad;
} mode_crtc; } mode_crtc;
struct { struct {
/** AMDGPU_HW_IP_* */ /** AMDGPU_HW_IP_* */
uint32_t type; __u32 type;
/** /**
* Index of the IP if there are more IPs of the same * Index of the IP if there are more IPs of the same
* type. Ignored by AMDGPU_INFO_HW_IP_COUNT. * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
*/ */
uint32_t ip_instance; __u32 ip_instance;
} query_hw_ip; } query_hw_ip;
struct { struct {
uint32_t dword_offset; __u32 dword_offset;
/** number of registers to read */ /** number of registers to read */
uint32_t count; __u32 count;
uint32_t instance; __u32 instance;
/** For future use, no flags defined so far */ /** For future use, no flags defined so far */
uint32_t flags; __u32 flags;
} read_mmr_reg; } read_mmr_reg;
struct { struct {
/** AMDGPU_INFO_FW_* */ /** AMDGPU_INFO_FW_* */
uint32_t fw_type; __u32 fw_type;
/** /**
* Index of the IP if there are more IPs of * Index of the IP if there are more IPs of
* the same type. * the same type.
*/ */
uint32_t ip_instance; __u32 ip_instance;
/** /**
* Index of the engine. Whether this is used depends * Index of the engine. Whether this is used depends
* on the firmware type. (e.g. MEC, SDMA) * on the firmware type. (e.g. MEC, SDMA)
*/ */
uint32_t index; __u32 index;
uint32_t _pad; __u32 _pad;
} query_fw; } query_fw;
}; };
}; };
struct drm_amdgpu_info_gds { struct drm_amdgpu_info_gds {
/** GDS GFX partition size */ /** GDS GFX partition size */
uint32_t gds_gfx_partition_size; __u32 gds_gfx_partition_size;
/** GDS compute partition size */ /** GDS compute partition size */
uint32_t compute_partition_size; __u32 compute_partition_size;
/** total GDS memory size */ /** total GDS memory size */
uint32_t gds_total_size; __u32 gds_total_size;
/** GWS size per GFX partition */ /** GWS size per GFX partition */
uint32_t gws_per_gfx_partition; __u32 gws_per_gfx_partition;
/** GSW size per compute partition */ /** GSW size per compute partition */
uint32_t gws_per_compute_partition; __u32 gws_per_compute_partition;
/** OA size per GFX partition */ /** OA size per GFX partition */
uint32_t oa_per_gfx_partition; __u32 oa_per_gfx_partition;
/** OA size per compute partition */ /** OA size per compute partition */
uint32_t oa_per_compute_partition; __u32 oa_per_compute_partition;
uint32_t _pad; __u32 _pad;
}; };
struct drm_amdgpu_info_vram_gtt { struct drm_amdgpu_info_vram_gtt {
uint64_t vram_size; __u64 vram_size;
uint64_t vram_cpu_accessible_size; __u64 vram_cpu_accessible_size;
uint64_t gtt_size; __u64 gtt_size;
}; };
struct drm_amdgpu_info_firmware { struct drm_amdgpu_info_firmware {
uint32_t ver; __u32 ver;
uint32_t feature; __u32 feature;
}; };
#define AMDGPU_VRAM_TYPE_UNKNOWN 0 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
...@@ -576,61 +576,61 @@ struct drm_amdgpu_info_firmware { ...@@ -576,61 +576,61 @@ struct drm_amdgpu_info_firmware {
struct drm_amdgpu_info_device { struct drm_amdgpu_info_device {
/** PCI Device ID */ /** PCI Device ID */
uint32_t device_id; __u32 device_id;
/** Internal chip revision: A0, A1, etc.) */ /** Internal chip revision: A0, A1, etc.) */
uint32_t chip_rev; __u32 chip_rev;
uint32_t external_rev; __u32 external_rev;
/** Revision id in PCI Config space */ /** Revision id in PCI Config space */
uint32_t pci_rev; __u32 pci_rev;
uint32_t family; __u32 family;
uint32_t num_shader_engines; __u32 num_shader_engines;
uint32_t num_shader_arrays_per_engine; __u32 num_shader_arrays_per_engine;
/* in KHz */ /* in KHz */
uint32_t gpu_counter_freq; __u32 gpu_counter_freq;
uint64_t max_engine_clock; __u64 max_engine_clock;
uint64_t max_memory_clock; __u64 max_memory_clock;
/* cu information */ /* cu information */
uint32_t cu_active_number; __u32 cu_active_number;
uint32_t cu_ao_mask; __u32 cu_ao_mask;
uint32_t cu_bitmap[4][4]; __u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */ /** Render backend pipe mask. One render backend is CB+DB. */
uint32_t enabled_rb_pipes_mask; __u32 enabled_rb_pipes_mask;
uint32_t num_rb_pipes; __u32 num_rb_pipes;
uint32_t num_hw_gfx_contexts; __u32 num_hw_gfx_contexts;
uint32_t _pad; __u32 _pad;
uint64_t ids_flags; __u64 ids_flags;
/** Starting virtual address for UMDs. */ /** Starting virtual address for UMDs. */
uint64_t virtual_address_offset; __u64 virtual_address_offset;
/** The maximum virtual address */ /** The maximum virtual address */
uint64_t virtual_address_max; __u64 virtual_address_max;
/** Required alignment of virtual addresses. */ /** Required alignment of virtual addresses. */
uint32_t virtual_address_alignment; __u32 virtual_address_alignment;
/** Page table entry - fragment size */ /** Page table entry - fragment size */
uint32_t pte_fragment_size; __u32 pte_fragment_size;
uint32_t gart_page_size; __u32 gart_page_size;
/** constant engine ram size*/ /** constant engine ram size*/
uint32_t ce_ram_size; __u32 ce_ram_size;
/** video memory type info*/ /** video memory type info*/
uint32_t vram_type; __u32 vram_type;
/** video memory bit width*/ /** video memory bit width*/
uint32_t vram_bit_width; __u32 vram_bit_width;
/* vce harvesting instance */ /* vce harvesting instance */
uint32_t vce_harvest_config; __u32 vce_harvest_config;
}; };
struct drm_amdgpu_info_hw_ip { struct drm_amdgpu_info_hw_ip {
/** Version of h/w IP */ /** Version of h/w IP */
uint32_t hw_ip_version_major; __u32 hw_ip_version_major;
uint32_t hw_ip_version_minor; __u32 hw_ip_version_minor;
/** Capabilities */ /** Capabilities */
uint64_t capabilities_flags; __u64 capabilities_flags;
/** command buffer address start alignment*/ /** command buffer address start alignment*/
uint32_t ib_start_alignment; __u32 ib_start_alignment;
/** command buffer size alignment*/ /** command buffer size alignment*/
uint32_t ib_size_alignment; __u32 ib_size_alignment;
/** Bitmask of available rings. Bit 0 means ring 0, etc. */ /** Bitmask of available rings. Bit 0 means ring 0, etc. */
uint32_t available_rings; __u32 available_rings;
uint32_t _pad; __u32 _pad;
}; };
/* /*
......
include/uapi/drm/armada_drm.h
View file @ 663a233e
...@@ -9,6 +9,8 @@ ...@@ -9,6 +9,8 @@
#ifndef DRM_ARMADA_IOCTL_H #ifndef DRM_ARMADA_IOCTL_H
#define DRM_ARMADA_IOCTL_H #define DRM_ARMADA_IOCTL_H
#include "drm.h"
#define DRM_ARMADA_GEM_CREATE 0x00 #define DRM_ARMADA_GEM_CREATE 0x00
#define DRM_ARMADA_GEM_MMAP 0x02 #define DRM_ARMADA_GEM_MMAP 0x02
#define DRM_ARMADA_GEM_PWRITE 0x03 #define DRM_ARMADA_GEM_PWRITE 0x03
......
include/uapi/drm/drm.h
View file @ 663a233e
...@@ -54,6 +54,7 @@ typedef int32_t __s32; ...@@ -54,6 +54,7 @@ typedef int32_t __s32;
typedef uint32_t __u32; typedef uint32_t __u32;
typedef int64_t __s64; typedef int64_t __s64;
typedef uint64_t __u64; typedef uint64_t __u64;
typedef size_t __kernel_size_t;
typedef unsigned long drm_handle_t; typedef unsigned long drm_handle_t;
#endif #endif
...@@ -129,11 +130,11 @@ struct drm_version { ...@@ -129,11 +130,11 @@ struct drm_version {
int version_major; /**< Major version */ int version_major; /**< Major version */
int version_minor; /**< Minor version */ int version_minor; /**< Minor version */
int version_patchlevel; /**< Patch level */ int version_patchlevel; /**< Patch level */
size_t name_len; /**< Length of name buffer */ __kernel_size_t name_len; /**< Length of name buffer */
char __user *name; /**< Name of driver */ char __user *name; /**< Name of driver */
size_t date_len; /**< Length of date buffer */ __kernel_size_t date_len; /**< Length of date buffer */
char __user *date; /**< User-space buffer to hold date */ char __user *date; /**< User-space buffer to hold date */
size_t desc_len; /**< Length of desc buffer */ __kernel_size_t desc_len; /**< Length of desc buffer */
char __user *desc; /**< User-space buffer to hold desc */ char __user *desc; /**< User-space buffer to hold desc */
}; };
...@@ -143,7 +144,7 @@ struct drm_version { ...@@ -143,7 +144,7 @@ struct drm_version {
* \sa drmGetBusid() and drmSetBusId(). * \sa drmGetBusid() and drmSetBusId().
*/ */
struct drm_unique { struct drm_unique {
size_t unique_len; /**< Length of unique */ __kernel_size_t unique_len; /**< Length of unique */
char __user *unique; /**< Unique name for driver instantiation */ char __user *unique; /**< Unique name for driver instantiation */
}; };
......
include/uapi/drm/drm_fourcc.h
View file @ 663a233e
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#ifndef DRM_FOURCC_H #ifndef DRM_FOURCC_H
#define DRM_FOURCC_H #define DRM_FOURCC_H
#include <linux/types.h> #include "drm.h"
#define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \ #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
((__u32)(c) << 16) | ((__u32)(d) << 24)) ((__u32)(c) << 16) | ((__u32)(d) << 24))
......
include/uapi/drm/drm_mode.h
View file @ 663a233e
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#ifndef _DRM_MODE_H #ifndef _DRM_MODE_H
#define _DRM_MODE_H #define _DRM_MODE_H
#include <linux/types.h> #include "drm.h"
#define DRM_DISPLAY_INFO_LEN 32 #define DRM_DISPLAY_INFO_LEN 32
#define DRM_CONNECTOR_NAME_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32
...@@ -526,14 +526,14 @@ struct drm_mode_crtc_page_flip { ...@@ -526,14 +526,14 @@ struct drm_mode_crtc_page_flip {
/* create a dumb scanout buffer */ /* create a dumb scanout buffer */
struct drm_mode_create_dumb { struct drm_mode_create_dumb {
uint32_t height; __u32 height;
uint32_t width; __u32 width;
uint32_t bpp; __u32 bpp;
uint32_t flags; __u32 flags;
/* handle, pitch, size will be returned */ /* handle, pitch, size will be returned */
uint32_t handle; __u32 handle;
uint32_t pitch; __u32 pitch;
uint64_t size; __u64 size;
}; };
/* set up for mmap of a dumb scanout buffer */ /* set up for mmap of a dumb scanout buffer */
...@@ -550,7 +550,7 @@ struct drm_mode_map_dumb { ...@@ -550,7 +550,7 @@ struct drm_mode_map_dumb {
}; };
struct drm_mode_destroy_dumb { struct drm_mode_destroy_dumb {
uint32_t handle; __u32 handle;
}; };
/* page-flip flags are valid, plus: */ /* page-flip flags are valid, plus: */
......
include/uapi/drm/drm_sarea.h
View file @ 663a233e
...@@ -32,7 +32,7 @@ ...@@ -32,7 +32,7 @@
#ifndef _DRM_SAREA_H_ #ifndef _DRM_SAREA_H_
#define _DRM_SAREA_H_ #define _DRM_SAREA_H_
#include <drm/drm.h> #include "drm.h"
/* SAREA area needs to be at least a page */ /* SAREA area needs to be at least a page */
#if defined(__alpha__) #if defined(__alpha__)
......
include/uapi/drm/exynos_drm.h
View file @ 663a233e
...@@ -15,7 +15,7 @@ ...@@ -15,7 +15,7 @@
#ifndef _UAPI_EXYNOS_DRM_H_ #ifndef _UAPI_EXYNOS_DRM_H_
#define _UAPI_EXYNOS_DRM_H_ #define _UAPI_EXYNOS_DRM_H_
#include <drm/drm.h> #include "drm.h"
/** /**
* User-desired buffer creation information structure. * User-desired buffer creation information structure.
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
* - this handle will be set by gem module of kernel side. * - this handle will be set by gem module of kernel side.
*/ */
struct drm_exynos_gem_create { struct drm_exynos_gem_create {
uint64_t size; __u64 size;
unsigned int flags; unsigned int flags;
unsigned int handle; unsigned int handle;
}; };
...@@ -44,7 +44,7 @@ struct drm_exynos_gem_create { ...@@ -44,7 +44,7 @@ struct drm_exynos_gem_create {
struct drm_exynos_gem_info { struct drm_exynos_gem_info {
unsigned int handle; unsigned int handle;
unsigned int flags; unsigned int flags;
uint64_t size; __u64 size;
}; };
/** /**
...@@ -58,7 +58,7 @@ struct drm_exynos_gem_info { ...@@ -58,7 +58,7 @@ struct drm_exynos_gem_info {
struct drm_exynos_vidi_connection { struct drm_exynos_vidi_connection {
unsigned int connection; unsigned int connection;
unsigned int extensions; unsigned int extensions;
uint64_t edid; __u64 edid;
}; };
/* memory type definitions. */ /* memory type definitions. */
......
include/uapi/drm/i810_drm.h
View file @ 663a233e
#ifndef _I810_DRM_H_ #ifndef _I810_DRM_H_
#define _I810_DRM_H_ #define _I810_DRM_H_
#include <drm/drm.h> #include "drm.h"
/* WARNING: These defines must be the same as what the Xserver uses. /* WARNING: These defines must be the same as what the Xserver uses.
* if you change them, you must change the defines in the Xserver. * if you change them, you must change the defines in the Xserver.
......
include/uapi/drm/i915_drm.h
View file @ 663a233e
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#ifndef _UAPI_I915_DRM_H_ #ifndef _UAPI_I915_DRM_H_
#define _UAPI_I915_DRM_H_ #define _UAPI_I915_DRM_H_
#include <drm/drm.h> #include "drm.h"
/* Please note that modifications to all structs defined here are /* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints. * subject to backwards-compatibility constraints.
......
include/uapi/drm/mga_drm.h
View file @ 663a233e
...@@ -35,7 +35,7 @@ ...@@ -35,7 +35,7 @@
#ifndef __MGA_DRM_H__ #ifndef __MGA_DRM_H__
#define __MGA_DRM_H__ #define __MGA_DRM_H__
#include <drm/drm.h> #include "drm.h"
/* WARNING: If you change any of these defines, make sure to change the /* WARNING: If you change any of these defines, make sure to change the
* defines in the Xserver file (mga_sarea.h) * defines in the Xserver file (mga_sarea.h)
......
include/uapi/drm/msm_drm.h
View file @ 663a233e
...@@ -18,8 +18,7 @@ ...@@ -18,8 +18,7 @@
#ifndef __MSM_DRM_H__ #ifndef __MSM_DRM_H__
#define __MSM_DRM_H__ #define __MSM_DRM_H__
#include <stddef.h> #include "drm.h"
#include <drm/drm.h>
/* Please note that modifications to all structs defined here are /* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints: * subject to backwards-compatibility constraints:
......
include/uapi/drm/nouveau_drm.h
View file @ 663a233e
...@@ -27,6 +27,8 @@ ...@@ -27,6 +27,8 @@
#define DRM_NOUVEAU_EVENT_NVIF 0x80000000 #define DRM_NOUVEAU_EVENT_NVIF 0x80000000
#include <drm/drm.h>
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0) #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
...@@ -41,34 +43,34 @@ ...@@ -41,34 +43,34 @@
#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008 #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
struct drm_nouveau_gem_info { struct drm_nouveau_gem_info {
uint32_t handle; __u32 handle;
uint32_t domain; __u32 domain;
uint64_t size; __u64 size;
uint64_t offset; __u64 offset;
uint64_t map_handle; __u64 map_handle;
uint32_t tile_mode; __u32 tile_mode;
uint32_t tile_flags; __u32 tile_flags;
}; };
struct drm_nouveau_gem_new { struct drm_nouveau_gem_new {
struct drm_nouveau_gem_info info; struct drm_nouveau_gem_info info;
uint32_t channel_hint; __u32 channel_hint;
uint32_t align; __u32 align;
}; };
#define NOUVEAU_GEM_MAX_BUFFERS 1024 #define NOUVEAU_GEM_MAX_BUFFERS 1024
struct drm_nouveau_gem_pushbuf_bo_presumed { struct drm_nouveau_gem_pushbuf_bo_presumed {
uint32_t valid; __u32 valid;
uint32_t domain; __u32 domain;
uint64_t offset; __u64 offset;
}; };
struct drm_nouveau_gem_pushbuf_bo { struct drm_nouveau_gem_pushbuf_bo {
uint64_t user_priv; __u64 user_priv;
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domains; __u32 write_domains;
uint32_t valid_domains; __u32 valid_domains;
struct drm_nouveau_gem_pushbuf_bo_presumed presumed; struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
}; };
...@@ -77,46 +79,46 @@ struct drm_nouveau_gem_pushbuf_bo { ...@@ -77,46 +79,46 @@ struct drm_nouveau_gem_pushbuf_bo {
#define NOUVEAU_GEM_RELOC_OR (1 << 2) #define NOUVEAU_GEM_RELOC_OR (1 << 2)
#define NOUVEAU_GEM_MAX_RELOCS 1024 #define NOUVEAU_GEM_MAX_RELOCS 1024
struct drm_nouveau_gem_pushbuf_reloc { struct drm_nouveau_gem_pushbuf_reloc {
uint32_t reloc_bo_index; __u32 reloc_bo_index;
uint32_t reloc_bo_offset; __u32 reloc_bo_offset;
uint32_t bo_index; __u32 bo_index;
uint32_t flags; __u32 flags;
uint32_t data; __u32 data;
uint32_t vor; __u32 vor;
uint32_t tor; __u32 tor;
}; };
#define NOUVEAU_GEM_MAX_PUSH 512 #define NOUVEAU_GEM_MAX_PUSH 512
struct drm_nouveau_gem_pushbuf_push { struct drm_nouveau_gem_pushbuf_push {
uint32_t bo_index; __u32 bo_index;
uint32_t pad; __u32 pad;
uint64_t offset; __u64 offset;
uint64_t length; __u64 length;
}; };
struct drm_nouveau_gem_pushbuf { struct drm_nouveau_gem_pushbuf {
uint32_t channel; __u32 channel;
uint32_t nr_buffers; __u32 nr_buffers;
uint64_t buffers; __u64 buffers;
uint32_t nr_relocs; __u32 nr_relocs;
uint32_t nr_push; __u32 nr_push;
uint64_t relocs; __u64 relocs;
uint64_t push; __u64 push;
uint32_t suffix0; __u32 suffix0;
uint32_t suffix1; __u32 suffix1;
uint64_t vram_available; __u64 vram_available;
uint64_t gart_available; __u64 gart_available;
}; };
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
struct drm_nouveau_gem_cpu_prep { struct drm_nouveau_gem_cpu_prep {
uint32_t handle; __u32 handle;
uint32_t flags; __u32 flags;
}; };
struct drm_nouveau_gem_cpu_fini { struct drm_nouveau_gem_cpu_fini {
uint32_t handle; __u32 handle;
}; };
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */ #define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
......
include/uapi/drm/omap_drm.h
View file @ 663a233e
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
#ifndef __OMAP_DRM_H__ #ifndef __OMAP_DRM_H__
#define __OMAP_DRM_H__ #define __OMAP_DRM_H__
#include <drm/drm.h> #include "drm.h"
/* Please note that modifications to all structs defined here are /* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints. * subject to backwards-compatibility constraints.
......
include/uapi/drm/qxl_drm.h
View file @ 663a233e
...@@ -24,13 +24,12 @@ ...@@ -24,13 +24,12 @@
#ifndef QXL_DRM_H #ifndef QXL_DRM_H
#define QXL_DRM_H #define QXL_DRM_H
#include <stddef.h> #include "drm.h"
#include "drm/drm.h"
/* Please note that modifications to all structs defined here are /* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints. * subject to backwards-compatibility constraints.
* *
* Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
* compatibility Keep fields aligned to their size * compatibility Keep fields aligned to their size
*/ */
...@@ -48,14 +47,14 @@ ...@@ -48,14 +47,14 @@
#define DRM_QXL_ALLOC_SURF 0x06 #define DRM_QXL_ALLOC_SURF 0x06
struct drm_qxl_alloc { struct drm_qxl_alloc {
uint32_t size; __u32 size;
uint32_t handle; /* 0 is an invalid handle */ __u32 handle; /* 0 is an invalid handle */
}; };
struct drm_qxl_map { struct drm_qxl_map {
uint64_t offset; /* use for mmap system call */ __u64 offset; /* use for mmap system call */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
/* /*
...@@ -68,59 +67,59 @@ struct drm_qxl_map { ...@@ -68,59 +67,59 @@ struct drm_qxl_map {
#define QXL_RELOC_TYPE_SURF 2 #define QXL_RELOC_TYPE_SURF 2
struct drm_qxl_reloc { struct drm_qxl_reloc {
uint64_t src_offset; /* offset into src_handle or src buffer */ __u64 src_offset; /* offset into src_handle or src buffer */
uint64_t dst_offset; /* offset in dest handle */ __u64 dst_offset; /* offset in dest handle */
uint32_t src_handle; /* dest handle to compute address from */ __u32 src_handle; /* dest handle to compute address from */
uint32_t dst_handle; /* 0 if to command buffer */ __u32 dst_handle; /* 0 if to command buffer */
uint32_t reloc_type; __u32 reloc_type;
uint32_t pad; __u32 pad;
}; };
struct drm_qxl_command { struct drm_qxl_command {
uint64_t __user command; /* void* */ __u64 __user command; /* void* */
uint64_t __user relocs; /* struct drm_qxl_reloc* */ __u64 __user relocs; /* struct drm_qxl_reloc* */
uint32_t type; __u32 type;
uint32_t command_size; __u32 command_size;
uint32_t relocs_num; __u32 relocs_num;
uint32_t pad; __u32 pad;
}; };
/* XXX: call it drm_qxl_commands? */ /* XXX: call it drm_qxl_commands? */
struct drm_qxl_execbuffer { struct drm_qxl_execbuffer {
uint32_t flags; /* for future use */ __u32 flags; /* for future use */
uint32_t commands_num; __u32 commands_num;
uint64_t __user commands; /* struct drm_qxl_command* */ __u64 __user commands; /* struct drm_qxl_command* */
}; };
struct drm_qxl_update_area { struct drm_qxl_update_area {
uint32_t handle; __u32 handle;
uint32_t top; __u32 top;
uint32_t left; __u32 left;
uint32_t bottom; __u32 bottom;
uint32_t right; __u32 right;
uint32_t pad; __u32 pad;
}; };
#define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */ #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
#define QXL_PARAM_MAX_RELOCS 2 #define QXL_PARAM_MAX_RELOCS 2
struct drm_qxl_getparam { struct drm_qxl_getparam {
uint64_t param; __u64 param;
uint64_t value; __u64 value;
}; };
/* these are one bit values */ /* these are one bit values */
struct drm_qxl_clientcap { struct drm_qxl_clientcap {
uint32_t index; __u32 index;
uint32_t pad; __u32 pad;
}; };
struct drm_qxl_alloc_surf { struct drm_qxl_alloc_surf {
uint32_t format; __u32 format;
uint32_t width; __u32 width;
uint32_t height; __u32 height;
int32_t stride; __s32 stride;
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
#define DRM_IOCTL_QXL_ALLOC \ #define DRM_IOCTL_QXL_ALLOC \
......
include/uapi/drm/r128_drm.h
View file @ 663a233e
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
#ifndef __R128_DRM_H__ #ifndef __R128_DRM_H__
#define __R128_DRM_H__ #define __R128_DRM_H__
#include <drm/drm.h> #include "drm.h"
/* WARNING: If you change any of these defines, make sure to change the /* WARNING: If you change any of these defines, make sure to change the
* defines in the X server file (r128_sarea.h) * defines in the X server file (r128_sarea.h)
......
include/uapi/drm/radeon_drm.h
View file @ 663a233e
...@@ -793,9 +793,9 @@ typedef struct drm_radeon_surface_free { ...@@ -793,9 +793,9 @@ typedef struct drm_radeon_surface_free {
#define RADEON_GEM_DOMAIN_VRAM 0x4 #define RADEON_GEM_DOMAIN_VRAM 0x4
struct drm_radeon_gem_info { struct drm_radeon_gem_info {
uint64_t gart_size; __u64 gart_size;
uint64_t vram_size; __u64 vram_size;
uint64_t vram_visible; __u64 vram_visible;
}; };
#define RADEON_GEM_NO_BACKING_STORE (1 << 0) #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
...@@ -807,11 +807,11 @@ struct drm_radeon_gem_info { ...@@ -807,11 +807,11 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create { struct drm_radeon_gem_create {
uint64_t size; __u64 size;
uint64_t alignment; __u64 alignment;
uint32_t handle; __u32 handle;
uint32_t initial_domain; __u32 initial_domain;
uint32_t flags; __u32 flags;
}; };
/* /*
...@@ -825,10 +825,10 @@ struct drm_radeon_gem_create { ...@@ -825,10 +825,10 @@ struct drm_radeon_gem_create {
#define RADEON_GEM_USERPTR_REGISTER (1 << 3) #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
struct drm_radeon_gem_userptr { struct drm_radeon_gem_userptr {
uint64_t addr; __u64 addr;
uint64_t size; __u64 size;
uint32_t flags; __u32 flags;
uint32_t handle; __u32 handle;
}; };
#define RADEON_TILING_MACRO 0x1 #define RADEON_TILING_MACRO 0x1
...@@ -850,72 +850,72 @@ struct drm_radeon_gem_userptr { ...@@ -850,72 +850,72 @@ struct drm_radeon_gem_userptr {
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling { struct drm_radeon_gem_set_tiling {
uint32_t handle; __u32 handle;
uint32_t tiling_flags; __u32 tiling_flags;
uint32_t pitch; __u32 pitch;
}; };
struct drm_radeon_gem_get_tiling { struct drm_radeon_gem_get_tiling {
uint32_t handle; __u32 handle;
uint32_t tiling_flags; __u32 tiling_flags;
uint32_t pitch; __u32 pitch;
}; };
struct drm_radeon_gem_mmap { struct drm_radeon_gem_mmap {
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
uint64_t offset; __u64 offset;
uint64_t size; __u64 size;
uint64_t addr_ptr; __u64 addr_ptr;
}; };
struct drm_radeon_gem_set_domain { struct drm_radeon_gem_set_domain {
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domain; __u32 write_domain;
}; };
struct drm_radeon_gem_wait_idle { struct drm_radeon_gem_wait_idle {
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
struct drm_radeon_gem_busy { struct drm_radeon_gem_busy {
uint32_t handle; __u32 handle;
uint32_t domain; __u32 domain;
}; };
struct drm_radeon_gem_pread { struct drm_radeon_gem_pread {
/** Handle for the object being read. */ /** Handle for the object being read. */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
/** Offset into the object to read from */ /** Offset into the object to read from */
uint64_t offset; __u64 offset;
/** Length of data to read */ /** Length of data to read */
uint64_t size; __u64 size;
/** Pointer to write the data into. */ /** Pointer to write the data into. */
/* void *, but pointers are not 32/64 compatible */ /* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr; __u64 data_ptr;
}; };
struct drm_radeon_gem_pwrite { struct drm_radeon_gem_pwrite {
/** Handle for the object being written to. */ /** Handle for the object being written to. */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
/** Offset into the object to write to */ /** Offset into the object to write to */
uint64_t offset; __u64 offset;
/** Length of data to write */ /** Length of data to write */
uint64_t size; __u64 size;
/** Pointer to read the data from. */ /** Pointer to read the data from. */
/* void *, but pointers are not 32/64 compatible */ /* void *, but pointers are not 32/64 compatible */
uint64_t data_ptr; __u64 data_ptr;
}; };
/* Sets or returns a value associated with a buffer. */ /* Sets or returns a value associated with a buffer. */
struct drm_radeon_gem_op { struct drm_radeon_gem_op {
uint32_t handle; /* buffer */ __u32 handle; /* buffer */
uint32_t op; /* RADEON_GEM_OP_* */ __u32 op; /* RADEON_GEM_OP_* */
uint64_t value; /* input or return value */ __u64 value; /* input or return value */
}; };
#define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
...@@ -935,11 +935,11 @@ struct drm_radeon_gem_op { ...@@ -935,11 +935,11 @@ struct drm_radeon_gem_op {
#define RADEON_VM_PAGE_SNOOPED (1 << 4) #define RADEON_VM_PAGE_SNOOPED (1 << 4)
struct drm_radeon_gem_va { struct drm_radeon_gem_va {
uint32_t handle; __u32 handle;
uint32_t operation; __u32 operation;
uint32_t vm_id; __u32 vm_id;
uint32_t flags; __u32 flags;
uint64_t offset; __u64 offset;
}; };
#define RADEON_CHUNK_ID_RELOCS 0x01 #define RADEON_CHUNK_ID_RELOCS 0x01
...@@ -961,29 +961,29 @@ struct drm_radeon_gem_va { ...@@ -961,29 +961,29 @@ struct drm_radeon_gem_va {
/* 0 = normal, + = higher priority, - = lower priority */ /* 0 = normal, + = higher priority, - = lower priority */
struct drm_radeon_cs_chunk { struct drm_radeon_cs_chunk {
uint32_t chunk_id; __u32 chunk_id;
uint32_t length_dw; __u32 length_dw;
uint64_t chunk_data; __u64 chunk_data;
}; };
/* drm_radeon_cs_reloc.flags */ /* drm_radeon_cs_reloc.flags */
#define RADEON_RELOC_PRIO_MASK (0xf << 0) #define RADEON_RELOC_PRIO_MASK (0xf << 0)
struct drm_radeon_cs_reloc { struct drm_radeon_cs_reloc {
uint32_t handle; __u32 handle;
uint32_t read_domains; __u32 read_domains;
uint32_t write_domain; __u32 write_domain;
uint32_t flags; __u32 flags;
}; };
struct drm_radeon_cs { struct drm_radeon_cs {
uint32_t num_chunks; __u32 num_chunks;
uint32_t cs_id; __u32 cs_id;
/* this points to uint64_t * which point to cs chunks */ /* this points to __u64 * which point to cs chunks */
uint64_t chunks; __u64 chunks;
/* updates to the limits after this CS ioctl */ /* updates to the limits after this CS ioctl */
uint64_t gart_limit; __u64 gart_limit;
uint64_t vram_limit; __u64 vram_limit;
}; };
#define RADEON_INFO_DEVICE_ID 0x00 #define RADEON_INFO_DEVICE_ID 0x00
...@@ -1042,9 +1042,9 @@ struct drm_radeon_cs { ...@@ -1042,9 +1042,9 @@ struct drm_radeon_cs {
#define RADEON_INFO_GPU_RESET_COUNTER 0x26 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
struct drm_radeon_info { struct drm_radeon_info {
uint32_t request; __u32 request;
uint32_t pad; __u32 pad;
uint64_t value; __u64 value;
}; };
/* Those correspond to the tile index to use, this is to explicitly state /* Those correspond to the tile index to use, this is to explicitly state
......
include/uapi/drm/savage_drm.h
View file @ 663a233e
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#ifndef __SAVAGE_DRM_H__ #ifndef __SAVAGE_DRM_H__
#define __SAVAGE_DRM_H__ #define __SAVAGE_DRM_H__
#include <drm/drm.h> #include "drm.h"
#ifndef __SAVAGE_SAREA_DEFINES__ #ifndef __SAVAGE_SAREA_DEFINES__
#define __SAVAGE_SAREA_DEFINES__ #define __SAVAGE_SAREA_DEFINES__
......
include/uapi/drm/tegra_drm.h
View file @ 663a233e
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#ifndef _UAPI_TEGRA_DRM_H_ #ifndef _UAPI_TEGRA_DRM_H_
#define _UAPI_TEGRA_DRM_H_ #define _UAPI_TEGRA_DRM_H_
#include <drm/drm.h> #include "drm.h"
#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
......
include/uapi/drm/via_drm.h
View file @ 663a233e
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#ifndef _VIA_DRM_H_ #ifndef _VIA_DRM_H_
#define _VIA_DRM_H_ #define _VIA_DRM_H_
#include <drm/drm.h> #include "drm.h"
/* WARNING: These defines must be the same as what the Xserver uses. /* WARNING: These defines must be the same as what the Xserver uses.
* if you change them, you must change the defines in the Xserver. * if you change them, you must change the defines in the Xserver.
...@@ -33,9 +33,6 @@ ...@@ -33,9 +33,6 @@
#ifndef _VIA_DEFINES_ #ifndef _VIA_DEFINES_
#define _VIA_DEFINES_ #define _VIA_DEFINES_
#ifndef __KERNEL__
#include "via_drmclient.h"
#endif
#define VIA_NR_SAREA_CLIPRECTS 8 #define VIA_NR_SAREA_CLIPRECTS 8
#define VIA_NR_XVMC_PORTS 10 #define VIA_NR_XVMC_PORTS 10
......
include/uapi/drm/virtgpu_drm.h
View file @ 663a233e
...@@ -24,13 +24,12 @@ ...@@ -24,13 +24,12 @@
#ifndef VIRTGPU_DRM_H #ifndef VIRTGPU_DRM_H
#define VIRTGPU_DRM_H #define VIRTGPU_DRM_H
#include <stddef.h> #include "drm.h"
#include "drm/drm.h"
/* Please note that modifications to all structs defined here are /* Please note that modifications to all structs defined here are
* subject to backwards-compatibility constraints. * subject to backwards-compatibility constraints.
* *
* Do not use pointers, use uint64_t instead for 32 bit / 64 bit user/kernel * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
* compatibility Keep fields aligned to their size * compatibility Keep fields aligned to their size
*/ */
...@@ -45,88 +44,88 @@ ...@@ -45,88 +44,88 @@
#define DRM_VIRTGPU_GET_CAPS 0x09 #define DRM_VIRTGPU_GET_CAPS 0x09
struct drm_virtgpu_map { struct drm_virtgpu_map {
uint64_t offset; /* use for mmap system call */ __u64 offset; /* use for mmap system call */
uint32_t handle; __u32 handle;
uint32_t pad; __u32 pad;
}; };
struct drm_virtgpu_execbuffer { struct drm_virtgpu_execbuffer {
uint32_t flags; /* for future use */ __u32 flags; /* for future use */
uint32_t size; __u32 size;
uint64_t command; /* void* */ __u64 command; /* void* */
uint64_t bo_handles; __u64 bo_handles;
uint32_t num_bo_handles; __u32 num_bo_handles;
uint32_t pad; __u32 pad;
}; };
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
struct drm_virtgpu_getparam { struct drm_virtgpu_getparam {
uint64_t param; __u64 param;
uint64_t value; __u64 value;
}; };
/* NO_BO flags? NO resource flag? */ /* NO_BO flags? NO resource flag? */
/* resource flag for y_0_top */ /* resource flag for y_0_top */
struct drm_virtgpu_resource_create { struct drm_virtgpu_resource_create {
uint32_t target; __u32 target;
uint32_t format; __u32 format;
uint32_t bind; __u32 bind;
uint32_t width; __u32 width;
uint32_t height; __u32 height;
uint32_t depth; __u32 depth;
uint32_t array_size; __u32 array_size;
uint32_t last_level; __u32 last_level;
uint32_t nr_samples; __u32 nr_samples;
uint32_t flags; __u32 flags;
uint32_t bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
uint32_t res_handle; /* returned by kernel */ __u32 res_handle; /* returned by kernel */
uint32_t size; /* validate transfer in the host */ __u32 size; /* validate transfer in the host */
uint32_t stride; /* validate transfer in the host */ __u32 stride; /* validate transfer in the host */
}; };
struct drm_virtgpu_resource_info { struct drm_virtgpu_resource_info {
uint32_t bo_handle; __u32 bo_handle;
uint32_t res_handle; __u32 res_handle;
uint32_t size; __u32 size;
uint32_t stride; __u32 stride;
}; };
struct drm_virtgpu_3d_box { struct drm_virtgpu_3d_box {
uint32_t x; __u32 x;
uint32_t y; __u32 y;
uint32_t z; __u32 z;
uint32_t w; __u32 w;
uint32_t h; __u32 h;
uint32_t d; __u32 d;
}; };
struct drm_virtgpu_3d_transfer_to_host { struct drm_virtgpu_3d_transfer_to_host {
uint32_t bo_handle; __u32 bo_handle;
struct drm_virtgpu_3d_box box; struct drm_virtgpu_3d_box box;
uint32_t level; __u32 level;
uint32_t offset; __u32 offset;
}; };
struct drm_virtgpu_3d_transfer_from_host { struct drm_virtgpu_3d_transfer_from_host {
uint32_t bo_handle; __u32 bo_handle;
struct drm_virtgpu_3d_box box; struct drm_virtgpu_3d_box box;
uint32_t level; __u32 level;
uint32_t offset; __u32 offset;
}; };
#define VIRTGPU_WAIT_NOWAIT 1 /* like it */ #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
struct drm_virtgpu_3d_wait { struct drm_virtgpu_3d_wait {
uint32_t handle; /* 0 is an invalid handle */ __u32 handle; /* 0 is an invalid handle */
uint32_t flags; __u32 flags;
}; };
struct drm_virtgpu_get_caps { struct drm_virtgpu_get_caps {
uint32_t cap_set_id; __u32 cap_set_id;
uint32_t cap_set_ver; __u32 cap_set_ver;
uint64_t addr; __u64 addr;
uint32_t size; __u32 size;
uint32_t pad; __u32 pad;
}; };
#define DRM_IOCTL_VIRTGPU_MAP \ #define DRM_IOCTL_VIRTGPU_MAP \
......
include/uapi/drm/vmwgfx_drm.h
View file @ 663a233e
...@@ -28,9 +28,7 @@ ...@@ -28,9 +28,7 @@
#ifndef __VMWGFX_DRM_H__ #ifndef __VMWGFX_DRM_H__
#define __VMWGFX_DRM_H__ #define __VMWGFX_DRM_H__
#ifndef __KERNEL__ #include "drm.h"
#include <drm/drm.h>
#endif
#define DRM_VMW_MAX_SURFACE_FACES 6 #define DRM_VMW_MAX_SURFACE_FACES 6
#define DRM_VMW_MAX_MIP_LEVELS 24 #define DRM_VMW_MAX_MIP_LEVELS 24
...@@ -111,9 +109,9 @@ enum drm_vmw_handle_type { ...@@ -111,9 +109,9 @@ enum drm_vmw_handle_type {
*/ */
struct drm_vmw_getparam_arg { struct drm_vmw_getparam_arg {
uint64_t value; __u64 value;
uint32_t param; __u32 param;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -134,8 +132,8 @@ struct drm_vmw_getparam_arg { ...@@ -134,8 +132,8 @@ struct drm_vmw_getparam_arg {
*/ */
struct drm_vmw_context_arg { struct drm_vmw_context_arg {
int32_t cid; __s32 cid;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -165,7 +163,7 @@ struct drm_vmw_context_arg { ...@@ -165,7 +163,7 @@ struct drm_vmw_context_arg {
* @mip_levels: Number of mip levels for each face. * @mip_levels: Number of mip levels for each face.
* An unused face should have 0 encoded. * An unused face should have 0 encoded.
* @size_addr: Address of a user-space array of sruct drm_vmw_size * @size_addr: Address of a user-space array of sruct drm_vmw_size
* cast to an uint64_t for 32-64 bit compatibility. * cast to an __u64 for 32-64 bit compatibility.
* The size of the array should equal the total number of mipmap levels. * The size of the array should equal the total number of mipmap levels.
* @shareable: Boolean whether other clients (as identified by file descriptors) * @shareable: Boolean whether other clients (as identified by file descriptors)
* may reference this surface. * may reference this surface.
...@@ -177,12 +175,12 @@ struct drm_vmw_context_arg { ...@@ -177,12 +175,12 @@ struct drm_vmw_context_arg {
*/ */
struct drm_vmw_surface_create_req { struct drm_vmw_surface_create_req {
uint32_t flags; __u32 flags;
uint32_t format; __u32 format;
uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
uint64_t size_addr; __u64 size_addr;
int32_t shareable; __s32 shareable;
int32_t scanout; __s32 scanout;
}; };
/** /**
...@@ -197,7 +195,7 @@ struct drm_vmw_surface_create_req { ...@@ -197,7 +195,7 @@ struct drm_vmw_surface_create_req {
*/ */
struct drm_vmw_surface_arg { struct drm_vmw_surface_arg {
int32_t sid; __s32 sid;
enum drm_vmw_handle_type handle_type; enum drm_vmw_handle_type handle_type;
}; };
...@@ -213,10 +211,10 @@ struct drm_vmw_surface_arg { ...@@ -213,10 +211,10 @@ struct drm_vmw_surface_arg {
*/ */
struct drm_vmw_size { struct drm_vmw_size {
uint32_t width; __u32 width;
uint32_t height; __u32 height;
uint32_t depth; __u32 depth;
uint32_t pad64; __u32 pad64;
}; };
/** /**
...@@ -284,13 +282,13 @@ union drm_vmw_surface_reference_arg { ...@@ -284,13 +282,13 @@ union drm_vmw_surface_reference_arg {
/** /**
* struct drm_vmw_execbuf_arg * struct drm_vmw_execbuf_arg
* *
* @commands: User-space address of a command buffer cast to an uint64_t. * @commands: User-space address of a command buffer cast to an __u64.
* @command-size: Size in bytes of the command buffer. * @command-size: Size in bytes of the command buffer.
* @throttle-us: Sleep until software is less than @throttle_us * @throttle-us: Sleep until software is less than @throttle_us
* microseconds ahead of hardware. The driver may round this value * microseconds ahead of hardware. The driver may round this value
* to the nearest kernel tick. * to the nearest kernel tick.
* @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an
* uint64_t. * __u64.
* @version: Allows expanding the execbuf ioctl parameters without breaking * @version: Allows expanding the execbuf ioctl parameters without breaking
* backwards compatibility, since user-space will always tell the kernel * backwards compatibility, since user-space will always tell the kernel
* which version it uses. * which version it uses.
...@@ -302,14 +300,14 @@ union drm_vmw_surface_reference_arg { ...@@ -302,14 +300,14 @@ union drm_vmw_surface_reference_arg {
#define DRM_VMW_EXECBUF_VERSION 2 #define DRM_VMW_EXECBUF_VERSION 2
struct drm_vmw_execbuf_arg { struct drm_vmw_execbuf_arg {
uint64_t commands; __u64 commands;
uint32_t command_size; __u32 command_size;
uint32_t throttle_us; __u32 throttle_us;
uint64_t fence_rep; __u64 fence_rep;
uint32_t version; __u32 version;
uint32_t flags; __u32 flags;
uint32_t context_handle; __u32 context_handle;
uint32_t pad64; __u32 pad64;
}; };
/** /**
...@@ -338,12 +336,12 @@ struct drm_vmw_execbuf_arg { ...@@ -338,12 +336,12 @@ struct drm_vmw_execbuf_arg {
*/ */
struct drm_vmw_fence_rep { struct drm_vmw_fence_rep {
uint32_t handle; __u32 handle;
uint32_t mask; __u32 mask;
uint32_t seqno; __u32 seqno;
uint32_t passed_seqno; __u32 passed_seqno;
uint32_t pad64; __u32 pad64;
int32_t error; __s32 error;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -373,8 +371,8 @@ struct drm_vmw_fence_rep { ...@@ -373,8 +371,8 @@ struct drm_vmw_fence_rep {
*/ */
struct drm_vmw_alloc_dmabuf_req { struct drm_vmw_alloc_dmabuf_req {
uint32_t size; __u32 size;
uint32_t pad64; __u32 pad64;
}; };
/** /**
...@@ -391,11 +389,11 @@ struct drm_vmw_alloc_dmabuf_req { ...@@ -391,11 +389,11 @@ struct drm_vmw_alloc_dmabuf_req {
*/ */
struct drm_vmw_dmabuf_rep { struct drm_vmw_dmabuf_rep {
uint64_t map_handle; __u64 map_handle;
uint32_t handle; __u32 handle;
uint32_t cur_gmr_id; __u32 cur_gmr_id;
uint32_t cur_gmr_offset; __u32 cur_gmr_offset;
uint32_t pad64; __u32 pad64;
}; };
/** /**
...@@ -428,8 +426,8 @@ union drm_vmw_alloc_dmabuf_arg { ...@@ -428,8 +426,8 @@ union drm_vmw_alloc_dmabuf_arg {
*/ */
struct drm_vmw_unref_dmabuf_arg { struct drm_vmw_unref_dmabuf_arg {
uint32_t handle; __u32 handle;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -452,10 +450,10 @@ struct drm_vmw_unref_dmabuf_arg { ...@@ -452,10 +450,10 @@ struct drm_vmw_unref_dmabuf_arg {
*/ */
struct drm_vmw_rect { struct drm_vmw_rect {
int32_t x; __s32 x;
int32_t y; __s32 y;
uint32_t w; __u32 w;
uint32_t h; __u32 h;
}; };
/** /**
...@@ -477,21 +475,21 @@ struct drm_vmw_rect { ...@@ -477,21 +475,21 @@ struct drm_vmw_rect {
*/ */
struct drm_vmw_control_stream_arg { struct drm_vmw_control_stream_arg {
uint32_t stream_id; __u32 stream_id;
uint32_t enabled; __u32 enabled;
uint32_t flags; __u32 flags;
uint32_t color_key; __u32 color_key;
uint32_t handle; __u32 handle;
uint32_t offset; __u32 offset;
int32_t format; __s32 format;
uint32_t size; __u32 size;
uint32_t width; __u32 width;
uint32_t height; __u32 height;
uint32_t pitch[3]; __u32 pitch[3];
uint32_t pad64; __u32 pad64;
struct drm_vmw_rect src; struct drm_vmw_rect src;
struct drm_vmw_rect dst; struct drm_vmw_rect dst;
}; };
...@@ -519,12 +517,12 @@ struct drm_vmw_control_stream_arg { ...@@ -519,12 +517,12 @@ struct drm_vmw_control_stream_arg {
*/ */
struct drm_vmw_cursor_bypass_arg { struct drm_vmw_cursor_bypass_arg {
uint32_t flags; __u32 flags;
uint32_t crtc_id; __u32 crtc_id;
int32_t xpos; __s32 xpos;
int32_t ypos; __s32 ypos;
int32_t xhot; __s32 xhot;
int32_t yhot; __s32 yhot;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -542,8 +540,8 @@ struct drm_vmw_cursor_bypass_arg { ...@@ -542,8 +540,8 @@ struct drm_vmw_cursor_bypass_arg {
*/ */
struct drm_vmw_stream_arg { struct drm_vmw_stream_arg {
uint32_t stream_id; __u32 stream_id;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -565,7 +563,7 @@ struct drm_vmw_stream_arg { ...@@ -565,7 +563,7 @@ struct drm_vmw_stream_arg {
/** /**
* struct drm_vmw_get_3d_cap_arg * struct drm_vmw_get_3d_cap_arg
* *
* @buffer: Pointer to a buffer for capability data, cast to an uint64_t * @buffer: Pointer to a buffer for capability data, cast to an __u64
* @size: Max size to copy * @size: Max size to copy
* *
* Input argument to the DRM_VMW_GET_3D_CAP_IOCTL * Input argument to the DRM_VMW_GET_3D_CAP_IOCTL
...@@ -573,9 +571,9 @@ struct drm_vmw_stream_arg { ...@@ -573,9 +571,9 @@ struct drm_vmw_stream_arg {
*/ */
struct drm_vmw_get_3d_cap_arg { struct drm_vmw_get_3d_cap_arg {
uint64_t buffer; __u64 buffer;
uint32_t max_size; __u32 max_size;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -624,14 +622,14 @@ struct drm_vmw_get_3d_cap_arg { ...@@ -624,14 +622,14 @@ struct drm_vmw_get_3d_cap_arg {
*/ */
struct drm_vmw_fence_wait_arg { struct drm_vmw_fence_wait_arg {
uint32_t handle; __u32 handle;
int32_t cookie_valid; __s32 cookie_valid;
uint64_t kernel_cookie; __u64 kernel_cookie;
uint64_t timeout_us; __u64 timeout_us;
int32_t lazy; __s32 lazy;
int32_t flags; __s32 flags;
int32_t wait_options; __s32 wait_options;
int32_t pad64; __s32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -655,12 +653,12 @@ struct drm_vmw_fence_wait_arg { ...@@ -655,12 +653,12 @@ struct drm_vmw_fence_wait_arg {
*/ */
struct drm_vmw_fence_signaled_arg { struct drm_vmw_fence_signaled_arg {
uint32_t handle; __u32 handle;
uint32_t flags; __u32 flags;
int32_t signaled; __s32 signaled;
uint32_t passed_seqno; __u32 passed_seqno;
uint32_t signaled_flags; __u32 signaled_flags;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -681,8 +679,8 @@ struct drm_vmw_fence_signaled_arg { ...@@ -681,8 +679,8 @@ struct drm_vmw_fence_signaled_arg {
*/ */
struct drm_vmw_fence_arg { struct drm_vmw_fence_arg {
uint32_t handle; __u32 handle;
uint32_t pad64; __u32 pad64;
}; };
...@@ -703,9 +701,9 @@ struct drm_vmw_fence_arg { ...@@ -703,9 +701,9 @@ struct drm_vmw_fence_arg {
struct drm_vmw_event_fence { struct drm_vmw_event_fence {
struct drm_event base; struct drm_event base;
uint64_t user_data; __u64 user_data;
uint32_t tv_sec; __u32 tv_sec;
uint32_t tv_usec; __u32 tv_usec;
}; };
/* /*
...@@ -717,17 +715,17 @@ struct drm_vmw_event_fence { ...@@ -717,17 +715,17 @@ struct drm_vmw_event_fence {
/** /**
* struct drm_vmw_fence_event_arg * struct drm_vmw_fence_event_arg
* *
* @fence_rep: Pointer to fence_rep structure cast to uint64_t or 0 if * @fence_rep: Pointer to fence_rep structure cast to __u64 or 0 if
* the fence is not supposed to be referenced by user-space. * the fence is not supposed to be referenced by user-space.
* @user_info: Info to be delivered with the event. * @user_info: Info to be delivered with the event.
* @handle: Attach the event to this fence only. * @handle: Attach the event to this fence only.
* @flags: A set of flags as defined above. * @flags: A set of flags as defined above.
*/ */
struct drm_vmw_fence_event_arg { struct drm_vmw_fence_event_arg {
uint64_t fence_rep; __u64 fence_rep;
uint64_t user_data; __u64 user_data;
uint32_t handle; __u32 handle;
uint32_t flags; __u32 flags;
}; };
...@@ -747,7 +745,7 @@ struct drm_vmw_fence_event_arg { ...@@ -747,7 +745,7 @@ struct drm_vmw_fence_event_arg {
* @sid: Surface id to present from. * @sid: Surface id to present from.
* @dest_x: X placement coordinate for surface. * @dest_x: X placement coordinate for surface.
* @dest_y: Y placement coordinate for surface. * @dest_y: Y placement coordinate for surface.
* @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
* @num_clips: Number of cliprects given relative to the framebuffer origin, * @num_clips: Number of cliprects given relative to the framebuffer origin,
* in the same coordinate space as the frame buffer. * in the same coordinate space as the frame buffer.
* @pad64: Unused 64-bit padding. * @pad64: Unused 64-bit padding.
...@@ -756,13 +754,13 @@ struct drm_vmw_fence_event_arg { ...@@ -756,13 +754,13 @@ struct drm_vmw_fence_event_arg {
*/ */
struct drm_vmw_present_arg { struct drm_vmw_present_arg {
uint32_t fb_id; __u32 fb_id;
uint32_t sid; __u32 sid;
int32_t dest_x; __s32 dest_x;
int32_t dest_y; __s32 dest_y;
uint64_t clips_ptr; __u64 clips_ptr;
uint32_t num_clips; __u32 num_clips;
uint32_t pad64; __u32 pad64;
}; };
...@@ -780,16 +778,16 @@ struct drm_vmw_present_arg { ...@@ -780,16 +778,16 @@ struct drm_vmw_present_arg {
* struct drm_vmw_present_arg * struct drm_vmw_present_arg
* @fb_id: fb_id to present / read back from. * @fb_id: fb_id to present / read back from.
* @num_clips: Number of cliprects. * @num_clips: Number of cliprects.
* @clips_ptr: Pointer to an array of clip rects cast to an uint64_t. * @clips_ptr: Pointer to an array of clip rects cast to an __u64.
* @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an uint64_t. * @fence_rep: Pointer to a struct drm_vmw_fence_rep, cast to an __u64.
* If this member is NULL, then the ioctl should not return a fence. * If this member is NULL, then the ioctl should not return a fence.
*/ */
struct drm_vmw_present_readback_arg { struct drm_vmw_present_readback_arg {
uint32_t fb_id; __u32 fb_id;
uint32_t num_clips; __u32 num_clips;
uint64_t clips_ptr; __u64 clips_ptr;
uint64_t fence_rep; __u64 fence_rep;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -805,14 +803,14 @@ struct drm_vmw_present_readback_arg { ...@@ -805,14 +803,14 @@ struct drm_vmw_present_readback_arg {
* struct drm_vmw_update_layout_arg * struct drm_vmw_update_layout_arg
* *
* @num_outputs: number of active connectors * @num_outputs: number of active connectors
* @rects: pointer to array of drm_vmw_rect cast to an uint64_t * @rects: pointer to array of drm_vmw_rect cast to an __u64
* *
* Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl. * Input argument to the DRM_VMW_UPDATE_LAYOUT Ioctl.
*/ */
struct drm_vmw_update_layout_arg { struct drm_vmw_update_layout_arg {
uint32_t num_outputs; __u32 num_outputs;
uint32_t pad64; __u32 pad64;
uint64_t rects; __u64 rects;
}; };
...@@ -849,10 +847,10 @@ enum drm_vmw_shader_type { ...@@ -849,10 +847,10 @@ enum drm_vmw_shader_type {
*/ */
struct drm_vmw_shader_create_arg { struct drm_vmw_shader_create_arg {
enum drm_vmw_shader_type shader_type; enum drm_vmw_shader_type shader_type;
uint32_t size; __u32 size;
uint32_t buffer_handle; __u32 buffer_handle;
uint32_t shader_handle; __u32 shader_handle;
uint64_t offset; __u64 offset;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -871,8 +869,8 @@ struct drm_vmw_shader_create_arg { ...@@ -871,8 +869,8 @@ struct drm_vmw_shader_create_arg {
* Input argument to the DRM_VMW_UNREF_SHADER ioctl. * Input argument to the DRM_VMW_UNREF_SHADER ioctl.
*/ */
struct drm_vmw_shader_arg { struct drm_vmw_shader_arg {
uint32_t handle; __u32 handle;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
...@@ -918,14 +916,14 @@ enum drm_vmw_surface_flags { ...@@ -918,14 +916,14 @@ enum drm_vmw_surface_flags {
* Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl. * Part of output argument for the DRM_VMW_GB_SURFACE_REF Ioctl.
*/ */
struct drm_vmw_gb_surface_create_req { struct drm_vmw_gb_surface_create_req {
uint32_t svga3d_flags; __u32 svga3d_flags;
uint32_t format; __u32 format;
uint32_t mip_levels; __u32 mip_levels;
enum drm_vmw_surface_flags drm_surface_flags; enum drm_vmw_surface_flags drm_surface_flags;
uint32_t multisample_count; __u32 multisample_count;
uint32_t autogen_filter; __u32 autogen_filter;
uint32_t buffer_handle; __u32 buffer_handle;
uint32_t array_size; __u32 array_size;
struct drm_vmw_size base_size; struct drm_vmw_size base_size;
}; };
...@@ -944,11 +942,11 @@ struct drm_vmw_gb_surface_create_req { ...@@ -944,11 +942,11 @@ struct drm_vmw_gb_surface_create_req {
* Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl. * Output argument for the DRM_VMW_GB_SURFACE_CREATE ioctl.
*/ */
struct drm_vmw_gb_surface_create_rep { struct drm_vmw_gb_surface_create_rep {
uint32_t handle; __u32 handle;
uint32_t backup_size; __u32 backup_size;
uint32_t buffer_handle; __u32 buffer_handle;
uint32_t buffer_size; __u32 buffer_size;
uint64_t buffer_map_handle; __u64 buffer_map_handle;
}; };
/** /**
...@@ -1061,8 +1059,8 @@ enum drm_vmw_synccpu_op { ...@@ -1061,8 +1059,8 @@ enum drm_vmw_synccpu_op {
struct drm_vmw_synccpu_arg { struct drm_vmw_synccpu_arg {
enum drm_vmw_synccpu_op op; enum drm_vmw_synccpu_op op;
enum drm_vmw_synccpu_flags flags; enum drm_vmw_synccpu_flags flags;
uint32_t handle; __u32 handle;
uint32_t pad64; __u32 pad64;
}; };
/*************************************************************************/ /*************************************************************************/
......
include/uapi/linux/agpgart.h
View file @ 663a233e
...@@ -52,6 +52,7 @@ ...@@ -52,6 +52,7 @@
#ifndef __KERNEL__ #ifndef __KERNEL__
#include <linux/types.h> #include <linux/types.h>
#include <stdlib.h>
struct agp_version { struct agp_version {
__u16 major; __u16 major;
......
include/uapi/linux/virtio_gpu.h
View file @ 663a233e
...@@ -287,7 +287,7 @@ struct virtio_gpu_get_capset { ...@@ -287,7 +287,7 @@ struct virtio_gpu_get_capset {
/* VIRTIO_GPU_RESP_OK_CAPSET */ /* VIRTIO_GPU_RESP_OK_CAPSET */
struct virtio_gpu_resp_capset { struct virtio_gpu_resp_capset {
struct virtio_gpu_ctrl_hdr hdr; struct virtio_gpu_ctrl_hdr hdr;
uint8_t capset_data[]; __u8 capset_data[];
}; };
#define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
......
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