Commit 66d627d5 authored by Bard Liao's avatar Bard Liao Committed by Mark Brown

ASoC: rt286: Fix sync function

We try to write index registers into cache when we write an index
register, but we change the reg value before updating the cache.
As a result, the cache is never be updated. This patch will fix
this issue.
Signed-off-by: default avatarBard Liao <bardliao@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
parent b7a29767
...@@ -191,7 +191,6 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) ...@@ -191,7 +191,6 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
/*handle index registers*/ /*handle index registers*/
if (reg <= 0xff) { if (reg <= 0xff) {
rt286_hw_write(client, RT286_COEF_INDEX, reg); rt286_hw_write(client, RT286_COEF_INDEX, reg);
reg = RT286_PROC_COEF;
for (i = 0; i < INDEX_CACHE_SIZE; i++) { for (i = 0; i < INDEX_CACHE_SIZE; i++) {
if (reg == rt286->index_cache[i].reg) { if (reg == rt286->index_cache[i].reg) {
rt286->index_cache[i].def = value; rt286->index_cache[i].def = value;
...@@ -199,6 +198,7 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value) ...@@ -199,6 +198,7 @@ static int rt286_hw_write(void *context, unsigned int reg, unsigned int value)
} }
} }
reg = RT286_PROC_COEF;
} }
data[0] = (reg >> 24) & 0xff; data[0] = (reg >> 24) & 0xff;
......
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