Commit 67b35b08 authored by Chengming Gui's avatar Chengming Gui Committed by Alex Deucher

drm/amd/amdgpu: configure beige_goby gfx according to gfx 10.3's definition

The gfx version of beige_goby is 10.3,
identical to sienna_cichlid,
follow the way of sienna_cichlid
Signed-off-by: default avatarChengming Gui <Jack.Gui@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8760403e
...@@ -6135,6 +6135,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, ...@@ -6135,6 +6135,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
...@@ -6270,6 +6271,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) ...@@ -6270,6 +6271,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
break; break;
default: default:
...@@ -6282,6 +6284,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) ...@@ -6282,6 +6284,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
(CP_MEC_CNTL__MEC_ME1_HALT_MASK | (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
CP_MEC_CNTL__MEC_ME2_HALT_MASK)); CP_MEC_CNTL__MEC_ME2_HALT_MASK));
...@@ -6378,6 +6381,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) ...@@ -6378,6 +6381,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
tmp &= 0xffffff00; tmp &= 0xffffff00;
tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
...@@ -7092,6 +7096,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) ...@@ -7092,6 +7096,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
case CHIP_SIENNA_CICHLID: case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
...@@ -7138,6 +7143,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) ...@@ -7138,6 +7143,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
GRBM_CAM_DATA__CAM_ADDR__SHIFT) | GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
...@@ -7447,6 +7453,7 @@ static int gfx_v10_0_soft_reset(void *handle) ...@@ -7447,6 +7453,7 @@ static int gfx_v10_0_soft_reset(void *handle)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
GRBM_SOFT_RESET, GRBM_SOFT_RESET,
...@@ -7613,6 +7620,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) ...@@ -7613,6 +7620,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
/* wait for RLC_SAFE_MODE */ /* wait for RLC_SAFE_MODE */
...@@ -7647,6 +7655,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) ...@@ -7647,6 +7655,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
case CHIP_NAVY_FLOUNDER: case CHIP_NAVY_FLOUNDER:
case CHIP_VANGOGH: case CHIP_VANGOGH:
case CHIP_DIMGREY_CAVEFISH: case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
break; break;
default: default:
......
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