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Commit 68df1dba authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'amlogic-dt64' of... 

Merge tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

Amlogic ARM64 DT updates for v4.20
- AXG: cleanup/reorder nodes
- AXG: add audio PDM support for s400 board
- GX: increase CMA memory size
- GX: new canvas driver

* tag 'amlogic-dt64' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  arm64: dts: meson: Switch simple-mfd and syscon order
  arm64: dts: meson-axg-s400: Add chosen and memory nodes
  arm64: dts: meson-axg: use the proper compatible for ethmac
  arm64: dts: meson-axg: s400: add pdm to the sound card
  arm64: dts: meson-axg: s400: add dmic codec
  arm64: dts: meson-axg: add pdm
  arm64: dts: meson-gx: add dmcbus and canvas nodes.
  arm64: dts: meson: libretech: update board model
  arm64: dts: meson-gx: increase default shared CMA pool size
  arm64: dts: meson-axg: sort nodes consistently
  arm64: dts: meson-axg: s400: add sound card
  arm64: dts: meson-axg: s400: enable audio devices
  arm64: dts: meson-axg: add audio fifos
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 923769f7 445f2bda
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arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
View file @ 68df1dba
......@@ -60,6 +60,55 @@ aliases {
serial1 = &uart_A;
};
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
status = "okay";
sound-name-prefix = "Linein";
};
lineout: audio-codec@1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
status = "okay";
sound-name-prefix = "Lineout";
};
spdif_dit: audio-codec@2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
};
dmics: audio-codec@3 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <7>;
wakeup-delay-ms = <50>;
status = "okay";
sound-name-prefix = "MIC";
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x40000000>;
};
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
......@@ -68,15 +117,26 @@ main_12v: regulator-main_12v {
regulator-always-on;
};
vddio_boot: regulator-vddio_boot {
vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v>;
gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
......@@ -95,26 +155,15 @@ vddio_ao18: regulator-vddio_ao18 {
regulator-always-on;
};
vcc_3v3: regulator-vcc_3v3 {
vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VDDIO_BOOT";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
vcc_5v: regulator-vcc_5v {
compatible = "regulator-fixed";
regulator-name = "VCC5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&main_12v>;
gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb_pwr: regulator-usb_pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
......@@ -126,11 +175,6 @@ usb_pwr: regulator-usb_pwr {
enable-active-high;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
......@@ -138,13 +182,6 @@ sdio_pwrseq: sdio-pwrseq {
clock-names = "ext_clock";
};
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
speaker-leds {
compatible = "gpio-leds";
......@@ -179,30 +216,129 @@ aled6 {
};
};
linein: audio-codec@0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
VDDP-supply = <&vcc_3v3>;
VDDD-supply = <&vcc_3v3>;
sound {
compatible = "amlogic,axg-sound-card";
model = "AXG-S400";
audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
<&tdmin_lb>, <&tdmout_c>;
audio-widgets = "Line", "Lineout",
"Line", "Linein",
"Speaker", "Speaker1 Left",
"Speaker", "Speaker1 Right";
audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
"SPDIFOUT IN 0", "FRDDR_A OUT 3",
"TDMOUT_C IN 1", "FRDDR_B OUT 2",
"SPDIFOUT IN 1", "FRDDR_B OUT 3",
"TDMOUT_C IN 2", "FRDDR_C OUT 2",
"SPDIFOUT IN 2", "FRDDR_C OUT 3",
"TDM_C Playback", "TDMOUT_C OUT",
"TDMIN_A IN 2", "TDM_C Capture",
"TDMIN_A IN 5", "TDM_C Loopback",
"TDMIN_B IN 2", "TDM_C Capture",
"TDMIN_B IN 5", "TDM_C Loopback",
"TDMIN_C IN 2", "TDM_C Capture",
"TDMIN_C IN 5", "TDM_C Loopback",
"TDMIN_LB IN 2", "TDM_C Loopback",
"TDMIN_LB IN 5", "TDM_C Capture",
"TODDR_A IN 0", "TDMIN_A OUT",
"TODDR_B IN 0", "TDMIN_A OUT",
"TODDR_C IN 0", "TDMIN_A OUT",
"TODDR_A IN 1", "TDMIN_B OUT",
"TODDR_B IN 1", "TDMIN_B OUT",
"TODDR_C IN 1", "TDMIN_B OUT",
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
"TODDR_A IN 4", "PDM Capture",
"TODDR_B IN 4", "PDM Capture",
"TODDR_C IN 4", "PDM Capture",
"TODDR_A IN 6", "TDMIN_LB OUT",
"TODDR_B IN 6", "TDMIN_LB OUT",
"TODDR_C IN 6", "TDMIN_LB OUT",
"Lineout", "Lineout AOUTL",
"Lineout", "Lineout AOUTR",
"Speaker1 Left", "SPK1 OUT_A",
"Speaker1 Left", "SPK1 OUT_B",
"Speaker1 Right", "SPK1 OUT_C",
"Speaker1 Right", "SPK1 OUT_D",
"Linein AINL", "Linein",
"Linein AINR", "Linein";
assigned-clocks = <&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>;
assigned-clock-parents = <0>, <0>, <0>;
assigned-clock-rates = <589824000>,
<270950400>,
<393216000>;
status = "okay";
sound-name-prefix = "Linein";
};
lineout: audio-codec@1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
PVDD-supply = <&vcc_5v>;
status = "okay";
sound-name-prefix = "Lineout";
dai-link@0 {
sound-dai = <&frddr_a>;
};
dai-link@1 {
sound-dai = <&frddr_b>;
};
dai-link@2 {
sound-dai = <&frddr_c>;
};
dai-link@3 {
sound-dai = <&toddr_a>;
};
dai-link@4 {
sound-dai = <&toddr_b>;
};
dai-link@5 {
sound-dai = <&toddr_c>;
};
dai-link@6 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-2 = <1 1>;
dai-tdm-slot-rx-mask-1 = <1 1>;
mclk-fs = <256>;
codec@0 {
sound-dai = <&lineout>;
};
codec@1 {
sound-dai = <&speaker_amp1>;
};
codec@2 {
sound-dai = <&linein>;
};
};
dai-link@7 {
sound-dai = <&spdifout>;
codec {
sound-dai = <&spdif_dit>;
};
};
dai-link@8 {
sound-dai = <&pdm>;
codec {
sound-dai = <&dmics>;
};
};
};
spdif_dit: audio-codec@2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
wifi32k: wifi32k {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
};
};
......@@ -226,16 +362,16 @@ eth_phy0: ethernet-phy@0 {
};
};
&uart_A {
&frddr_a {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
&uart_AO {
&frddr_b {
status = "okay";
};
&frddr_c {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
&ir {
......@@ -260,6 +396,7 @@ speaker_amp1: audio-codec@1b {
PVDD_B-supply = <&main_12v>;
PVDD_C-supply = <&main_12v>;
PVDD_D-supply = <&main_12v>;
sound-name-prefix = "SPK1";
};
};
......@@ -277,30 +414,22 @@ gpio_speaker: gpio-controller@1f {
};
};
&pdm {
pinctrl-0 = <&pdm_dclk_a14_pins>, <&pdm_din0_pins>,
<&pdm_din1_pins>, <&pdm_din2_pins>, <&pdm_din3_pins>;
pinctrl-names = "default";
status = "okay";
};
&pwm_ab {
status = "okay";
pinctrl-0 = <&pwm_a_x20_pins>;
pinctrl-names = "default";
};
/* emmc storage */
&sd_emmc_c {
&saradc {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <180000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
vref-supply = <&vddio_ao18>;
};
/* wifi module */
......@@ -330,7 +459,94 @@ brcmf: wifi@1 {
};
};
&saradc {
/* emmc storage */
&sd_emmc_c {
status = "okay";
vref-supply = <&vddio_ao18>;
pinctrl-0 = <&emmc_pins>;
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <180000000>;
non-removable;
disable-wp;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
&spdifout {
pinctrl-0 = <&spdif_out_a20_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_a {
pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
<&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_b {
pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
<&tdmb_din3_pins>, <&mclk_b_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmif_c {
pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
<&tdmc_din1_pins>, <&tdmc_dout2_pins>,
<&mclk_c_pins>;
pinctrl-names = "default";
status = "okay";
};
&tdmin_a {
status = "okay";
};
&tdmin_b {
status = "okay";
};
&tdmin_c {
status = "okay";
};
&tdmin_lb {
status = "okay";
};
&tdmout_c {
status = "okay";
};
&toddr_a {
status = "okay";
};
&toddr_b {
status = "okay";
};
&toddr_c {
status = "okay";
};
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
pinctrl-names = "default";
};
&uart_AO {
status = "okay";
pinctrl-0 = <&uart_ao_a_pins>;
pinctrl-names = "default";
};
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View file @ 68df1dba
......@@ -3,13 +3,14 @@
* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/clock/axg-audio-clkc.h>
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/clock/axg-aoclkc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/meson-axg-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
/ {
......@@ -19,22 +20,53 @@ / {
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tdmif_a: audio-controller@0 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_A";
clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
<&clkc_audio AUD_CLKID_MST_A_SCLK>,
<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
/* 16 MiB reserved for Hardware ROM Firmware */
hwrom_reserved: hwrom@0 {
reg = <0x0 0x0 0x0 0x1000000>;
no-map;
};
tdmif_b: audio-controller@1 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_B";
clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
<&clkc_audio AUD_CLKID_MST_B_SCLK>,
<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
tdmif_c: audio-controller@2 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_C";
clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
<&clkc_audio AUD_CLKID_MST_C_SCLK>,
<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
ao_alt_xtal: ao_alt_xtal-clk {
compatible = "fixed-clock";
clock-frequency = <32000000>;
clock-output-names = "ao_alt_xtal";
#clock-cells = <0>;
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
cpus {
......@@ -78,77 +110,27 @@ l2: l2-cache0 {
};
};
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
tdmif_a: audio-controller@0 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_A";
clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
<&clkc_audio AUD_CLKID_MST_A_SCLK>,
<&clkc_audio AUD_CLKID_MST_A_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
tdmif_b: audio-controller@1 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_B";
clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
<&clkc_audio AUD_CLKID_MST_B_SCLK>,
<&clkc_audio AUD_CLKID_MST_B_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
tdmif_c: audio-controller@2 {
compatible = "amlogic,axg-tdm-iface";
#sound-dai-cells = <0>;
sound-name-prefix = "TDM_C";
clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
<&clkc_audio AUD_CLKID_MST_C_SCLK>,
<&clkc_audio AUD_CLKID_MST_C_LRCLK>;
clock-names = "mclk", "sclk", "lrclk";
status = "disabled";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
/* 16 MiB reserved for Hardware ROM Firmware */
hwrom_reserved: hwrom@0 {
reg = <0x0 0x0 0x0 0x1000000>;
no-map;
};
ao_alt_xtal: ao_alt_xtal-clk {
compatible = "fixed-clock";
clock-frequency = <32000000>;
clock-output-names = "ao_alt_xtal";
#clock-cells = <0>;
/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
secmon_reserved: secmon@5000000 {
reg = <0x0 0x05000000 0x0 0x300000>;
no-map;
};
};
soc {
......@@ -157,403 +139,139 @@ soc {
#size-cells = <2>;
ranges;
apb: apb@ffe00000 {
compatible = "simple-bus";
reg = <0x0 0xffe00000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
sd_emmc_b: sd@5000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x5000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000
0x0 0xff634540 0x0 0x8>;
interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
status = "disabled";
};
sd_emmc_c: mmc@7000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
pdm: audio-controller@ff632000 {
compatible = "amlogic,axg-pdm";
reg = <0x0 0xff632000 0x0 0x34>;
#sound-dai-cells = <0>;
sound-name-prefix = "PDM";
clocks = <&clkc_audio AUD_CLKID_PDM>,
<&clkc_audio AUD_CLKID_PDM_DCLK>,
<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
clock-names = "pclk", "dclk", "sysclk";
status = "disabled";
};
audio: bus@ff642000 {
periphs: bus@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
resets = <&reset RESET_AUDIO>;
hwrng: rng@18 {
compatible = "amlogic,meson-rng";
reg = <0x0 0x18 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
tdmin_a: audio-controller@300 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x300 0x0 0x40>;
sound-name-prefix = "TDMIN_A";
clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
gpio: bank@480 {
reg = <0x0 0x00480 0x0 0x40>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x3c>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
tdmin_b: audio-controller@340 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x340 0x0 0x40>;
sound-name-prefix = "TDMIN_B";
clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_c: audio-controller@380 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x380 0x0 0x40>;
sound-name-prefix = "TDMIN_C";
clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_lb: audio-controller@3c0 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x3c0 0x0 0x40>;
sound-name-prefix = "TDMIN_LB";
clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
spdifout: audio-controller@480 {
compatible = "amlogic,axg-spdifout";
reg = <0x0 0x480 0x0 0x50>;
#sound-dai-cells = <0>;
sound-name-prefix = "SPDIFOUT";
clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
clock-names = "pclk", "mclk";
status = "disabled";
};
tdmout_a: audio-controller@500 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x500 0x0 0x40>;
sound-name-prefix = "TDMOUT_A";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmout_b: audio-controller@540 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x540 0x0 0x40>;
sound-name-prefix = "TDMOUT_B";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmout_c: audio-controller@580 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x580 0x0 0x40>;
sound-name-prefix = "TDMOUT_C";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
gpio_intc: interrupt-controller@f080 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x0 0xf080 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
pwm_ab: pwm@1b000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1b000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@1a000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1a000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
reset: reset-controller@1004 {
compatible = "amlogic,meson-axg-reset";
reg = <0x0 0x01004 0x0 0x9c>;
#reset-cells = <1>;
};
spicc0: spi@13000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x13000 0x0 0x3c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@15000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x15000 0x0 0x3c>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@1f000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1f000 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@1e000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1e000 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@1d000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1d000 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@1c000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1c000 0x0 0x20>;
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
};
ethmac: ethernet@ff3f0000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xff3f0000 0x0 0x10000
0x0 0xff634540 0x0 0x8>;
interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
status = "disabled";
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
i2c0_pins: i2c0 {
mux {
groups = "i2c0_sck",
"i2c0_sda";
function = "i2c0";
};
};
sysctrl: system-controller@0 {
compatible = "amlogic,meson-axg-hhi-sysctrl", "syscon", "simple-mfd";
reg = <0 0 0 0x400>;
i2c1_x_pins: i2c1_x {
mux {
groups = "i2c1_sck_x",
"i2c1_sda_x";
function = "i2c1";
};
};
clkc: clock-controller {
compatible = "amlogic,axg-clkc";
#clock-cells = <1>;
i2c1_z_pins: i2c1_z {
mux {
groups = "i2c1_sck_z",
"i2c1_sda_z";
function = "i2c1";
};
};
};
};
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
i2c2_a_pins: i2c2_a {
mux {
groups = "i2c2_sck_a",
"i2c2_sda_a";
function = "i2c2";
};
};
periphs: periphs@ff634000 {
compatible = "simple-bus";
reg = <0x0 0xff634000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
i2c2_x_pins: i2c2_x {
mux {
groups = "i2c2_sck_x",
"i2c2_sda_x";
function = "i2c2";
};
};
hwrng: rng {
compatible = "amlogic,meson-rng";
reg = <0x0 0x18 0x0 0x4>;
clocks = <&clkc CLKID_RNG0>;
clock-names = "core";
};
i2c3_a6_pins: i2c3_a6 {
mux {
groups = "i2c3_sda_a6",
"i2c3_sck_a7";
function = "i2c3";
};
};
pinctrl_periphs: pinctrl@480 {
compatible = "amlogic,meson-axg-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
i2c3_a12_pins: i2c3_a12 {
mux {
groups = "i2c3_sda_a12",
"i2c3_sck_a13";
function = "i2c3";
};
};
gpio: bank@480 {
reg = <0x0 0x00480 0x0 0x40>,
<0x0 0x004e8 0x0 0x14>,
<0x0 0x00520 0x0 0x14>,
<0x0 0x00430 0x0 0x3c>;
reg-names = "mux", "pull", "pull-enable", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
i2c3_a19_pins: i2c3_a19 {
mux {
groups = "i2c3_sda_a19",
"i2c3_sck_a20";
function = "i2c3";
};
};
emmc_pins: emmc {
mux {
groups = "emmc_nand_d0",
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_clk",
"emmc_cmd",
"emmc_ds";
"emmc_nand_d1",
"emmc_nand_d2",
"emmc_nand_d3",
"emmc_nand_d4",
"emmc_nand_d5",
"emmc_nand_d6",
"emmc_nand_d7",
"emmc_clk",
"emmc_cmd",
"emmc_ds";
function = "emmc";
};
};
......@@ -569,40 +287,57 @@ cfg-pull-down {
};
};
sdio_pins: sdio {
eth_rgmii_x_pins: eth-x-rgmii {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
groups = "eth_mdio_x",
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
};
};
sdio_clk_gate_pins: sdio_clk_gate {
eth_rgmii_y_pins: eth-y-rgmii {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
groups = "eth_mdio_y",
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
};
};
eth_rmii_x_pins: eth-x-rmii {
mux {
groups = "eth_mdio_x",
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x";
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x";
function = "eth";
};
};
......@@ -610,55 +345,29 @@ mux {
eth_rmii_y_pins: eth-y-rmii {
mux {
groups = "eth_mdio_y",
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y";
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y";
function = "eth";
};
};
eth_rgmii_x_pins: eth-x-rgmii {
mclk_b_pins: mclk_b {
mux {
groups = "eth_mdio_x",
"eth_mdc_x",
"eth_rgmii_rx_clk_x",
"eth_rx_dv_x",
"eth_rxd0_x",
"eth_rxd1_x",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_x",
"eth_txd0_x",
"eth_txd1_x",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
groups = "mclk_b";
function = "mclk_b";
};
};
eth_rgmii_y_pins: eth-y-rgmii {
mclk_c_pins: mclk_c {
mux {
groups = "eth_mdio_y",
"eth_mdc_y",
"eth_rgmii_rx_clk_y",
"eth_rx_dv_y",
"eth_rxd0_y",
"eth_rxd1_y",
"eth_rxd2_rgmii",
"eth_rxd3_rgmii",
"eth_rgmii_tx_clk",
"eth_txen_y",
"eth_txd0_y",
"eth_txd1_y",
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
groups = "mclk_c";
function = "mclk_c";
};
};
......@@ -788,6 +497,29 @@ mux {
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
"sdio_d1",
"sdio_d2",
"sdio_d3",
"sdio_cmd",
"sdio_clk";
function = "sdio";
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
};
};
spdif_in_z_pins: spdif_in_z {
mux {
groups = "spdif_in_z";
......@@ -823,13 +555,6 @@ mux {
};
};
spdif_out_z_pins: spdif_out_z {
mux {
groups = "spdif_out_z";
function = "spdif_out";
};
};
spdif_out_a1_pins: spdif_out_a1 {
mux {
groups = "spdif_out_a1";
......@@ -858,11 +583,18 @@ mux {
};
};
spdif_out_z_pins: spdif_out_z {
mux {
groups = "spdif_out_z";
function = "spdif_out";
};
};
spi0_pins: spi0 {
mux {
groups = "spi0_miso",
"spi0_mosi",
"spi0_clk";
"spi0_mosi",
"spi0_clk";
function = "spi0";
};
};
......@@ -888,12 +620,11 @@ mux {
};
};
spi1_a_pins: spi1_a {
mux {
groups = "spi1_miso_a",
"spi1_mosi_a",
"spi1_clk_a";
"spi1_mosi_a",
"spi1_clk_a";
function = "spi1";
};
};
......@@ -915,8 +646,8 @@ mux {
spi1_x_pins: spi1_x {
mux {
groups = "spi1_miso_x",
"spi1_mosi_x",
"spi1_clk_x";
"spi1_mosi_x",
"spi1_clk_x";
function = "spi1";
};
};
......@@ -928,145 +659,52 @@ mux {
};
};
i2c0_pins: i2c0 {
mux {
groups = "i2c0_sck",
"i2c0_sda";
function = "i2c0";
};
};
i2c1_z_pins: i2c1_z {
mux {
groups = "i2c1_sck_z",
"i2c1_sda_z";
function = "i2c1";
};
};
i2c1_x_pins: i2c1_x {
mux {
groups = "i2c1_sck_x",
"i2c1_sda_x";
function = "i2c1";
};
};
i2c2_x_pins: i2c2_x {
mux {
groups = "i2c2_sck_x",
"i2c2_sda_x";
function = "i2c2";
};
};
i2c2_a_pins: i2c2_a {
mux {
groups = "i2c2_sck_a",
"i2c2_sda_a";
function = "i2c2";
};
};
i2c3_a6_pins: i2c3_a6 {
mux {
groups = "i2c3_sda_a6",
"i2c3_sck_a7";
function = "i2c3";
};
};
i2c3_a12_pins: i2c3_a12 {
mux {
groups = "i2c3_sda_a12",
"i2c3_sck_a13";
function = "i2c3";
};
};
i2c3_a19_pins: i2c3_a19 {
mux {
groups = "i2c3_sda_a19",
"i2c3_sck_a20";
function = "i2c3";
};
};
uart_a_pins: uart_a {
mux {
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
uart_a_cts_rts_pins: uart_a_cts_rts {
mux {
groups = "uart_cts_a",
"uart_rts_a";
function = "uart_a";
};
};
uart_b_x_pins: uart_b_x {
mux {
groups = "uart_tx_b_x",
"uart_rx_b_x";
function = "uart_b";
};
};
uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
tdma_din0_pins: tdma_din0 {
mux {
groups = "uart_cts_b_x",
"uart_rts_b_x";
function = "uart_b";
groups = "tdma_din0";
function = "tdma";
};
};
uart_b_z_pins: uart_b_z {
tdma_dout0_x14_pins: tdma_dout0_x14 {
mux {
groups = "uart_tx_b_z",
"uart_rx_b_z";
function = "uart_b";
groups = "tdma_dout0_x14";
function = "tdma";
};
};
uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
tdma_dout0_x15_pins: tdma_dout0_x15 {
mux {
groups = "uart_cts_b_z",
"uart_rts_b_z";
function = "uart_b";
groups = "tdma_dout0_x15";
function = "tdma";
};
};
uart_ao_b_z_pins: uart_ao_b_z {
tdma_dout1_pins: tdma_dout1 {
mux {
groups = "uart_ao_tx_b_z",
"uart_ao_rx_b_z";
function = "uart_ao_b_z";
groups = "tdma_dout1";
function = "tdma";
};
};
uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
tdma_din1_pins: tdma_din1 {
mux {
groups = "uart_ao_cts_b_z",
"uart_ao_rts_b_z";
function = "uart_ao_b_z";
groups = "tdma_din1";
function = "tdma";
};
};
mclk_b_pins: mclk_b {
tdma_fs_pins: tdma_fs {
mux {
groups = "mclk_b";
function = "mclk_b";
groups = "tdma_fs";
function = "tdma";
};
};
mclk_c_pins: mclk_c {
tdma_fs_slv_pins: tdma_fs_slv {
mux {
groups = "mclk_c";
function = "mclk_c";
groups = "tdma_fs_slv";
function = "tdma";
};
};
......@@ -1084,65 +722,58 @@ mux {
};
};
tdma_fs_pins: tdma_fs {
mux {
groups = "tdma_fs";
function = "tdma";
};
};
tdma_fs_slv_pins: tdma_fs_slv {
tdmb_din0_pins: tdmb_din0 {
mux {
groups = "tdma_fs_slv";
function = "tdma";
groups = "tdmb_din0";
function = "tdmb";
};
};
tdma_din0_pins: tdma_din0 {
tdmb_din1_pins: tdmb_din1 {
mux {
groups = "tdma_din0";
function = "tdma";
groups = "tdmb_din1";
function = "tdmb";
};
};
tdma_dout0_x14_pins: tdma_dout0_x14 {
tdmb_din2_pins: tdmb_din2 {
mux {
groups = "tdma_dout0_x14";
function = "tdma";
groups = "tdmb_din2";
function = "tdmb";
};
};
tdma_dout0_x15_pins: tdma_dout0_x15 {
tdmb_din3_pins: tdmb_din3 {
mux {
groups = "tdma_dout0_x15";
function = "tdma";
groups = "tdmb_din3";
function = "tdmb";
};
};
tdma_dout1_pins: tdma_dout1 {
tdmb_dout0_pins: tdmb_dout0 {
mux {
groups = "tdma_dout1";
function = "tdma";
groups = "tdmb_dout0";
function = "tdmb";
};
};
tdma_din1_pins: tdma_din1 {
tdmb_dout1_pins: tdmb_dout1 {
mux {
groups = "tdma_din1";
function = "tdma";
groups = "tdmb_dout1";
function = "tdmb";
};
};
tdmb_sclk_pins: tdmb_sclk {
tdmb_dout2_pins: tdmb_dout2 {
mux {
groups = "tdmb_sclk";
groups = "tdmb_dout2";
function = "tdmb";
};
};
tdmb_sclk_slv_pins: tdmb_sclk_slv {
tdmb_dout3_pins: tdmb_dout3 {
mux {
groups = "tdmb_sclk_slv";
groups = "tdmb_dout3";
function = "tdmb";
};
};
......@@ -1161,163 +792,412 @@ mux {
};
};
tdmb_din0_pins: tdmb_din0 {
tdmb_sclk_pins: tdmb_sclk {
mux {
groups = "tdmb_din0";
groups = "tdmb_sclk";
function = "tdmb";
};
};
tdmb_dout0_pins: tdmb_dout0 {
tdmb_sclk_slv_pins: tdmb_sclk_slv {
mux {
groups = "tdmb_dout0";
groups = "tdmb_sclk_slv";
function = "tdmb";
};
};
tdmb_din1_pins: tdmb_din1 {
tdmc_fs_pins: tdmc_fs {
mux {
groups = "tdmb_din1";
function = "tdmb";
groups = "tdmc_fs";
function = "tdmc";
};
};
tdmb_dout1_pins: tdmb_dout1 {
tdmc_fs_slv_pins: tdmc_fs_slv {
mux {
groups = "tdmb_dout1";
function = "tdmb";
groups = "tdmc_fs_slv";
function = "tdmc";
};
};
tdmb_din2_pins: tdmb_din2 {
tdmc_sclk_pins: tdmc_sclk {
mux {
groups = "tdmb_din2";
function = "tdmb";
groups = "tdmc_sclk";
function = "tdmc";
};
};
tdmb_dout2_pins: tdmb_dout2 {
tdmc_sclk_slv_pins: tdmc_sclk_slv {
mux {
groups = "tdmb_dout2";
function = "tdmb";
groups = "tdmc_sclk_slv";
function = "tdmc";
};
};
tdmb_din3_pins: tdmb_din3 {
tdmc_din0_pins: tdmc_din0 {
mux {
groups = "tdmb_din3";
function = "tdmb";
groups = "tdmc_din0";
function = "tdmc";
};
};
tdmc_din1_pins: tdmc_din1 {
mux {
groups = "tdmc_din1";
function = "tdmc";
};
};
tdmc_din2_pins: tdmc_din2 {
mux {
groups = "tdmc_din2";
function = "tdmc";
};
};
tdmb_dout3_pins: tdmb_dout3 {
tdmc_din3_pins: tdmc_din3 {
mux {
groups = "tdmb_dout3";
function = "tdmb";
groups = "tdmc_din3";
function = "tdmc";
};
};
tdmc_sclk_pins: tdmc_sclk {
tdmc_dout0_pins: tdmc_dout0 {
mux {
groups = "tdmc_sclk";
groups = "tdmc_dout0";
function = "tdmc";
};
};
tdmc_sclk_slv_pins: tdmc_sclk_slv {
tdmc_dout1_pins: tdmc_dout1 {
mux {
groups = "tdmc_sclk_slv";
groups = "tdmc_dout1";
function = "tdmc";
};
};
tdmc_fs_pins: tdmc_fs {
tdmc_dout2_pins: tdmc_dout2 {
mux {
groups = "tdmc_fs";
groups = "tdmc_dout2";
function = "tdmc";
};
};
tdmc_fs_slv_pins: tdmc_fs_slv {
tdmc_dout3_pins: tdmc_dout3 {
mux {
groups = "tdmc_fs_slv";
groups = "tdmc_dout3";
function = "tdmc";
};
};
tdmc_din0_pins: tdmc_din0 {
uart_a_pins: uart_a {
mux {
groups = "tdmc_din0";
function = "tdmc";
groups = "uart_tx_a",
"uart_rx_a";
function = "uart_a";
};
};
tdmc_dout0_pins: tdmc_dout0 {
uart_a_cts_rts_pins: uart_a_cts_rts {
mux {
groups = "tdmc_dout0";
function = "tdmc";
groups = "uart_cts_a",
"uart_rts_a";
function = "uart_a";
};
};
tdmc_din1_pins: tdmc_din1 {
uart_b_x_pins: uart_b_x {
mux {
groups = "tdmc_din1";
function = "tdmc";
groups = "uart_tx_b_x",
"uart_rx_b_x";
function = "uart_b";
};
};
tdmc_dout1_pins: tdmc_dout1 {
uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
mux {
groups = "tdmc_dout1";
function = "tdmc";
groups = "uart_cts_b_x",
"uart_rts_b_x";
function = "uart_b";
};
};
tdmc_din2_pins: tdmc_din2 {
uart_b_z_pins: uart_b_z {
mux {
groups = "tdmc_din2";
function = "tdmc";
groups = "uart_tx_b_z",
"uart_rx_b_z";
function = "uart_b";
};
};
tdmc_dout2_pins: tdmc_dout2 {
uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
mux {
groups = "tdmc_dout2";
function = "tdmc";
groups = "uart_cts_b_z",
"uart_rts_b_z";
function = "uart_b";
};
};
tdmc_din3_pins: tdmc_din3 {
uart_ao_b_z_pins: uart_ao_b_z {
mux {
groups = "tdmc_din3";
function = "tdmc";
groups = "uart_ao_tx_b_z",
"uart_ao_rx_b_z";
function = "uart_ao_b_z";
};
};
tdmc_dout3_pins: tdmc_dout3 {
uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
mux {
groups = "tdmc_dout3";
function = "tdmc";
groups = "uart_ao_cts_b_z",
"uart_ao_rts_b_z";
function = "uart_ao_b_z";
};
};
};
};
sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xfffc0000 0x20000>;
hiubus: bus@ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13000 0x400>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-axg-hhi-sysctrl",
"simple-mfd", "syscon";
reg = <0 0 0 0x400>;
clkc: clock-controller {
compatible = "amlogic,axg-clkc";
#clock-cells = <1>;
};
};
};
mailbox: mailbox@ff63dc00 {
compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
reg = <0 0xff63dc00 0 0x400>;
interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
#mbox-cells = <1>;
};
audio: bus@ff642000 {
compatible = "simple-bus";
reg = <0x0 0xff642000 0x0 0x2000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};
toddr_a: audio-controller@100 {
compatible = "amlogic,axg-toddr";
reg = <0x0 0x100 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "TODDR_A";
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
resets = <&arb AXG_ARB_TODDR_A>;
status = "disabled";
};
toddr_b: audio-controller@140 {
compatible = "amlogic,axg-toddr";
reg = <0x0 0x140 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "TODDR_B";
interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
resets = <&arb AXG_ARB_TODDR_B>;
status = "disabled";
};
toddr_c: audio-controller@180 {
compatible = "amlogic,axg-toddr";
reg = <0x0 0x180 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "TODDR_C";
interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
resets = <&arb AXG_ARB_TODDR_C>;
status = "disabled";
};
frddr_a: audio-controller@1c0 {
compatible = "amlogic,axg-frddr";
reg = <0x0 0x1c0 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "FRDDR_A";
interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
resets = <&arb AXG_ARB_FRDDR_A>;
status = "disabled";
};
frddr_b: audio-controller@200 {
compatible = "amlogic,axg-frddr";
reg = <0x0 0x200 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "FRDDR_B";
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
resets = <&arb AXG_ARB_FRDDR_B>;
status = "disabled";
};
frddr_c: audio-controller@240 {
compatible = "amlogic,axg-frddr";
reg = <0x0 0x240 0x0 0x1c>;
#sound-dai-cells = <0>;
sound-name-prefix = "FRDDR_C";
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
resets = <&arb AXG_ARB_FRDDR_C>;
status = "disabled";
};
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};
tdmin_a: audio-controller@300 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x300 0x0 0x40>;
sound-name-prefix = "TDMIN_A";
clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_b: audio-controller@340 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x340 0x0 0x40>;
sound-name-prefix = "TDMIN_B";
clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_c: audio-controller@380 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x380 0x0 0x40>;
sound-name-prefix = "TDMIN_C";
clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmin_lb: audio-controller@3c0 {
compatible = "amlogic,axg-tdmin";
reg = <0x0 0x3c0 0x0 0x40>;
sound-name-prefix = "TDMIN_LB";
clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
<&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
spdifout: audio-controller@480 {
compatible = "amlogic,axg-spdifout";
reg = <0x0 0x480 0x0 0x50>;
#sound-dai-cells = <0>;
sound-name-prefix = "SPDIFOUT";
clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
clock-names = "pclk", "mclk";
status = "disabled";
};
tdmout_a: audio-controller@500 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x500 0x0 0x40>;
sound-name-prefix = "TDMOUT_A";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
tdmout_b: audio-controller@540 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x540 0x0 0x40>;
sound-name-prefix = "TDMOUT_B";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13400 0x400>;
tdmout_c: audio-controller@580 {
compatible = "amlogic,axg-tdmout";
reg = <0x0 0x580 0x0 0x40>;
sound-name-prefix = "TDMOUT_C";
clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
<&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
clock-names = "pclk", "sclk", "sclk_sel",
"lrclk", "lrclk_sel";
status = "disabled";
};
};
......@@ -1329,7 +1209,7 @@ aobus: bus@ff800000 {
ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-axg-ao-sysctrl", "syscon", "simple-mfd";
compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
clkc_AO: clock-controller {
......@@ -1347,8 +1227,8 @@ pinctrl_aobus: pinctrl@14 {
gpio_ao: bank@14 {
reg = <0x0 0x00014 0x0 0x8>,
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
<0x0 0x0002c 0x0 0x4>,
<0x0 0x00024 0x0 0x8>;
reg-names = "mux", "pull", "gpio";
gpio-controller;
#gpio-cells = <2>;
......@@ -1407,7 +1287,7 @@ mux {
uart_ao_a_pins: uart_ao_a {
mux {
groups = "uart_ao_tx_a",
"uart_ao_rx_a";
"uart_ao_rx_a";
function = "uart_ao_a";
};
};
......@@ -1415,7 +1295,7 @@ mux {
uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
mux {
groups = "uart_ao_cts_a",
"uart_ao_rts_a";
"uart_ao_rts_a";
function = "uart_ao_a";
};
};
......@@ -1423,7 +1303,7 @@ mux {
uart_ao_b_pins: uart_ao_b {
mux {
groups = "uart_ao_tx_b",
"uart_ao_rx_b";
"uart_ao_rx_b";
function = "uart_ao_b";
};
};
......@@ -1431,7 +1311,7 @@ mux {
uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
mux {
groups = "uart_ao_cts_b",
"uart_ao_rts_b";
"uart_ao_rts_b";
function = "uart_ao_b";
};
};
......@@ -1443,13 +1323,6 @@ sec_AO: ao-secure@140 {
amlogic,has-chip-id;
};
pwm_AO_ab: pwm@7000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x07000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_AO_cd: pwm@2000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x02000 0x0 0x20>;
......@@ -1457,16 +1330,6 @@ pwm_AO_cd: pwm@2000 {
status = "disabled";
};
i2c_AO: i2c@5000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x05000 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart_AO: serial@3000 {
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
reg = <0x0 0x3000 0x0 0x18>;
......@@ -1485,6 +1348,23 @@ uart_AO_B: serial@4000 {
status = "disabled";
};
i2c_AO: i2c@5000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x05000 0x0 0x20>;
interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_AO_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pwm_AO_ab: pwm@7000 {
compatible = "amlogic,meson-axg-ao-pwm";
reg = <0x0 0x07000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
ir: ir@8000 {
compatible = "amlogic,meson-gxbb-ir";
reg = <0x0 0x8000 0x0 0x20>;
......@@ -1499,12 +1379,211 @@ saradc: adc@9000 {
#io-channel-cells = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>,
<&clkc_AO CLKID_AO_SAR_ADC>,
<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
<&clkc_AO CLKID_AO_SAR_ADC>,
<&clkc_AO CLKID_AO_SAR_ADC_CLK>,
<&clkc_AO CLKID_AO_SAR_ADC_SEL>;
clock-names = "clkin", "core", "adc_clk", "adc_sel";
status = "disabled";
};
};
gic: interrupt-controller@ffc01000 {
compatible = "arm,gic-400";
reg = <0x0 0xffc01000 0 0x1000>,
<0x0 0xffc02000 0 0x2000>,
<0x0 0xffc04000 0 0x2000>,
<0x0 0xffc06000 0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
cbus: bus@ffd00000 {
compatible = "simple-bus";
reg = <0x0 0xffd00000 0x0 0x25000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
reset: reset-controller@1004 {
compatible = "amlogic,meson-axg-reset";
reg = <0x0 0x01004 0x0 0x9c>;
#reset-cells = <1>;
};
gpio_intc: interrupt-controller@f080 {
compatible = "amlogic,meson-gpio-intc";
reg = <0x0 0xf080 0x0 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
pwm_ab: pwm@1b000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1b000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
pwm_cd: pwm@1a000 {
compatible = "amlogic,meson-axg-ee-pwm";
reg = <0x0 0x1a000 0x0 0x20>;
#pwm-cells = <3>;
status = "disabled";
};
spicc0: spi@13000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x13000 0x0 0x3c>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC0>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spicc1: spi@15000 {
compatible = "amlogic,meson-axg-spicc";
reg = <0x0 0x15000 0x0 0x3c>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkc CLKID_SPICC1>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@1c000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1c000 0x0 0x20>;
interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@1d000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1d000 0x0 0x20>;
interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@1e000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1e000 0x0 0x20>;
interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@1f000 {
compatible = "amlogic,meson-axg-i2c";
reg = <0x0 0x1f000 0x0 0x20>;
interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
clocks = <&clkc CLKID_I2C>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart_B: serial@23000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x23000 0x0 0x18>;
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
uart_A: serial@24000 {
compatible = "amlogic,meson-gx-uart";
reg = <0x0 0x24000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
};
};
apb: bus@ffe00000 {
compatible = "simple-bus";
reg = <0x0 0xffe00000 0x0 0x200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
sd_emmc_b: sd@5000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x5000 0x0 0x800>;
interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_B>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_B>;
};
sd_emmc_c: mmc@7000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0x7000 0x0 0x800>;
interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_C>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
resets = <&reset RESET_SD_EMMC_C>;
};
};
sram: sram@fffc0000 {
compatible = "amlogic,meson-axg-sram", "mmio-sram";
reg = <0x0 0xfffc0000 0x0 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0xfffc0000 0x20000>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13000 0x400>;
};
cpu_scp_hpri: scp-shmem@200 {
compatible = "amlogic,meson-axg-scp-shmem";
reg = <0x13400 0x400>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
};
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View file @ 68df1dba
......@@ -44,7 +44,7 @@ secmon_reserved_alt: secmon@5000000 {
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xbc00000>;
size = <0x0 0x10000000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
......@@ -344,7 +344,7 @@ aobus: bus@c8100000 {
ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
sysctrl_AO: sys-ctrl@0 {
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
reg = <0x0 0x0 0x0 0x100>;
pwrc_vpu: power-controller-vpu {
......@@ -423,6 +423,19 @@ hwrng: rng {
};
};
dmcbus: bus@c8838000 {
compatible = "simple-bus";
reg = <0x0 0xc8838000 0x0 0x400>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>;
canvas: video-lut@48 {
compatible = "amlogic,canvas";
reg = <0x0 0x48 0x0 0x14>;
};
};
hiubus: bus@c883c000 {
compatible = "simple-bus";
reg = <0x0 0xc883c000 0x0 0x2000>;
......@@ -431,7 +444,7 @@ hiubus: bus@c883c000 {
ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
sysctrl: system-controller@0 {
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
reg = <0 0 0 0x400>;
};
......
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View file @ 68df1dba
......@@ -13,7 +13,7 @@
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
model = "Libre Technology CC";
model = "Libre Computer Board AML-S905X-CC";
aliases {
serial0 = &uart_AO;
......
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