Commit 69c8a9bc authored by Clark Wang's avatar Clark Wang Committed by Mark Brown

spi: lpspi: fix dataloss when SS is inactivated between every words

If we don't use CONT to keep SS activated or use DMA mode without
cs-gpio, SS will be inactivated between every words. The word here
means the data sent once which length can be set as 1/2/4 bytes.

In the isr function, we read the FSR_RXCOUNT just behind the
fsl_lpspi_read_rx_fifo. This causes the value of FSR_RXCOUNT cannot
reflect whether there is still data not sent timely. So do this
judgement by FSR_TXCOUNT.
Signed-off-by: default avatarClark Wang <xiaoning.wang@nxp.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f37d8e67
...@@ -62,7 +62,7 @@ ...@@ -62,7 +62,7 @@
#define CFGR1_PCSPOL BIT(8) #define CFGR1_PCSPOL BIT(8)
#define CFGR1_NOSTALL BIT(3) #define CFGR1_NOSTALL BIT(3)
#define CFGR1_MASTER BIT(0) #define CFGR1_MASTER BIT(0)
#define FSR_RXCOUNT (BIT(16)|BIT(17)|BIT(18)) #define FSR_TXCOUNT (0xFF)
#define RSR_RXEMPTY BIT(1) #define RSR_RXEMPTY BIT(1)
#define TCR_CPOL BIT(31) #define TCR_CPOL BIT(31)
#define TCR_CPHA BIT(30) #define TCR_CPHA BIT(30)
...@@ -452,7 +452,7 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id) ...@@ -452,7 +452,7 @@ static irqreturn_t fsl_lpspi_isr(int irq, void *dev_id)
} }
if (temp_SR & SR_MBF || if (temp_SR & SR_MBF ||
readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_RXCOUNT) { readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR); writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE); fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
return IRQ_HANDLED; return IRQ_HANDLED;
......
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