Commit 6ce448ee authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'hisi-arm32-dt-for-5.9' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM: DT: Hisilicon ARM32 SoCs updates for v5.9

- Update L2 cache controller nodes to fix dtschema validator warnings
  for hi3620 and hix5hd2

* tag 'hisi-arm32-dt-for-5.9' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: hisilicon: Align L2 cache-controller nodename with dtschema

Link: https://lore.kernel.org/r/5F165FA1.2030301@hisilicon.comSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 4828f457 5720fcdc
...@@ -71,7 +71,7 @@ amba { ...@@ -71,7 +71,7 @@ amba {
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>; ranges = <0 0xfc000000 0x2000000>;
L2: l2-cache { L2: cache-controller {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x100000 0x100000>; reg = <0x100000 0x100000>;
interrupts = <0 15 4>; interrupts = <0 15 4>;
......
...@@ -381,7 +381,7 @@ local_timer@a00600 { ...@@ -381,7 +381,7 @@ local_timer@a00600 {
interrupts = <1 13 0xf01>; interrupts = <1 13 0xf01>;
}; };
l2: l2-cache { l2: cache-controller {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x00a10000 0x100000>; reg = <0x00a10000 0x100000>;
interrupts = <0 15 4>; interrupts = <0 15 4>;
......
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