Skip to content

L
linux
Commit 6cf813fb authored by Ben Skeggs's avatar Ben Skeggs
Browse files
Options

drm/nouveau/device: prepare for new-style subdevs 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 7974dd1b
Hide whitespace changes
Inline Side-by-side
Showing with 2378 additions and 437 deletions
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file @ 6cf813fb
......@@ -84,9 +84,9 @@ struct nvkm_device {
struct nvkm_event event;
const char *cname;
u64 disable_mask;
const struct nvkm_device_chip *chip;
enum {
NV_04 = 0x04,
NV_10 = 0x10,
......@@ -104,7 +104,6 @@ struct nvkm_device {
u32 crystal;
struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR];
struct nvkm_object *subdev[NVDEV_SUBDEV_NR];
struct {
struct notifier_block nb;
......@@ -153,6 +152,9 @@ struct nvkm_device {
struct nouveau_platform_gpu *gpu;
};
struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index);
struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index);
struct nvkm_device_func {
struct nvkm_device_pci *(*pci)(struct nvkm_device *);
struct nvkm_device_tegra *(*tegra)(struct nvkm_device *);
......@@ -164,6 +166,50 @@ struct nvkm_device_func {
struct nvkm_device_quirk {
};
struct nvkm_device_chip {
const char *name;
int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **);
int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **);
int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **);
int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **);
int (*devinit)(struct nvkm_device *, int idx, struct nvkm_devinit **);
int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **);
int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **);
int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **);
int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **);
int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **);
int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **);
int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **);
int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **);
int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **);
int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **);
int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **);
int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **);
int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **);
int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **);
int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*ce[3] )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **);
int (*dma )(struct nvkm_device *, int idx, struct nvkm_dmaeng **);
int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **);
int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **);
int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **);
int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **);
};
struct nvkm_device *nvkm_device_find(u64 name);
int nvkm_device_list(u64 *name, int size);
......
drivers/gpu/drm/nouveau/nvkm/core/engine.c
View file @ 6cf813fb
......@@ -68,6 +68,8 @@ static int
nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend)
{
struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
if (engine->subdev.object.oclass)
return engine->subdev.object.oclass->ofuncs->fini(&engine->subdev.object, suspend);
if (engine->func->fini)
return engine->func->fini(engine, suspend);
return 0;
......@@ -86,6 +88,9 @@ nvkm_engine_init(struct nvkm_subdev *obj)
return ret;
}
if (engine->subdev.object.oclass)
return engine->subdev.object.oclass->ofuncs->init(&engine->subdev.object);
if (engine->func->oneinit && !engine->subdev.oneinit) {
nvkm_trace(subdev, "one-time init running...\n");
time = ktime_to_us(ktime_get());
......@@ -110,6 +115,10 @@ static void *
nvkm_engine_dtor(struct nvkm_subdev *obj)
{
struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev);
if (engine->subdev.object.oclass) {
engine->subdev.object.oclass->ofuncs->dtor(&engine->subdev.object);
return NULL;
}
if (engine->func->dtor)
return engine->func->dtor(engine);
return engine;
......@@ -201,5 +210,6 @@ nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
INIT_LIST_HEAD(&engine->contexts);
spin_lock_init(&engine->lock);
engine->subdev.func = &nvkm_engine_func;
return 0;
}
drivers/gpu/drm/nouveau/nvkm/core/ioctl.c
View file @ 6cf813fb
......@@ -91,7 +91,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
struct nvkm_object *engctx = NULL;
struct nvkm_object *object = NULL;
struct nvkm_parent *parent;
struct nvkm_object *engine;
struct nvkm_engine *engine;
struct nvkm_oclass *oclass;
u32 _handle, _oclass;
int ret;
......@@ -117,7 +117,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
parent = nv_parent(handle->object);
/* check that parent supports the requested subclass */
ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass);
ret = nvkm_parent_sclass(&parent->object, _oclass,
(struct nvkm_object **)&engine, &oclass);
if (ret) {
nvif_debug(&parent->object, "illegal class 0x%04x\n", _oclass);
goto fail_class;
......@@ -128,18 +129,20 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
* state calculated at init (ie. default context construction)
*/
if (engine) {
ret = nvkm_object_inc(engine);
if (ret)
engine = nvkm_engine_ref(engine);
if (IS_ERR(engine)) {
ret = PTR_ERR(engine);
engine = NULL;
goto fail_class;
}
}
/* if engine requires it, create a context object to insert
* between the parent and its children (eg. PGRAPH context)
*/
if (engine && nv_engine(engine)->cclass) {
ret = nvkm_object_old(&parent->object, engine,
nv_engine(engine)->cclass,
data, size, &engctx);
if (engine && engine->cclass) {
ret = nvkm_object_old(&parent->object, &engine->subdev.object,
engine->cclass, data, size, &engctx);
if (ret)
goto fail_engctx;
} else {
......@@ -147,7 +150,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
}
/* finally, create new object and bind it to its handle */
ret = nvkm_object_old(engctx, engine, oclass, data, size, &object);
ret = nvkm_object_old(engctx, &engine->subdev.object, oclass,
data, size, &object);
client->data = object;
if (ret)
goto fail_ctor;
......@@ -178,8 +182,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size)
fail_ctor:
nvkm_object_ref(NULL, &engctx);
fail_engctx:
if (engine)
nvkm_object_dec(engine, false);
nvkm_engine_unref(&engine);
fail_class:
return ret;
}
......
drivers/gpu/drm/nouveau/nvkm/core/object.c
View file @ 6cf813fb
......@@ -201,6 +201,7 @@ nvkm_object_del(struct nvkm_object **pobject)
if (object && !WARN_ON(!object->func)) {
if (object->func->dtor)
*pobject = object->func->dtor(object);
nvkm_engine_unref(&object->engine);
kfree(*pobject);
*pobject = NULL;
}
......@@ -212,7 +213,7 @@ nvkm_object_ctor(const struct nvkm_object_func *func,
{
object->func = func;
object->client = oclass->client;
object->engine = oclass->engine;
object->engine = nvkm_engine_ref(oclass->engine);
object->oclass_name = oclass->base.oclass;
object->handle = oclass->handle;
object->parent = oclass->parent;
......@@ -251,10 +252,11 @@ nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
}
int
nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine,
nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engobj,
struct nvkm_oclass *oclass, u32 pclass,
int size, void **pobject)
{
struct nvkm_engine *engine = engobj ? nv_engine(engobj) : NULL;
struct nvkm_object *object;
object = *pobject = kzalloc(size, GFP_KERNEL);
......@@ -262,7 +264,7 @@ nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine,
return -ENOMEM;
nvkm_object_ref(parent, &object->parent);
nvkm_object_ref(engine, (struct nvkm_object **)&object->engine);
object->engine = nvkm_engine_ref(engine);
object->oclass = oclass;
object->pclass = pclass;
atomic_set(&object->refcount, 1);
......@@ -287,7 +289,7 @@ _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
void
nvkm_object_destroy(struct nvkm_object *object)
{
nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine);
nvkm_engine_unref(&object->engine);
nvkm_object_ref(NULL, &object->parent);
kfree(object);
}
......@@ -333,7 +335,8 @@ nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine,
}
if (ret == 0) {
atomic_set(&object->refcount, 1);
if (!nv_iclass(object, NV_SUBDEV_CLASS))
atomic_set(&object->refcount, 1);
}
return 0;
......@@ -370,14 +373,6 @@ nvkm_object_inc(struct nvkm_object *object)
goto fail_parent;
}
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
ret = nvkm_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret)
goto fail_engine;
}
ret = nvkm_object_init(object);
atomic_set(&object->usecount, 1);
if (ret)
......@@ -386,12 +381,6 @@ nvkm_object_inc(struct nvkm_object *object)
return 0;
fail_self:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
nvkm_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
fail_engine:
if (object->parent)
nvkm_object_dec(object->parent, false);
fail_parent:
......@@ -405,12 +394,6 @@ nvkm_object_decf(struct nvkm_object *object)
nvkm_object_fini(object, false);
atomic_set(&object->usecount, 0);
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
nvkm_object_dec(&object->engine->subdev.object, false);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
if (object->parent)
nvkm_object_dec(object->parent, false);
......@@ -427,14 +410,6 @@ nvkm_object_decs(struct nvkm_object *object)
if (ret)
return ret;
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
ret = nvkm_object_dec(&object->engine->subdev.object, true);
mutex_unlock(&nv_subdev(object->engine)->mutex);
if (ret)
goto fail_engine;
}
if (object->parent) {
ret = nvkm_object_dec(object->parent, true);
if (ret)
......@@ -444,13 +419,6 @@ nvkm_object_decs(struct nvkm_object *object)
return 0;
fail_parent:
if (object->engine) {
mutex_lock(&nv_subdev(object->engine)->mutex);
nvkm_object_inc(&object->engine->subdev.object);
mutex_unlock(&nv_subdev(object->engine)->mutex);
}
fail_engine:
nvkm_object_init(object);
return ret;
......
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file @ 6cf813fb
......@@ -74,6 +74,12 @@ nvkm_subdev_name[64] = {
void
nvkm_subdev_intr(struct nvkm_subdev *subdev)
{
if (subdev->object.oclass) {
if (subdev->intr)
subdev->intr(subdev);
return;
}
if (subdev->func->intr)
subdev->func->intr(subdev);
}
......@@ -85,10 +91,18 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
const char *action = suspend ? "suspend" : "fini";
u32 pmc_enable = subdev->pmc_enable;
s64 time;
int ret;
nvkm_trace(subdev, "%s running...\n", action);
time = ktime_to_us(ktime_get());
if (!subdev->func) {
ret = subdev->object.oclass->ofuncs->fini(&subdev->object, suspend);
if (ret)
return ret;
goto done;
}
if (subdev->func->fini) {
int ret = subdev->func->fini(subdev, suspend);
if (ret) {
......@@ -104,6 +118,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend)
nvkm_rd32(device, 0x000200);
}
done:
time = ktime_to_us(ktime_get()) - time;
nvkm_trace(subdev, "%s completed in %lldus\n", action, time);
return 0;
......@@ -117,7 +132,7 @@ nvkm_subdev_preinit(struct nvkm_subdev *subdev)
nvkm_trace(subdev, "preinit running...\n");
time = ktime_to_us(ktime_get());
if (subdev->func->preinit) {
if (!subdev->object.oclass && subdev->func->preinit) {
int ret = subdev->func->preinit(subdev);
if (ret) {
nvkm_error(subdev, "preinit failed, %d\n", ret);
......@@ -139,6 +154,13 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
nvkm_trace(subdev, "init running...\n");
time = ktime_to_us(ktime_get());
if (!subdev->func) {
ret = subdev->object.oclass->ofuncs->init(&subdev->object);
if (ret)
return ret;
goto done;
}
if (subdev->func->oneinit && !subdev->oneinit) {
s64 time;
nvkm_trace(subdev, "one-time init running...\n");
......@@ -162,6 +184,7 @@ nvkm_subdev_init(struct nvkm_subdev *subdev)
}
}
done:
time = ktime_to_us(ktime_get()) - time;
nvkm_trace(subdev, "init completed in %lldus\n", time);
return 0;
......@@ -172,6 +195,12 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev)
{
struct nvkm_subdev *subdev = *psubdev;
s64 time;
if (subdev && subdev->object.oclass) {
subdev->object.oclass->ofuncs->dtor(&subdev->object);
return;
}
if (subdev && !WARN_ON(!subdev->func)) {
nvkm_trace(subdev, "destroy running...\n");
time = ktime_to_us(ktime_get());
......@@ -211,8 +240,10 @@ nvkm_subdev(void *obj, int idx)
struct nvkm_object *object = nv_object(obj);
while (object && !nv_iclass(object, NV_SUBDEV_CLASS))
object = object->parent;
if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx)
object = nv_device(obj)->subdev[idx];
if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) {
struct nvkm_device *device = nv_device(obj);
return nvkm_device_subdev(device, idx);
}
return object ? nv_subdev(object) : NULL;
}
......@@ -266,8 +297,6 @@ _nvkm_subdev_fini(struct nvkm_object *object, bool suspend)
void
nvkm_subdev_destroy(struct nvkm_subdev *subdev)
{
int subidx = nv_hclass(subdev) & 0xff;
nv_device(subdev)->subdev[subidx] = NULL;
nvkm_object_destroy(&subdev->object);
}
......
drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c
View file @ 6cf813fb
......@@ -40,21 +40,19 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data)
}
#endif
int
nvkm_acpi_fini(struct nvkm_device *device, bool suspend)
void
nvkm_acpi_fini(struct nvkm_device *device)
{
#ifdef CONFIG_ACPI
unregister_acpi_notifier(&device->acpi.nb);
#endif
return 0;
}
int
void
nvkm_acpi_init(struct nvkm_device *device)
{
#ifdef CONFIG_ACPI
device->acpi.nb.notifier_call = nvkm_acpi_ntfy;
register_acpi_notifier(&device->acpi.nb);
#endif
return 0;
}
drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h
View file @ 6cf813fb
......@@ -3,6 +3,6 @@
#include <core/os.h>
struct nvkm_device;
int nvkm_acpi_init(struct nvkm_device *);
int nvkm_acpi_fini(struct nvkm_device *, bool);
void nvkm_acpi_init(struct nvkm_device *);
void nvkm_acpi_fini(struct nvkm_device *);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file @ 6cf813fb
......@@ -67,6 +67,1916 @@ nvkm_device_list(u64 *name, int size)
return nr;
}
static const struct nvkm_device_chip
null_chipset = {
.name = "NULL",
// .bios = nvkm_bios_new,
};
static const struct nvkm_device_chip
nv4_chipset = {
.name = "NV04",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
// .sw = nv04_sw_new,
};
static const struct nvkm_device_chip
nv5_chipset = {
.name = "NV05",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv04_fifo_new,
// .gr = nv04_gr_new,
// .sw = nv04_sw_new,
};
static const struct nvkm_device_chip
nv10_chipset = {
.name = "NV10",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .gr = nv10_gr_new,
};
static const struct nvkm_device_chip
nv11_chipset = {
.name = "NV11",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv15_chipset = {
.name = "NV15",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv17_chipset = {
.name = "NV17",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv18_chipset = {
.name = "NV18",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv1a_chipset = {
.name = "nForce",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv10_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv1f_chipset = {
.name = "nForce2",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv10_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv20_chipset = {
.name = "NV20",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv20_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv25_chipset = {
.name = "NV25",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv28_chipset = {
.name = "NV28",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv25_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv2a_chipset = {
.name = "NV2A",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv2a_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv30_chipset = {
.name = "NV30",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv31_chipset = {
.name = "NV31",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv30_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv34_chipset = {
.name = "NV34",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv34_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv35_chipset = {
.name = "NV35",
// .bios = nvkm_bios_new,
// .bus = nv04_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv36_chipset = {
.name = "NV36",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv04_clk_new,
// .devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv17_fifo_new,
// .gr = nv35_gr_new,
// .mpeg = nv31_mpeg_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv40_chipset = {
.name = "NV40",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv41_chipset = {
.name = "NV41",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv42_chipset = {
.name = "NV42",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv43_chipset = {
.name = "NV43",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv40_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv44_chipset = {
.name = "NV44",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv45_chipset = {
.name = "NV45",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv46_chipset = {
.name = "G72",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv47_chipset = {
.name = "G70",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv49_chipset = {
.name = "G71",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv4a_chipset = {
.name = "NV44A",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv4b_chipset = {
.name = "G73",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv4c_chipset = {
.name = "C61",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv4e_chipset = {
.name = "C51",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv4e_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv50_chipset = {
.name = "G80",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = nv50_clk_new,
// .devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = nv50_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv50_disp_new,
// .dma = nv50_dma_new,
// .fifo = nv50_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = nv50_mpeg_new,
// .pm = nv50_pm_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nv63_chipset = {
.name = "C73",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv67_chipset = {
.name = "C67",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv68_chipset = {
.name = "C68",
// .bios = nvkm_bios_new,
// .bus = nv31_bus_new,
// .clk = nv40_clk_new,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
// .i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = nv04_disp_new,
// .dma = nv04_dma_new,
// .fifo = nv40_fifo_new,
// .gr = nv40_gr_new,
// .mpeg = nv44_mpeg_new,
// .pm = nv40_pm_new,
// .sw = nv10_sw_new,
};
static const struct nvkm_device_chip
nv84_chipset = {
.name = "G84",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
};
static const struct nvkm_device_chip
nv86_chipset = {
.name = "G86",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
};
static const struct nvkm_device_chip
nv92_chipset = {
.name = "G92",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = nv50_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = nv50_gpio_new,
// .i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g84_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
};
static const struct nvkm_device_chip
nv94_chipset = {
.name = "G94",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g94_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = g84_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
};
static const struct nvkm_device_chip
nv96_chipset = {
.name = "G96",
// .bios = nvkm_bios_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
// .clk = g84_clk_new,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g84_devinit_new,
// .mc = g94_mc_new,
// .bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
// .bar = nv50_bar_new,
// .volt = nv40_volt_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .vp = g84_vp_new,
// .cipher = g84_cipher_new,
// .bsp = g84_bsp_new,
// .disp = g94_disp_new,
// .pm = g84_pm_new,
};
static const struct nvkm_device_chip
nv98_chipset = {
.name = "G98",
// .bios = nvkm_bios_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
// .clk = g84_clk_new,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g98_devinit_new,
// .mc = g98_mc_new,
// .bus = g94_bus_new,
// .timer = nv04_timer_new,
// .fb = g84_fb_new,
// .imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
// .bar = nv50_bar_new,
// .volt = nv40_volt_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .sw = nv50_sw_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .sec = g98_sec_new,
// .msvld = g98_msvld_new,
// .msppp = g98_msppp_new,
// .disp = g94_disp_new,
// .pm = g84_pm_new,
};
static const struct nvkm_device_chip
nva0_chipset = {
.name = "GT200",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = g84_clk_new,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .bsp = g84_bsp_new,
// .cipher = g84_cipher_new,
// .disp = gt200_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .pm = gt200_pm_new,
// .sw = nv50_sw_new,
// .vp = g84_vp_new,
};
static const struct nvkm_device_chip
nva3_chipset = {
.name = "GT215",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mpeg = g84_mpeg_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nva5_chipset = {
.name = "GT216",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nva8_chipset = {
.name = "GT218",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nvaa_chipset = {
.name = "MCP77/MCP78",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = g84_pm_new,
// .sec = g98_sec_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nvac_chipset = {
.name = "MCP79/MCP7A",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = mcp77_clk_new,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = g84_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .disp = g94_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = g84_pm_new,
// .sec = g98_sec_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nvaf_chipset = {
.name = "MCP89",
// .bar = nv50_bar_new,
// .bios = nvkm_bios_new,
// .bus = g94_bus_new,
// .clk = gt215_clk_new,
// .devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
// .fuse = nv50_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gt215_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gt215_ce_new,
// .disp = gt215_disp_new,
// .dma = nv50_dma_new,
// .fifo = g84_fifo_new,
// .gr = nv50_gr_new,
// .mspdec = g98_mspdec_new,
// .msppp = g98_msppp_new,
// .msvld = g98_msvld_new,
// .pm = gt215_pm_new,
// .sw = nv50_sw_new,
};
static const struct nvkm_device_chip
nvc0_chipset = {
.name = "GF100",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf100_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvc1_chipset = {
.name = "GF108",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf108_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf108_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvc3_chipset = {
.name = "GF106",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvc4_chipset = {
.name = "GF104",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvc8_chipset = {
.name = "GF110",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf110_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvce_chipset = {
.name = "GF114",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .ce[1] = gf100_ce1_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvcf_chipset = {
.name = "GF116",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf100_pmu_new,
// .therm = gt215_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gt215_disp_new,
// .dma = gf100_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf104_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf100_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvd7_chipset = {
.name = "GF117",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
// .i2c = gf117_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .ce[0] = gf100_ce0_new,
// .disp = gf119_disp_new,
// .dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf117_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf117_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvd9_chipset = {
.name = "GF119",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gf100_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gf110_gpio_new,
// .i2c = gf110_i2c_new,
// .ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gf100_ce0_new,
// .disp = gf119_disp_new,
// .dma = gf119_dma_new,
// .fifo = gf100_fifo_new,
// .gr = gf119_gr_new,
// .mspdec = gf100_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gf100_msvld_new,
// .pm = gf117_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nve4_chipset = {
.name = "GK104",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk104_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nve6_chipset = {
.name = "GK106",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk104_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk104_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nve7_chipset = {
.name = "GK107",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gf110_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk104_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk104_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvea_chipset = {
.name = "GK20A",
// .bar = gk20a_bar_new,
// .bus = gf100_bus_new,
// .clk = gk20a_clk_new,
// .fb = gk20a_fb_new,
// .fuse = gf100_fuse_new,
// .ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .pmu = gk20a_pmu_new,
// .timer = gk20a_timer_new,
// .volt = gk20a_volt_new,
// .ce[2] = gk104_ce2_new,
// .dma = gf119_dma_new,
// .fifo = gk20a_fifo_new,
// .gr = gk20a_gr_new,
// .pm = gk104_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvf0_chipset = {
.name = "GK110",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk110_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .pm = gk110_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nvf1_chipset = {
.name = "GK110B",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk110_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk110_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk104_fifo_new,
// .gr = gk110b_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .pm = gk110_pm_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv106_chipset = {
.name = "GK208B",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk110_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv108_chipset = {
.name = "GK208",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gk104_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gf110_therm_new,
// .timer = nv04_timer_new,
// .volt = nv40_volt_new,
// .ce[0] = gk104_ce0_new,
// .ce[1] = gk104_ce1_new,
// .ce[2] = gk104_ce2_new,
// .disp = gk110_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gk208_gr_new,
// .mspdec = gk104_mspdec_new,
// .msppp = gf100_msppp_new,
// .msvld = gk104_msvld_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv117_chipset = {
.name = "GM107",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .clk = gk104_clk_new,
// .devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gf110_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .therm = gm107_therm_new,
// .timer = gk20a_timer_new,
// .ce[0] = gk104_ce0_new,
// .ce[2] = gk104_ce2_new,
// .disp = gm107_disp_new,
// .dma = gf119_dma_new,
// .fifo = gk208_fifo_new,
// .gr = gm107_gr_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv124_chipset = {
.name = "GM204",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new,
// .ce[2] = gm204_ce2_new,
// .disp = gm204_disp_new,
// .dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm204_gr_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv126_chipset = {
.name = "GM206",
// .bar = gf100_bar_new,
// .bios = nvkm_bios_new,
// .bus = gf100_bus_new,
// .devinit = gm204_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
// .gpio = gk104_gpio_new,
// .i2c = gm204_i2c_new,
// .ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mxm = nv50_mxm_new,
// .pmu = gk208_pmu_new,
// .timer = gk20a_timer_new,
// .ce[0] = gm204_ce0_new,
// .ce[1] = gm204_ce1_new,
// .ce[2] = gm204_ce2_new,
// .disp = gm204_disp_new,
// .dma = gf119_dma_new,
// .fifo = gm204_fifo_new,
// .gr = gm206_gr_new,
// .sw = gf100_sw_new,
};
static const struct nvkm_device_chip
nv12b_chipset = {
.name = "GM20B",
// .bar = gk20a_bar_new,
// .bus = gf100_bus_new,
// .fb = gk20a_fb_new,
// .fuse = gm107_fuse_new,
// .ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
// .mmu = gf100_mmu_new,
// .timer = gk20a_timer_new,
// .ce[2] = gm204_ce2_new,
// .dma = gf119_dma_new,
// .fifo = gm20b_fifo_new,
// .gr = gm20b_gr_new,
// .sw = gf100_sw_new,
};
#include <core/parent.h>
#include <core/client.h>
......@@ -116,45 +2026,129 @@ nvkm_device_event_func = {
.ctor = nvkm_device_event_ctor,
};
struct nvkm_subdev *
nvkm_device_subdev(struct nvkm_device *device, int index)
{
struct nvkm_engine *engine;
if (device->disable_mask & (1ULL << index))
return NULL;
switch (index) {
#define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break
_(BAR , device->bar , &device->bar->subdev);
_(VBIOS , device->bios , &device->bios->subdev);
_(BUS , device->bus , &device->bus->subdev);
_(CLK , device->clk , &device->clk->subdev);
_(DEVINIT, device->devinit, &device->devinit->subdev);
_(FB , device->fb , &device->fb->subdev);
_(FUSE , device->fuse , &device->fuse->subdev);
_(GPIO , device->gpio , &device->gpio->subdev);
_(I2C , device->i2c , &device->i2c->subdev);
_(IBUS , device->ibus , device->ibus);
_(INSTMEM, device->imem , &device->imem->subdev);
_(LTC , device->ltc , &device->ltc->subdev);
_(MC , device->mc , &device->mc->subdev);
_(MMU , device->mmu , &device->mmu->subdev);
_(MXM , device->mxm , device->mxm);
_(PMU , device->pmu , &device->pmu->subdev);
_(THERM , device->therm , &device->therm->subdev);
_(TIMER , device->timer , &device->timer->subdev);
_(VOLT , device->volt , &device->volt->subdev);
#undef _
default:
engine = nvkm_device_engine(device, index);
if (engine)
return &engine->subdev;
break;
}
return NULL;
}
struct nvkm_engine *
nvkm_device_engine(struct nvkm_device *device, int index)
{
if (device->disable_mask & (1ULL << index))
return NULL;
switch (index) {
#define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break
_(BSP , device->bsp , device->bsp);
_(CE0 , device->ce[0] , device->ce[0]);
_(CE1 , device->ce[1] , device->ce[1]);
_(CE2 , device->ce[2] , device->ce[2]);
_(CIPHER , device->cipher , device->cipher);
_(DISP , device->disp , &device->disp->engine);
_(DMAOBJ , device->dma , &device->dma->engine);
_(FIFO , device->fifo , &device->fifo->engine);
_(GR , device->gr , &device->gr->engine);
_(IFB , device->ifb , device->ifb);
_(ME , device->me , device->me);
_(MPEG , device->mpeg , device->mpeg);
_(MSENC , device->msenc , device->msenc);
_(MSPDEC , device->mspdec , device->mspdec);
_(MSPPP , device->msppp , device->msppp);
_(MSVLD , device->msvld , device->msvld);
_(PM , device->pm , &device->pm->engine);
_(SEC , device->sec , device->sec);
_(SW , device->sw , &device->sw->engine);
_(VIC , device->vic , device->vic);
_(VP , device->vp , device->vp);
#undef _
default:
WARN_ON(1);
break;
}
return NULL;
}
int
nvkm_device_fini(struct nvkm_device *device, bool suspend)
{
struct nvkm_object *subdev;
const char *action = suspend ? "suspend" : "fini";
struct nvkm_subdev *subdev;
int ret, i;
s64 time;
nvdev_trace(device, "%s running...\n", action);
time = ktime_to_us(ktime_get());
nvkm_acpi_fini(device);
for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
ret = nvkm_object_dec(subdev, suspend);
if (ret && suspend)
goto fail;
}
if ((subdev = nvkm_device_subdev(device, i))) {
ret = nvkm_subdev_fini(subdev, suspend);
if (ret && suspend)
goto fail;
}
}
ret = nvkm_acpi_fini(device, suspend);
if (device->func->fini)
device->func->fini(device, suspend);
time = ktime_to_us(ktime_get()) - time;
nvdev_trace(device, "%s completed in %lldus...\n", action, time);
return 0;
fail:
for (; ret && i < NVDEV_SUBDEV_NR; i++) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
ret = nvkm_object_inc(subdev);
if (ret) {
/* XXX */
}
}
do {
if ((subdev = nvkm_device_subdev(device, i))) {
int rret = nvkm_subdev_init(subdev);
if (rret)
nvkm_fatal(subdev, "failed restart, %d\n", ret);
}
}
} while (++i < NVDEV_SUBDEV_NR);
nvdev_trace(device, "%s failed with %d\n", action, ret);
return ret;
}
int
static int
nvkm_device_preinit(struct nvkm_device *device)
{
int ret;
struct nvkm_subdev *subdev;
int ret, i;
s64 time;
nvdev_trace(device, "preinit running...\n");
......@@ -166,6 +2160,16 @@ nvkm_device_preinit(struct nvkm_device *device)
goto fail;
}
for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
if ((subdev = nvkm_device_subdev(device, i))) {
ret = nvkm_subdev_preinit(subdev);
if (ret)
goto fail;
}
}
/*XXX: devinit */
time = ktime_to_us(ktime_get()) - time;
nvdev_trace(device, "preinit completed in %lldus\n", time);
return 0;
......@@ -178,19 +2182,21 @@ nvkm_device_preinit(struct nvkm_device *device)
int
nvkm_device_init(struct nvkm_device *device)
{
struct nvkm_object *subdev;
struct nvkm_subdev *subdev;
int ret, i = 0, c;
s64 time;
ret = nvkm_device_preinit(device);
if (ret)
return ret;
ret = nvkm_acpi_init(device);
if (ret)
goto fail;
nvkm_device_fini(device, false);
nvdev_trace(device, "init running...\n");
time = ktime_to_us(ktime_get());
for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) {
#define _(s,m) case s: if (device->oclass[s] && !device->subdev[s]) { \
#define _(s,m) case s: if (device->oclass[s] && !device->m) { \
ret = nvkm_object_old(nv_object(device), NULL, \
device->oclass[s], NULL, (s), \
(struct nvkm_object **)&device->m); \
......@@ -200,7 +2206,6 @@ nvkm_device_init(struct nvkm_device *device)
} \
if (ret) \
goto fail; \
device->subdev[s] = (struct nvkm_object *)device->m; \
} break
switch (i) {
_(NVDEV_SUBDEV_BAR , bar);
......@@ -259,29 +2264,27 @@ nvkm_device_init(struct nvkm_device *device)
* subdev in turn as they're created.
*/
while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
struct nvkm_object *subdev = device->subdev[c++];
if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
ret = nvkm_object_inc(subdev);
if ((subdev = nvkm_device_subdev(device, c++))) {
ret = nvkm_subdev_init(subdev);
if (ret)
goto fail;
} else
if (subdev) {
nvkm_subdev_reset(subdev);
}
}
}
ret = 0;
nvkm_acpi_init(device);
time = ktime_to_us(ktime_get()) - time;
nvdev_trace(device, "init completed in %lldus\n", time);
return 0;
fail:
for (--i; ret && i >= 0; i--) {
if ((subdev = device->subdev[i])) {
if (!nv_iclass(subdev, NV_ENGINE_CLASS))
nvkm_object_dec(subdev, false);
}
}
do {
if ((subdev = nvkm_device_subdev(device, i)))
nvkm_subdev_fini(subdev, false);
} while (--i >= 0);
if (ret)
nvkm_acpi_fini(device, false);
nvdev_error(device, "init failed with %d\n", ret);
return ret;
}
......@@ -333,8 +2336,12 @@ nvkm_device_del(struct nvkm_device **pdevice)
int i;
if (device) {
mutex_lock(&nv_devices_mutex);
for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
nvkm_object_ref(NULL, &device->subdev[i]);
device->disable_mask = 0;
for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
struct nvkm_subdev *subdev =
nvkm_device_subdev(device, i);
nvkm_subdev_del(&subdev);
}
nvkm_event_fini(&device->event);
......@@ -363,6 +2370,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
bool detect, bool mmio, u64 subdev_mask,
struct nvkm_device *device)
{
struct nvkm_subdev *subdev;
u64 mmio_base, mmio_size;
u32 boot0, strap;
void __iomem *map;
......@@ -373,13 +2381,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
if (nvkm_device_find_locked(handle))
goto done;
ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
true, &device->engine);
device->engine.subdev.object.parent = NULL;
device->func = func;
if (ret)
goto done;
device->quirk = quirk;
switch (type) {
case NVKM_BUS_PCI:
......@@ -395,9 +2397,14 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
device->cfgopt = cfg;
device->dbgopt = dbg;
device->name = name;
list_add_tail(&device->head, &nv_devices);
ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0,
true, &device->engine);
device->engine.subdev.object.parent = NULL;
if (ret)
goto done;
ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event);
if (ret)
goto done;
......@@ -482,12 +2489,83 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
break;
}
if (ret) {
switch (!ret * device->chipset) {
case 0x004: device->chip = &nv4_chipset; break;
case 0x005: device->chip = &nv5_chipset; break;
case 0x010: device->chip = &nv10_chipset; break;
case 0x011: device->chip = &nv11_chipset; break;
case 0x015: device->chip = &nv15_chipset; break;
case 0x017: device->chip = &nv17_chipset; break;
case 0x018: device->chip = &nv18_chipset; break;
case 0x01a: device->chip = &nv1a_chipset; break;
case 0x01f: device->chip = &nv1f_chipset; break;
case 0x020: device->chip = &nv20_chipset; break;
case 0x025: device->chip = &nv25_chipset; break;
case 0x028: device->chip = &nv28_chipset; break;
case 0x02a: device->chip = &nv2a_chipset; break;
case 0x030: device->chip = &nv30_chipset; break;
case 0x031: device->chip = &nv31_chipset; break;
case 0x034: device->chip = &nv34_chipset; break;
case 0x035: device->chip = &nv35_chipset; break;
case 0x036: device->chip = &nv36_chipset; break;
case 0x040: device->chip = &nv40_chipset; break;
case 0x041: device->chip = &nv41_chipset; break;
case 0x042: device->chip = &nv42_chipset; break;
case 0x043: device->chip = &nv43_chipset; break;
case 0x044: device->chip = &nv44_chipset; break;
case 0x045: device->chip = &nv45_chipset; break;
case 0x046: device->chip = &nv46_chipset; break;
case 0x047: device->chip = &nv47_chipset; break;
case 0x049: device->chip = &nv49_chipset; break;
case 0x04a: device->chip = &nv4a_chipset; break;
case 0x04b: device->chip = &nv4b_chipset; break;
case 0x04c: device->chip = &nv4c_chipset; break;
case 0x04e: device->chip = &nv4e_chipset; break;
case 0x050: device->chip = &nv50_chipset; break;
case 0x063: device->chip = &nv63_chipset; break;
case 0x067: device->chip = &nv67_chipset; break;
case 0x068: device->chip = &nv68_chipset; break;
case 0x084: device->chip = &nv84_chipset; break;
case 0x086: device->chip = &nv86_chipset; break;
case 0x092: device->chip = &nv92_chipset; break;
case 0x094: device->chip = &nv94_chipset; break;
case 0x096: device->chip = &nv96_chipset; break;
case 0x098: device->chip = &nv98_chipset; break;
case 0x0a0: device->chip = &nva0_chipset; break;
case 0x0a3: device->chip = &nva3_chipset; break;
case 0x0a5: device->chip = &nva5_chipset; break;
case 0x0a8: device->chip = &nva8_chipset; break;
case 0x0aa: device->chip = &nvaa_chipset; break;
case 0x0ac: device->chip = &nvac_chipset; break;
case 0x0af: device->chip = &nvaf_chipset; break;
case 0x0c0: device->chip = &nvc0_chipset; break;
case 0x0c1: device->chip = &nvc1_chipset; break;
case 0x0c3: device->chip = &nvc3_chipset; break;
case 0x0c4: device->chip = &nvc4_chipset; break;
case 0x0c8: device->chip = &nvc8_chipset; break;
case 0x0ce: device->chip = &nvce_chipset; break;
case 0x0cf: device->chip = &nvcf_chipset; break;
case 0x0d7: device->chip = &nvd7_chipset; break;
case 0x0d9: device->chip = &nvd9_chipset; break;
case 0x0e4: device->chip = &nve4_chipset; break;
case 0x0e6: device->chip = &nve6_chipset; break;
case 0x0e7: device->chip = &nve7_chipset; break;
case 0x0ea: device->chip = &nvea_chipset; break;
case 0x0f0: device->chip = &nvf0_chipset; break;
case 0x0f1: device->chip = &nvf1_chipset; break;
case 0x106: device->chip = &nv106_chipset; break;
case 0x108: device->chip = &nv108_chipset; break;
case 0x117: device->chip = &nv117_chipset; break;
case 0x124: device->chip = &nv124_chipset; break;
case 0x126: device->chip = &nv126_chipset; break;
case 0x12b: device->chip = &nv12b_chipset; break;
default:
nvdev_error(device, "unknown chipset (%08x)\n", boot0);
goto done;
}
nvdev_info(device, "NVIDIA %s (%08x)\n", device->cname, boot0);
nvdev_info(device, "NVIDIA %s (%08x)\n",
device->chip->name, boot0);
/* determine frequency of timing crystal */
if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
......@@ -503,10 +2581,13 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case 0x00400040: device->crystal = 25000; break;
}
} else {
device->cname = "NULL";
device->chip = &null_chipset;
device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass;
}
if (!device->name)
device->name = device->chip->name;
if (mmio) {
device->pri = ioremap(mmio_base, mmio_size);
if (!device->pri) {
......@@ -523,6 +2604,72 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
atomic_set(&device->engine.subdev.object.usecount, 2);
mutex_init(&device->mutex);
for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
#define _(s,m) case s: \
if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \
ret = device->chip->m(device, (s), &device->m); \
if (ret) { \
subdev = nvkm_device_subdev(device, (s)); \
nvkm_subdev_del(&subdev); \
device->m = NULL; \
if (ret != -ENODEV) { \
nvdev_error(device, "%s ctor failed, %d\n", \
nvkm_subdev_name[s], ret); \
goto done; \
} \
} \
} \
break
switch (i) {
_(NVDEV_SUBDEV_BAR , bar);
_(NVDEV_SUBDEV_VBIOS , bios);
_(NVDEV_SUBDEV_BUS , bus);
_(NVDEV_SUBDEV_CLK , clk);
_(NVDEV_SUBDEV_DEVINIT, devinit);
_(NVDEV_SUBDEV_FB , fb);
_(NVDEV_SUBDEV_FUSE , fuse);
_(NVDEV_SUBDEV_GPIO , gpio);
_(NVDEV_SUBDEV_I2C , i2c);
_(NVDEV_SUBDEV_IBUS , ibus);
_(NVDEV_SUBDEV_INSTMEM, imem);
_(NVDEV_SUBDEV_LTC , ltc);
_(NVDEV_SUBDEV_MC , mc);
_(NVDEV_SUBDEV_MMU , mmu);
_(NVDEV_SUBDEV_MXM , mxm);
_(NVDEV_SUBDEV_PMU , pmu);
_(NVDEV_SUBDEV_THERM , therm);
_(NVDEV_SUBDEV_TIMER , timer);
_(NVDEV_SUBDEV_VOLT , volt);
_(NVDEV_ENGINE_BSP , bsp);
_(NVDEV_ENGINE_CE0 , ce[0]);
_(NVDEV_ENGINE_CE1 , ce[1]);
_(NVDEV_ENGINE_CE2 , ce[2]);
_(NVDEV_ENGINE_CIPHER , cipher);
_(NVDEV_ENGINE_DISP , disp);
_(NVDEV_ENGINE_DMAOBJ , dma);
_(NVDEV_ENGINE_FIFO , fifo);
_(NVDEV_ENGINE_GR , gr);
_(NVDEV_ENGINE_IFB , ifb);
_(NVDEV_ENGINE_ME , me);
_(NVDEV_ENGINE_MPEG , mpeg);
_(NVDEV_ENGINE_MSENC , msenc);
_(NVDEV_ENGINE_MSPDEC , mspdec);
_(NVDEV_ENGINE_MSPPP , msppp);
_(NVDEV_ENGINE_MSVLD , msvld);
_(NVDEV_ENGINE_PM , pm);
_(NVDEV_ENGINE_SEC , sec);
_(NVDEV_ENGINE_SW , sw);
_(NVDEV_ENGINE_VIC , vic);
_(NVDEV_ENGINE_VP , vp);
default:
WARN_ON(1);
continue;
}
#undef _
}
ret = 0;
done:
mutex_unlock(&nv_devices_mutex);
return ret;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View file @ 6cf813fb
......@@ -23,44 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mspdec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
int
gf100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xc0:
device->cname = "GF100";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -93,7 +60,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc4:
device->cname = "GF104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -126,7 +92,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc3:
device->cname = "GF106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -158,7 +123,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xce:
device->cname = "GF114";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -191,7 +155,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xcf:
device->cname = "GF116";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -223,7 +186,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xc1:
device->cname = "GF108";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -255,7 +217,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass;
break;
case 0xc8:
device->cname = "GF110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -288,7 +249,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass;
break;
case 0xd9:
device->cname = "GF119";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
......@@ -320,7 +280,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass;
break;
case 0xd7:
device->cname = "GF117";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View file @ 6cf813fb
......@@ -23,44 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
int
gk104_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0xe4:
device->cname = "GK104";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......@@ -94,7 +61,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe7:
device->cname = "GK107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......@@ -128,7 +94,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xe6:
device->cname = "GK106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......@@ -162,7 +127,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass;
break;
case 0xea:
device->cname = "GK20A";
device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
......@@ -184,7 +148,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass;
break;
case 0xf0:
device->cname = "GK110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......@@ -218,7 +181,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0xf1:
device->cname = "GK110B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
......@@ -252,7 +214,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass;
break;
case 0x106:
device->cname = "GK208B";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......@@ -285,7 +246,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
break;
case 0x108:
device->cname = "GK208";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View file @ 6cf813fb
......@@ -23,44 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltc.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
#include <engine/ce.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/pm.h>
int
gm100_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x117:
device->cname = "GM107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
......@@ -100,7 +67,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x124:
device->cname = "GM204";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
......@@ -141,7 +107,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x126:
device->cname = "GM206";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass;
......@@ -182,7 +147,6 @@ gm100_identify(struct nvkm_device *device)
#endif
break;
case 0x12b:
device->cname = "GM20B";
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View file @ 6cf813fb
......@@ -23,29 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
int
nv04_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x04:
device->cname = "NV04";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
......@@ -63,7 +45,6 @@ nv04_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x05:
device->cname = "NV05";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View file @ 6cf813fb
......@@ -23,30 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
int
nv10_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x10:
device->cname = "NV10";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -63,7 +44,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x15:
device->cname = "NV15";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -82,7 +62,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x16:
device->cname = "NV16";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -101,7 +80,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1a:
device->cname = "nForce";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -120,7 +98,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x11:
device->cname = "NV11";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -139,7 +116,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x17:
device->cname = "NV17";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -158,7 +134,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x1f:
device->cname = "nForce2";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -177,7 +152,6 @@ nv10_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x18:
device->cname = "NV18";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View file @ 6cf813fb
......@@ -23,31 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/disp.h>
int
nv20_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x20:
device->cname = "NV20";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -66,7 +46,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x25:
device->cname = "NV25";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -85,7 +64,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x28:
device->cname = "NV28";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -104,7 +82,6 @@ nv20_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x2a:
device->cname = "NV2A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View file @ 6cf813fb
......@@ -23,31 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
int
nv30_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x30:
device->cname = "NV30";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -66,7 +46,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x35:
device->cname = "NV35";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -85,7 +64,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x31:
device->cname = "NV31";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -105,7 +83,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x36:
device->cname = "NV36";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -125,7 +102,6 @@ nv30_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass;
break;
case 0x34:
device->cname = "NV34";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View file @ 6cf813fb
......@@ -23,35 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/mmu.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/volt.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
#include <engine/pm.h>
int
nv40_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x40:
device->cname = "NV40";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -74,7 +50,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x41:
device->cname = "NV41";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -97,7 +72,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x42:
device->cname = "NV42";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -120,7 +94,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x43:
device->cname = "NV43";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -143,7 +116,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x45:
device->cname = "NV45";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -166,7 +138,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x47:
device->cname = "G70";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -189,7 +160,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x49:
device->cname = "G71";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -212,7 +182,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4b:
device->cname = "G73";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -235,7 +204,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x44:
device->cname = "NV44";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -258,7 +226,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x46:
device->cname = "G72";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -281,7 +248,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4a:
device->cname = "NV44A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -304,7 +270,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4c:
device->cname = "C61";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -327,7 +292,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x4e:
device->cname = "C51";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
......@@ -350,7 +314,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x63:
device->cname = "C73";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -373,7 +336,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x67:
device->cname = "C67";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......@@ -396,7 +358,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass;
break;
case 0x68:
device->cname = "C68";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View file @ 6cf813fb
......@@ -23,46 +23,11 @@
*/
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/mmu.h>
#include <subdev/bar.h>
#include <subdev/pmu.h>
#include <subdev/volt.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/sw.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/vp.h>
#include <engine/cipher.h>
#include <engine/sec.h>
#include <engine/bsp.h>
#include <engine/msvld.h>
#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/ce.h>
#include <engine/disp.h>
#include <engine/pm.h>
int
nv50_identify(struct nvkm_device *device)
{
switch (device->chipset) {
case 0x50:
device->cname = "G80";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
......@@ -88,7 +53,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass;
break;
case 0x84:
device->cname = "G84";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
......@@ -117,7 +81,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x86:
device->cname = "G86";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
......@@ -146,7 +109,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x92:
device->cname = "G92";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
......@@ -175,7 +137,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x94:
device->cname = "G94";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -204,7 +165,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x96:
device->cname = "G96";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -233,7 +193,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0x98:
device->cname = "G98";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -262,7 +221,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa0:
device->cname = "G200";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
......@@ -291,7 +249,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -320,7 +277,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -349,7 +305,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass;
break;
case 0xa3:
device->cname = "GT215";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -380,7 +335,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa5:
device->cname = "GT216";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -410,7 +364,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xa8:
device->cname = "GT218";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......@@ -440,7 +393,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass;
break;
case 0xaf:
device->cname = "MCP89";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
......
drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h
View file @ 6cf813fb
......@@ -2,6 +2,42 @@
#define __NVKM_DEVICE_PRIV_H__
#include <core/device.h>
#include <subdev/bar.h>
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/fb.h>
#include <subdev/fuse.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/ibus.h>
#include <subdev/instmem.h>
#include <subdev/ltc.h>
#include <subdev/mc.h>
#include <subdev/mmu.h>
#include <subdev/mxm.h>
#include <subdev/pmu.h>
#include <subdev/therm.h>
#include <subdev/timer.h>
#include <subdev/volt.h>
#include <engine/bsp.h>
#include <engine/ce.h>
#include <engine/cipher.h>
#include <engine/disp.h>
#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/gr.h>
#include <engine/mpeg.h>
#include <engine/mspdec.h>
#include <engine/msppp.h>
#include <engine/msvld.h>
#include <engine/pm.h>
#include <engine/sec.h>
#include <engine/sw.h>
#include <engine/vp.h>
int nvkm_device_ctor(const struct nvkm_device_func *,
const struct nvkm_device_quirk *,
void *, enum nv_bus_type type, u64 handle,
......
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
View file @ 6cf813fb
......@@ -107,8 +107,8 @@ nvkm_udevice_info(struct nvkm_object *object, void *data, u32 size)
if (imem && args->v0.ram_size > 0)
args->v0.ram_user = args->v0.ram_user - imem->reserved;
strncpy(args->v0.chip, device->cname, sizeof(args->v0.chip));
strncpy(args->v0.name, device->cname, sizeof(args->v0.name));
strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip));
strncpy(args->v0.name, device->name, sizeof(args->v0.name));
return 0;
}
......
drivers/gpu/drm/nouveau/nvkm/engine/falcon.c
View file @ 6cf813fb
......@@ -138,7 +138,7 @@ _nvkm_falcon_init(struct nvkm_object *object)
ret = request_firmware(&fw, name, nv_device_base(device));
if (ret) {
nvkm_error(subdev, "unable to load firmware data\n");
return ret;
return -ENODEV;
}
falcon->data.data = vmemdup(fw->data, fw->size);
......@@ -153,7 +153,7 @@ _nvkm_falcon_init(struct nvkm_object *object)
ret = request_firmware(&fw, name, nv_device_base(device));
if (ret) {
nvkm_error(subdev, "unable to load firmware code\n");
return ret;
return -ENODEV;
}
falcon->code.data = vmemdup(fw->data, fw->size);
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View file @ 6cf813fb
......@@ -435,7 +435,7 @@ gf100_fifo_recover_work(struct work_struct *work)
{
struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault);
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_object *engine;
struct nvkm_engine *engine;
unsigned long flags;
u32 engn, engm = 0;
u64 mask, todo;
......@@ -450,9 +450,9 @@ gf100_fifo_recover_work(struct work_struct *work)
nvkm_mask(device, 0x002630, engm, engm);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
if ((engine = (void *)nvkm_engine(fifo, engn))) {
nvkm_object_fini(engine, false);
WARN_ON(nvkm_object_init(engine));
if ((engine = nvkm_device_engine(device, engn))) {
nvkm_subdev_fini(&engine->subdev, false);
WARN_ON(nvkm_subdev_init(&engine->subdev));
}
}
......
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View file @ 6cf813fb
......@@ -481,7 +481,7 @@ gk104_fifo_recover_work(struct work_struct *work)
{
struct gk104_fifo *fifo = container_of(work, typeof(*fifo), fault);
struct nvkm_device *device = fifo->base.engine.subdev.device;
struct nvkm_object *engine;
struct nvkm_engine *engine;
unsigned long flags;
u32 engn, engm = 0;
u64 mask, todo;
......@@ -496,9 +496,9 @@ gk104_fifo_recover_work(struct work_struct *work)
nvkm_mask(device, 0x002630, engm, engm);
for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
if ((engine = (void *)nvkm_engine(fifo, engn))) {
nvkm_object_fini(engine, false);
WARN_ON(nvkm_object_init(engine));
if ((engine = nvkm_device_engine(device, engn))) {
nvkm_subdev_fini(&engine->subdev, false);
WARN_ON(nvkm_subdev_init(&engine->subdev));
}
gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn));
}
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View file @ 6cf813fb
......@@ -1601,7 +1601,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
int i;
/* Convert device name to lowercase */
strncpy(cname, device->cname, sizeof(cname));
strncpy(cname, device->chip->name, sizeof(cname));
cname[sizeof(cname) - 1] = '\0';
i = strlen(cname);
while (i) {
......
drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c
View file @ 6cf813fb
......@@ -638,8 +638,8 @@ nvkm_perfctx_dtor(struct nvkm_object *object)
struct nvkm_pm *pm = (void *)object->engine;
struct nvkm_perfctx *ctx = (void *)object;
mutex_lock(&nv_subdev(pm)->mutex);
nvkm_gpuobj_destroy(&ctx->base);
mutex_lock(&nv_subdev(pm)->mutex);
if (pm->context == ctx)
pm->context = NULL;
mutex_unlock(&nv_subdev(pm)->mutex);
......
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c
View file @ 6cf813fb
......@@ -40,8 +40,8 @@ nv04_bus_intr(struct nvkm_subdev *subdev)
if (stat & 0x00000110) {
struct nvkm_gpio *gpio = device->gpio;
if (gpio && gpio->subdev.intr)
gpio->subdev.intr(&gpio->subdev);
if (gpio)
nvkm_subdev_intr(&gpio->subdev);
stat &= ~0x00000110;
nvkm_wr32(device, 0x001100, 0x00000110);
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c
View file @ 6cf813fb
......@@ -36,8 +36,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev)
if (gpio) {
struct nvkm_gpio *gpio = device->gpio;
if (gpio && gpio->subdev.intr)
gpio->subdev.intr(&gpio->subdev);
if (gpio)
nvkm_subdev_intr(&gpio->subdev);
}
if (stat & 0x00000008) { /* NV41- */
......@@ -54,8 +54,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev)
if (stat & 0x00070000) {
struct nvkm_therm *therm = device->therm;
if (therm && therm->subdev.intr)
therm->subdev.intr(&therm->subdev);
if (therm)
nvkm_subdev_intr(&therm->subdev);
stat &= ~0x00070000;
nvkm_wr32(device, 0x001100, 0x00070000);
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c
View file @ 6cf813fb
......@@ -69,8 +69,8 @@ nv50_bus_intr(struct nvkm_subdev *subdev)
if (stat & 0x00010000) {
struct nvkm_therm *therm = device->therm;
if (therm && therm->subdev.intr)
therm->subdev.intr(&therm->subdev);
if (therm)
nvkm_subdev_intr(&therm->subdev);
stat &= ~0x00010000;
nvkm_wr32(device, 0x001100, 0x00010000);
}
......
drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c
View file @ 6cf813fb
......@@ -65,8 +65,8 @@ nvkm_mc_intr(int irq, void *arg)
while (map->stat) {
if (intr & map->stat) {
unit = nvkm_subdev(mc, map->unit);
if (unit && unit->intr)
unit->intr(unit);
if (unit)
nvkm_subdev_intr(unit);
stat &= ~map->stat;
}
map++;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7