Commit 6d980c3e authored by Emil Tantilov's avatar Emil Tantilov Committed by Jeff Kirsher

ixgbe: Use function pointer for ixgbe_acquire/release_swfw_sync()

Change remaining direct calls to function pointers.
Signed-off-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Tested-by: default avatarEvan Swanson <evan.swanson@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 97322b33
...@@ -110,7 +110,6 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ...@@ -110,7 +110,6 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
&data_offset); &data_offset);
if (ret_val != 0) if (ret_val != 0)
goto setup_sfp_out; goto setup_sfp_out;
...@@ -130,7 +129,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) ...@@ -130,7 +129,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
} }
/* Release the semaphore */ /* Release the semaphore */
ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* /*
* Delay obtaining semaphore again to allow FW access, * Delay obtaining semaphore again to allow FW access,
* semaphore_delay is in ms usleep_range needs us. * semaphore_delay is in ms usleep_range needs us.
......
...@@ -1222,7 +1222,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1222,7 +1222,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
swfw_mask = IXGBE_GSSR_PHY0_SM; swfw_mask = IXGBE_GSSR_PHY0_SM;
do { do {
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
goto read_byte_out; goto read_byte_out;
} }
...@@ -1269,7 +1269,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1269,7 +1269,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
break; break;
fail: fail:
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
msleep(100); msleep(100);
ixgbe_i2c_bus_clear(hw); ixgbe_i2c_bus_clear(hw);
retry++; retry++;
...@@ -1280,7 +1280,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1280,7 +1280,7 @@ s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
} while (retry < max_retry); } while (retry < max_retry);
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
read_byte_out: read_byte_out:
return status; return status;
...@@ -1308,7 +1308,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1308,7 +1308,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
else else
swfw_mask = IXGBE_GSSR_PHY0_SM; swfw_mask = IXGBE_GSSR_PHY0_SM;
if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) { if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
goto write_byte_out; goto write_byte_out;
} }
...@@ -1352,7 +1352,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, ...@@ -1352,7 +1352,7 @@ s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
hw_dbg(hw, "I2C byte write error.\n"); hw_dbg(hw, "I2C byte write error.\n");
} while (retry < max_retry); } while (retry < max_retry);
ixgbe_release_swfw_sync(hw, swfw_mask); hw->mac.ops.release_swfw_sync(hw, swfw_mask);
write_byte_out: write_byte_out:
return status; return status;
......
...@@ -318,7 +318,7 @@ static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) ...@@ -318,7 +318,7 @@ static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
else else
status = IXGBE_ERR_SWFW_SYNC; status = IXGBE_ERR_SWFW_SYNC;
ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM); hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
return status; return status;
} }
......
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