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Commit 6f9af6fc authored by Adrian Bunk's avatar Adrian Bunk Committed by Linus Torvalds
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[PATCH] more comx removal 

The patch below removes the MAINTAINERS entry for the removed comx
driver.

Additionally, the following comx header files could be removed:
  drivers/net/wan/mixcom.h
  drivers/net/wan/hscx.h
  drivers/net/wan/munich32x.h
  drivers/net/wan/falc-lh.h

I've double-checked that none of them are used by any other driver.
parent 8fcb7c33
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MAINTAINERS
View file @ 6f9af6fc
...@@ -516,11 +516,6 @@ W: http://www.wittsend.com/computone.html ...@@ -516,11 +516,6 @@ W: http://www.wittsend.com/computone.html
L: linux-computone@lazuli.wittsend.com L: linux-computone@lazuli.wittsend.com
S: Supported S: Supported
COMX/MULTIGATE SYNC SERIAL DRIVERS
P: Pasztor Szilard
M: Pasztor Szilard <don@itc.hu>
S: Supported
COSA/SRP SYNC SERIAL DRIVER COSA/SRP SYNC SERIAL DRIVER
P: Jan "Yenya" Kasprzak P: Jan "Yenya" Kasprzak
M: kas@fi.muni.cz M: kas@fi.muni.cz
......
drivers/net/wan/falc-lh.h deleted 100644 → 0
View file @ 8fcb7c33
/*
* Defines for comx-hw-slicecom.c - FALC-LH specific
*
* Author: Bartok Istvan <bartoki@itc.hu>
* Last modified: Mon Feb 7 20:00:38 CET 2000
*
* :set tabstop=6
*/
/*
* Control register offsets on the LBI (page 90)
* use it like:
* lbi[ MODE ] = 0x34;
*/
#define MODE 0x03
#define IPC 0x08
#define IMR0 0x14 /* Interrupt Mask Register 0 */
#define IMR1 0x15
#define IMR2 0x16
#define IMR3 0x17
#define IMR4 0x18
#define IMR5 0x19
#define FMR0 0x1a /* Framer Mode Register 0 */
#define FMR1 0x1b
#define FMR2 0x1c
#define XSW 0x1e
#define XSP 0x1f
#define XC0 0x20
#define XC1 0x21
#define RC0 0x22
#define RC1 0x23
#define XPM0 0x24
#define XPM1 0x25
#define XPM2 0x26
#define TSWM 0x27
#define IDLE 0x29 /* Idle Code */
#define LIM0 0x34
#define LIM1 0x35
#define PCD 0x36
#define PCR 0x37
#define LIM2 0x38
/*
* Status registers on the LBI (page 134)
* these are read-only, use it like:
* if( lbi[ FRS0 ] ) ...
*/
#define FRS0 0x4c /* Framer Receive Status register 0 */
#define FRS1 0x4d /* Framer Receive Status register 1 */
#define FECL 0x50 /* Framing Error Counter low byte */ /* Counts FAS word receive errors */
#define FECH 0x51 /* high byte */
#define CVCL 0x52 /* Code Violation Counter low byte */ /* Counts bipolar and HDB3 code violations */
#define CVCH 0x53 /* high byte */
#define CEC1L 0x54 /* CRC4 Error Counter 1 low byte */ /* Counts CRC4 errors in the incoming stream */
#define CEC1H 0x55 /* high byte */
#define EBCL 0x56 /* E Bit error Counter low byte */ /* E-bits: the remote end sends them, when */
#define EBCH 0x57 /* high byte */ /* it detected a CRC4-error */
#define ISR0 0x68 /* Interrupt Status Register 0 */
#define ISR1 0x69 /* Interrupt Status Register 1 */
#define ISR2 0x6a /* Interrupt Status Register 2 */
#define ISR3 0x6b /* Interrupt Status Register 3 */
#define ISR5 0x6c /* Interrupt Status Register 5 */
#define GIS 0x6e /* Global Interrupt Status Register */
#define VSTR 0x6f /* version information */
/*
* Bit fields
*/
#define FRS0_LOS (1 << 7)
#define FRS0_AIS (1 << 6)
#define FRS0_LFA (1 << 5)
#define FRS0_RRA (1 << 4)
#define FRS0_AUXP (1 << 3)
#define FRS0_NMF (1 << 2)
#define FRS0_LMFA (1 << 1)
#define FRS1_XLS (1 << 1)
#define FRS1_XLO (1)
#define ISR2_FAR (1 << 7)
#define ISR2_LFA (1 << 6)
#define ISR2_MFAR (1 << 5)
#define ISR2_T400MS (1 << 4)
#define ISR2_AIS (1 << 3)
#define ISR2_LOS (1 << 2)
#define ISR2_RAR (1 << 1)
#define ISR2_RA (1)
#define ISR3_ES (1 << 7)
#define ISR3_SEC (1 << 6)
#define ISR3_LMFA16 (1 << 5)
#define ISR3_AIS16 (1 << 4)
#define ISR3_RA16 (1 << 3)
#define ISR3_API (1 << 2)
#define ISR3_RSN (1 << 1)
#define ISR3_RSP (1)
#define ISR5_XSP (1 << 7)
#define ISR5_XSN (1 << 6)
drivers/net/wan/hscx.h deleted 100644 → 0
View file @ 8fcb7c33
#define HSCX_MTU 1600
#define HSCX_ISTA 0x00
#define HSCX_MASK 0x00
#define HSCX_STAR 0x01
#define HSCX_CMDR 0x01
#define HSCX_MODE 0x02
#define HSCX_TIMR 0x03
#define HSCX_EXIR 0x04
#define HSCX_XAD1 0x04
#define HSCX_RBCL 0x05
#define HSCX_SAD2 0x05
#define HSCX_RAH1 0x06
#define HSCX_RSTA 0x07
#define HSCX_RAH2 0x07
#define HSCX_RAL1 0x08
#define HSCX_RCHR 0x09
#define HSCX_RAL2 0x09
#define HSCX_XBCL 0x0a
#define HSCX_BGR 0x0b
#define HSCX_CCR2 0x0c
#define HSCX_RBCH 0x0d
#define HSCX_XBCH 0x0d
#define HSCX_VSTR 0x0e
#define HSCX_RLCR 0x0e
#define HSCX_CCR1 0x0f
#define HSCX_FIFO 0x1e
#define HSCX_HSCX_CHOFFS 0x400
#define HSCX_SEROFFS 0x1000
#define HSCX_RME 0x80
#define HSCX_RPF 0x40
#define HSCX_RSC 0x20
#define HSCX_XPR 0x10
#define HSCX_TIN 0x08
#define HSCX_ICA 0x04
#define HSCX_EXA 0x02
#define HSCX_EXB 0x01
#define HSCX_XMR 0x80
#define HSCX_XDU 0x40
#define HSCX_EXE 0x40
#define HSCX_PCE 0x20
#define HSCX_RFO 0x10
#define HSCX_CSC 0x08
#define HSCX_RFS 0x04
#define HSCX_XDOV 0x80
#define HSCX_XFW 0x40
#define HSCX_XRNR 0x20
#define HSCX_RRNR 0x10
#define HSCX_RLI 0x08
#define HSCX_CEC 0x04
#define HSCX_CTS 0x02
#define HSCX_WFA 0x01
#define HSCX_RMC 0x80
#define HSCX_RHR 0x40
#define HSCX_RNR 0x20
#define HSCX_XREP 0x20
#define HSCX_STI 0x10
#define HSCX_XTF 0x08
#define HSCX_XIF 0x04
#define HSCX_XME 0x02
#define HSCX_XRES 0x01
#define HSCX_AUTO 0x00
#define HSCX_NONAUTO 0x40
#define HSCX_TRANS 0x80
#define HSCX_XTRANS 0xc0
#define HSCX_ADM16 0x20
#define HSCX_ADM8 0x00
#define HSCX_TMD_EXT 0x00
#define HSCX_TMD_INT 0x10
#define HSCX_RAC 0x08
#define HSCX_RTS 0x04
#define HSCX_TLP 0x01
#define HSCX_VFR 0x80
#define HSCX_RDO 0x40
#define HSCX_CRC 0x20
#define HSCX_RAB 0x10
#define HSCX_CIE 0x04
#define HSCX_RIE 0x02
#define HSCX_DMA 0x80
#define HSCX_NRM 0x40
#define HSCX_CAS 0x20
#define HSCX_XC 0x10
#define HSCX_OV 0x10
#define HSCX_CD 0x80
#define HSCX_RC 0x80
#define HSCX_PU 0x80
#define HSCX_NRZ 0x00
#define HSCX_NRZI 0x40
#define HSCX_ODS 0x10
#define HSCX_ITF 0x08
drivers/net/wan/mixcom.h deleted 100644 → 0
View file @ 8fcb7c33
/*
* Defines for the mixcom board
*
* Author: Gergely Madarasz <gorgo@itc.hu>
*
* Copyright (C) 1999 ITConsult-Pro Co. <info@itc.hu>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
*/
#define MIXCOM_IO_EXTENT 0x20
#define MIXCOM_DEFAULT_IO 0x180
#define MIXCOM_DEFAULT_IRQ 5
#define MIXCOM_ID 0x11
#define MIXCOM_SERIAL_OFFSET 0x1000
#define MIXCOM_CHANNEL_OFFSET 0x400
#define MIXCOM_IT_OFFSET 0xc14
#define MIXCOM_STATUS_OFFSET 0xc14
#define MIXCOM_ID_OFFSET 0xc10
#define MIXCOM_ON 0x1
#define MIXCOM_OFF 0x0
/* Status register bits */
#define MIXCOM_CTSB 0x1
#define MIXCOM_CTSA 0x2
#define MIXCOM_CHANNELNO 0x20
#define MIXCOM_POWERFAIL 0x40
#define MIXCOM_BOOT 0x80
drivers/net/wan/munich32x.h deleted 100644 → 0
View file @ 8fcb7c33
/*
* Defines for comx-hw-slicecom.c - MUNICH32X specific
*
* Author: Bartok Istvan <bartoki@itc.hu>
* Last modified: Tue Jan 11 14:27:36 CET 2000
*
* :set tabstop=6
*/
#define TXBUFFER_SIZE 1536 /* Max mennyit tud a kartya hardver atvenni */
#define RXBUFFER_SIZE (TXBUFFER_SIZE+4) /* For Rx reasons it must be a multiple of 4, and =>4 (page 265) */
/* +4 .. see page 265, bit FE */
/* TOD: a MODE1-be nem is ezt teszem, hanem a TXBUFFER-t, lehet hogy nem is kell? */
//#define PCI_VENDOR_ID_SIEMENS 0x110a
#define PCI_DEVICE_ID_SIEMENS_MUNICH32X 0x2101
/*
* PCI config space registers (page 120)
*/
#define MUNICH_PCI_PCIRES 0x4c /* 0xe0000 resets the chip */
/*
* MUNICH slave register offsets relative to base_address[0] (PCI BAR1) (page 181):
* offsets are in bytes, registers are u32's, so we need a >>2 for indexing
* the int[] by byte offsets. Use it like:
*
* bar1[ STAT ] = ~0L; or
* x = bar1[ STAT ];
*/
#define CONF (0x00 >> 2)
#define CMD (0x04 >> 2)
#define STAT (0x08 >> 2)
#define STACK (0x08 >> 2)
#define IMASK (0x0c >> 2)
#define PIQBA (0x14 >> 2)
#define PIQL (0x18 >> 2)
#define MODE1 (0x20 >> 2)
#define MODE2 (0x24 >> 2)
#define CCBA (0x28 >> 2)
#define TXPOLL (0x2c >> 2)
#define TIQBA (0x30 >> 2)
#define TIQL (0x34 >> 2)
#define RIQBA (0x38 >> 2)
#define RIQL (0x3c >> 2)
#define LCONF (0x40 >> 2) /* LBI Configuration Register */
#define LCCBA (0x44 >> 2) /* LBI Configuration Control Block */ /* DE: lehet hogy nem is kell? */
#define LTIQBA (0x50 >> 2) /* DE: lehet hogy nem is kell? page 210: LBI DMA Controller intq - nem hasznalunk DMA-t.. */
#define LTIQL (0x54 >> 2) /* DE: lehet hogy nem is kell? */
#define LRIQBA (0x58 >> 2) /* DE: lehet hogy nem is kell? */
#define LRIQL (0x5c >> 2) /* DE: lehet hogy nem is kell? */
#define LREG0 (0x60 >> 2) /* LBI Indirect External Configuration register 0 */
#define LREG1 (0x64 >> 2)
#define LREG2 (0x68 >> 2)
#define LREG3 (0x6c >> 2)
#define LREG4 (0x70 >> 2)
#define LREG5 (0x74 >> 2)
#define LREG6 (0x78 >> 2) /* LBI Indirect External Configuration register 6 */
#define LSTAT (0x7c >> 2) /* LBI Status Register */
#define GPDIR (0x80 >> 2) /* General Purpose Bus DIRection - 0..input, 1..output */
#define GPDATA (0x84 >> 2) /* General Purpose Bus DATA */
/*
* MUNICH commands: (they go into register CMD)
*/
#define CMD_ARPCM 0x01 /* Action Request Serial PCM Core */
#define CMD_ARLBI 0x02 /* Action Request LBI */
/*
* MUNICH event bits in the STAT, STACK, IMASK registers (page 188,189)
*/
#define STAT_PTI (1 << 15)
#define STAT_PRI (1 << 14)
#define STAT_LTI (1 << 13)
#define STAT_LRI (1 << 12)
#define STAT_IOMI (1 << 11)
#define STAT_SSCI (1 << 10)
#define STAT_LBII (1 << 9)
#define STAT_MBI (1 << 8)
#define STAT_TI (1 << 6)
#define STAT_TSPA (1 << 5)
#define STAT_RSPA (1 << 4)
#define STAT_LBIF (1 << 3)
#define STAT_LBIA (1 << 2)
#define STAT_PCMF (1 << 1)
#define STAT_PCMA (1)
/*
* We do not handle these (and do not touch their STAT bits) in the interrupt loop
*/
#define STAT_NOT_HANDLED_BY_INTERRUPT (STAT_PCMF | STAT_PCMA)
/*
* MUNICH MODE1/MODE2 slave register fields (page 193,196)
* these are not all masks, MODE1_XX_YY are my magic values!
*/
#define MODE1_PCM_E1 (1 << 31) /* E1, 2.048 Mbit/sec */
#define MODE1_TBS_4 (1 << 24) /* TBS = 4 .. no Tx bit shift */
#define MODE1_RBS_4 (1 << 18) /* RBS = 4 .. no Rx bit shift */
#define MODE1_REN (1 << 15) /* Rx Enable */
#define MODE1_MFL_MY TXBUFFER_SIZE /* Maximum Frame Length */
#define MODE1_MAGIC (MODE1_PCM_E1 | MODE1_TBS_4 | MODE1_RBS_4 | MODE1_REN | MODE1_MFL_MY)
#define MODE2_HPOLL (1 << 8) /* Hold Poll */
#define MODE2_SPOLL (1 << 7) /* Slow Poll */
#define MODE2_TSF (1) /* real magic - discovered by probing :) */
// #define MODE2_MAGIC (MODE2_TSF)
#define MODE2_MAGIC (MODE2_SPOLL | MODE2_TSF)
/*
* LCONF bits (page 205)
* these are not all masks, LCONF_XX_YY are my magic values!
*/
#define LCONF_IPA (1 << 31) /* Interrupt Pass. Use 1 for FALC54 */
#define LCONF_DCA (1 << 30) /* Disregard the int's for Channel A - DMSM does not try to handle them */
#define LCONF_DCB (1 << 29) /* Disregard the int's for Channel B */
#define LCONF_EBCRES (1 << 22) /* Reset LBI External Bus Controller, 0..reset, 1..normal operation */
#define LCONF_LBIRES (1 << 21) /* Reset LBI DMSM, 0..reset, 1..normal operation */
#define LCONF_BTYP_16DEMUX (1 << 7) /* 16-bit demultiplexed bus */
#define LCONF_ABM (1 << 4) /* Arbitration Master */
/* writing LCONF_MAGIC1 followed by a LCONF_MAGIC2 into LCONF resets the EBC and DMSM: */
#define LCONF_MAGIC1 (LCONF_BTYP_16DEMUX | LCONF_ABM | LCONF_IPA | LCONF_DCA | LCONF_DCB)
#define LCONF_MAGIC2 (LCONF_MAGIC1 | LCONF_EBCRES | LCONF_LBIRES)
/*
* LREGx magic values if a FALC54 is on the LBI (page 217)
*/
#define LREG0_MAGIC 0x00000264
#define LREG1_MAGIC 0x6e6a6b66
#define LREG2_MAGIC 0x00000264
#define LREG3_MAGIC 0x6e686966
#define LREG4_MAGIC 0x00000000
#define LREG5_MAGIC ( (7<<27) | (3<<24) | (1<<21) | (7<<3) | (2<<9) )
/*
* PCM Action Specification fields (munich_ccb_t.action_spec)
*/
#define CCB_ACTIONSPEC_IN (1 << 15) /* init */
#define CCB_ACTIONSPEC_ICO (1 << 14) /* init only this channel */
#define CCB_ACTIONSPEC_RES (1 << 6) /* reset all channels */
#define CCB_ACTIONSPEC_LOC (1 << 5)
#define CCB_ACTIONSPEC_LOOP (1 << 4)
#define CCB_ACTIONSPEC_LOOPI (1 << 3)
#define CCB_ACTIONSPEC_IA (1 << 2)
/*
* Interrupt Information bits in the TIQ, RIQ
*/
#define PCM_INT_HI (1 << 12)
#define PCM_INT_FI (1 << 11)
#define PCM_INT_IFC (1 << 10)
#define PCM_INT_SF (1 << 9)
#define PCM_INT_ERR (1 << 8)
#define PCM_INT_FO (1 << 7)
#define PCM_INT_FE2 (1 << 6)
#define PCM_INT_CHANNEL( info ) (info & 0x1F)
/*
* Rx status info in the rx_desc_t.status
*/
#define RX_STATUS_SF (1 << 6)
#define RX_STATUS_LOSS (1 << 5)
#define RX_STATUS_CRCO (1 << 4)
#define RX_STATUS_NOB (1 << 3)
#define RX_STATUS_LFD (1 << 2)
#define RX_STATUS_RA (1 << 1)
#define RX_STATUS_ROF 1
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