staging: sm750fb: use BIT macro for PANEL_DISPLAY_CTRL single-bit fields

Replace complex definition of PANEL_DISPLAY_CTRL register fields with BIT()
macro and use open-coded implementation for register manipulations.
Signed-off-by: Mike Rapoport <mike.rapoport@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/sm750fb/ddk750_chip.c

@@ -249,17 +249,17 @@ int ddk750_initHw(initchip_param_t *pInitParam)
 
 		/* Disable Overlay, if a former application left it on */
 		reg = PEEK32(VIDEO_DISPLAY_CTRL);
-		reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+		reg &= ~DISPLAY_CTRL_PLANE;
 		POKE32(VIDEO_DISPLAY_CTRL, reg);
 
 		/* Disable video alpha, if a former application left it on */
 		reg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL);
-		reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+		reg &= ~DISPLAY_CTRL_PLANE;
 		POKE32(VIDEO_ALPHA_DISPLAY_CTRL, reg);
 
 		/* Disable alpha plane, if a former application left it on */
 		reg = PEEK32(ALPHA_DISPLAY_CTRL);
-		reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+		reg &= ~DISPLAY_CTRL_PLANE;
 		POKE32(ALPHA_DISPLAY_CTRL, reg);
 
 		/* Disable DMA Channel, if a former application left it on */

drivers/staging/sm750fb/ddk750_display.c

@@ -28,10 +28,10 @@ static void setDisplayControl(int ctrl, int disp_state)
 		 * guarantee that the plane will also enabled or
 		 * disabled.
 		 */
-		val = FIELD_SET(val, DISPLAY_CTRL, TIMING, ENABLE);
+		val |= DISPLAY_CTRL_TIMING;
 		POKE32(reg, val);
 
-		val = FIELD_SET(val, DISPLAY_CTRL, PLANE, ENABLE);
+		val |= DISPLAY_CTRL_PLANE;
 
 		/*
 		 * Somehow the register value on the plane is not set
@@ -53,10 +53,10 @@ static void setDisplayControl(int ctrl, int disp_state)
 		 * find out if it is necessary to wait for 1 vsync
 		 * before modifying the timing enable bit.
 		 */
-		val = FIELD_SET(val, DISPLAY_CTRL, PLANE, DISABLE);
+		val &= ~DISPLAY_CTRL_PLANE;
 		POKE32(reg, val);
 
-		val = FIELD_SET(val, DISPLAY_CTRL, TIMING, DISABLE);
+		val &= ~DISPLAY_CTRL_TIMING;
 		POKE32(reg, val);
 	}
 }
@@ -71,9 +71,7 @@ static void waitNextVerticalSync(int ctrl, int delay)
 		/* Do not wait when the Primary PLL is off or display control is already off.
 		   This will prevent the software to wait forever. */
 		if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
-			(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL),
-				DISPLAY_CTRL, TIMING) ==
-				DISPLAY_CTRL_TIMING_DISABLE)) {
+		    !(PEEK32(PANEL_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
 			return;
 		}
 
@@ -94,9 +92,7 @@ static void waitNextVerticalSync(int ctrl, int delay)
 		/* Do not wait when the Primary PLL is off or display control is already off.
 			   This will prevent the software to wait forever. */
 		if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
-			(FIELD_GET(PEEK32(CRT_DISPLAY_CTRL),
-				DISPLAY_CTRL, TIMING) ==
-				DISPLAY_CTRL_TIMING_DISABLE)) {
+		    !(PEEK32(CRT_DISPLAY_CTRL) & DISPLAY_CTRL_TIMING)) {
 			return;
 		}
 
@@ -120,22 +116,22 @@ static void swPanelPowerSequence(int disp, int delay)
 
 	/* disp should be 1 to open sequence */
 	reg = PEEK32(PANEL_DISPLAY_CTRL);
-	reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
+	reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
 	POKE32(PANEL_DISPLAY_CTRL, reg);
 	primaryWaitVerticalSync(delay);
 
 	reg = PEEK32(PANEL_DISPLAY_CTRL);
-	reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, DATA, disp);
+	reg |= (disp ? PANEL_DISPLAY_CTRL_DATA : 0);
 	POKE32(PANEL_DISPLAY_CTRL, reg);
 	primaryWaitVerticalSync(delay);
 
 	reg = PEEK32(PANEL_DISPLAY_CTRL);
-	reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, VBIASEN, disp);
+	reg |= (disp ? PANEL_DISPLAY_CTRL_VBIASEN : 0);
 	POKE32(PANEL_DISPLAY_CTRL, reg);
 	primaryWaitVerticalSync(delay);
 
 	reg = PEEK32(PANEL_DISPLAY_CTRL);
-	reg = FIELD_VALUE(reg, PANEL_DISPLAY_CTRL, FPEN, disp);
+	reg |= (disp ? PANEL_DISPLAY_CTRL_FPEN : 0);
 	POKE32(PANEL_DISPLAY_CTRL, reg);
 	primaryWaitVerticalSync(delay);
 

drivers/staging/sm750fb/ddk750_mode.c

@@ -65,8 +65,7 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
 	dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT);
 
 	/* Set bit 14 of display controller */
-	dispControl = FIELD_SET(dispControl, DISPLAY_CTRL, CLOCK_PHASE,
-				ACTIVE_LOW);
+	dispControl = DISPLAY_CTRL_CLOCK_PHASE;
 
 	POKE32(CRT_DISPLAY_CTRL, dispControl);
 
@@ -102,22 +101,19 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
 		| FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
 
 
-		tmp = FIELD_VALUE(0, DISPLAY_CTRL, VSYNC_PHASE,
-				  pModeParam->vertical_sync_polarity) |
-			FIELD_VALUE(0, DISPLAY_CTRL, HSYNC_PHASE,
-				    pModeParam->horizontal_sync_polarity) |
-			FIELD_SET(0, DISPLAY_CTRL, TIMING, ENABLE) |
-			FIELD_SET(0, DISPLAY_CTRL, PLANE, ENABLE);
-
+		tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
+		if (pModeParam->vertical_sync_polarity)
+			tmp |= DISPLAY_CTRL_VSYNC_PHASE;
+		if (pModeParam->horizontal_sync_polarity)
+			tmp |= DISPLAY_CTRL_HSYNC_PHASE;
 
 		if (getChipType() == SM750LE) {
 			displayControlAdjust_SM750LE(pModeParam, tmp);
 		} else {
-			reg = PEEK32(CRT_DISPLAY_CTRL)
-				& FIELD_CLEAR(DISPLAY_CTRL, VSYNC_PHASE)
-				& FIELD_CLEAR(DISPLAY_CTRL, HSYNC_PHASE)
-				& FIELD_CLEAR(DISPLAY_CTRL, TIMING)
-				& FIELD_CLEAR(DISPLAY_CTRL, PLANE);
+			reg = PEEK32(CRT_DISPLAY_CTRL) &
+				~(DISPLAY_CTRL_VSYNC_PHASE |
+				  DISPLAY_CTRL_HSYNC_PHASE |
+				  DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE);
 
 			 POKE32(CRT_DISPLAY_CTRL, tmp | reg);
 		}
@@ -143,25 +139,21 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
 		FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
 		| FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
 
-		tmp = FIELD_VALUE(0, DISPLAY_CTRL, VSYNC_PHASE,
-				  pModeParam->vertical_sync_polarity) |
-			FIELD_VALUE(0, DISPLAY_CTRL, HSYNC_PHASE,
-				    pModeParam->horizontal_sync_polarity) |
-			FIELD_VALUE(0, DISPLAY_CTRL, CLOCK_PHASE,
-                                     pModeParam->clock_phase_polarity) |
-			FIELD_SET(0, DISPLAY_CTRL, TIMING, ENABLE) |
-			FIELD_SET(0, DISPLAY_CTRL, PLANE, ENABLE);
+		tmp = DISPLAY_CTRL_TIMING | DISPLAY_CTRL_PLANE;
+		if (pModeParam->vertical_sync_polarity)
+			tmp |= DISPLAY_CTRL_VSYNC_PHASE;
+		if (pModeParam->horizontal_sync_polarity)
+			tmp |= DISPLAY_CTRL_HSYNC_PHASE;
+		if (pModeParam->clock_phase_polarity)
+			tmp |= DISPLAY_CTRL_CLOCK_PHASE;
 
 		reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK |
-			FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW);
-
-		reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved)
-			& FIELD_CLEAR(DISPLAY_CTRL, CLOCK_PHASE)
-			& FIELD_CLEAR(DISPLAY_CTRL, VSYNC_PHASE)
-			& FIELD_CLEAR(DISPLAY_CTRL, HSYNC_PHASE)
-			& FIELD_CLEAR(DISPLAY_CTRL, TIMING)
-			& FIELD_CLEAR(DISPLAY_CTRL, PLANE);
+			PANEL_DISPLAY_CTRL_VSYNC;
 
+		reg = (PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) &
+			~(DISPLAY_CTRL_CLOCK_PHASE | DISPLAY_CTRL_VSYNC_PHASE |
+			  DISPLAY_CTRL_HSYNC_PHASE | DISPLAY_CTRL_TIMING |
+			  DISPLAY_CTRL_PLANE);
 
 		/* May a hardware bug or just my test chip (not confirmed).
 		* PANEL_DISPLAY_CTRL register seems requiring few writes

drivers/staging/sm750fb/ddk750_reg.h

@@ -787,75 +787,36 @@
 #define PANEL_DISPLAY_CTRL_SELECT_PANEL               0
 #define PANEL_DISPLAY_CTRL_SELECT_VGA                 1
 #define PANEL_DISPLAY_CTRL_SELECT_CRT                 2
-#define PANEL_DISPLAY_CTRL_FPEN                       27:27
-#define PANEL_DISPLAY_CTRL_FPEN_LOW                   0
-#define PANEL_DISPLAY_CTRL_FPEN_HIGH                  1
-#define PANEL_DISPLAY_CTRL_VBIASEN                    26:26
-#define PANEL_DISPLAY_CTRL_VBIASEN_LOW                0
-#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH               1
-#define PANEL_DISPLAY_CTRL_DATA                       25:25
-#define PANEL_DISPLAY_CTRL_DATA_DISABLE               0
-#define PANEL_DISPLAY_CTRL_DATA_ENABLE                1
-#define PANEL_DISPLAY_CTRL_FPVDDEN                    24:24
-#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW                0
-#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH               1
+#define PANEL_DISPLAY_CTRL_FPEN                       BIT(27)
+#define PANEL_DISPLAY_CTRL_VBIASEN                    BIT(26)
+#define PANEL_DISPLAY_CTRL_DATA                       BIT(25)
+#define PANEL_DISPLAY_CTRL_FPVDDEN                    BIT(24)
 
 #define PANEL_DISPLAY_CTRL_TFT_DISP 19:18
 #define PANEL_DISPLAY_CTRL_TFT_DISP_24 0
 #define PANEL_DISPLAY_CTRL_TFT_DISP_36 1
 #define PANEL_DISPLAY_CTRL_TFT_DISP_18 2
 
-
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY               19:19
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE       0
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE        1
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL               18:18
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE       0
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE        1
+#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY               BIT(19)
+#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL               BIT(18)
 #define PANEL_DISPLAY_CTRL_FIFO                       17:16
 #define PANEL_DISPLAY_CTRL_FIFO_1                     0
 #define PANEL_DISPLAY_CTRL_FIFO_3                     1
 #define PANEL_DISPLAY_CTRL_FIFO_7                     2
 #define PANEL_DISPLAY_CTRL_FIFO_11                    3
-#define DISPLAY_CTRL_CLOCK_PHASE                      14:14
-#define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH          0
-#define DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW           1
-#define DISPLAY_CTRL_VSYNC_PHASE                      13:13
-#define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH          0
-#define DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW           1
-#define DISPLAY_CTRL_HSYNC_PHASE                      12:12
-#define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH          0
-#define DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW           1
-#define PANEL_DISPLAY_CTRL_VSYNC                      11:11
-#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH          0
-#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW           1
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING             10:10
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE     0
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE      1
-#define PANEL_DISPLAY_CTRL_COLOR_KEY                  9:9
-#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE          0
-#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE           1
-#define DISPLAY_CTRL_TIMING                           8:8
-#define DISPLAY_CTRL_TIMING_DISABLE                   0
-#define DISPLAY_CTRL_TIMING_ENABLE                    1
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR           7:7
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN      0
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP        1
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN               6:6
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE       0
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE        1
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR         5:5
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT   0
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT    1
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN             4:4
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE     0
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE      1
-#define DISPLAY_CTRL_GAMMA                            3:3
-#define DISPLAY_CTRL_GAMMA_DISABLE                    0
-#define DISPLAY_CTRL_GAMMA_ENABLE                     1
-#define DISPLAY_CTRL_PLANE                            2:2
-#define DISPLAY_CTRL_PLANE_DISABLE                    0
-#define DISPLAY_CTRL_PLANE_ENABLE                     1
+#define DISPLAY_CTRL_CLOCK_PHASE                      BIT(14)
+#define DISPLAY_CTRL_VSYNC_PHASE                      BIT(13)
+#define DISPLAY_CTRL_HSYNC_PHASE                      BIT(12)
+#define PANEL_DISPLAY_CTRL_VSYNC                      BIT(11)
+#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING             BIT(10)
+#define PANEL_DISPLAY_CTRL_COLOR_KEY                  BIT(9)
+#define DISPLAY_CTRL_TIMING                           BIT(8)
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR           BIT(7)
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN               BIT(6)
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR         BIT(5)
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN             BIT(4)
+#define DISPLAY_CTRL_GAMMA                            BIT(3)
+#define DISPLAY_CTRL_PLANE                            BIT(2)
 #define PANEL_DISPLAY_CTRL_FORMAT                     1:0
 #define PANEL_DISPLAY_CTRL_FORMAT_8                   0
 #define PANEL_DISPLAY_CTRL_FORMAT_16                  1

drivers/staging/sm750fb/sm750_hw.c

@@ -416,28 +416,24 @@ int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
 	case FB_BLANK_UNBLANK:
 		pr_debug("flag = FB_BLANK_UNBLANK\n");
 		dpms = SYSTEM_CTRL_DPMS_VPHP;
-		pps = PANEL_DISPLAY_CTRL_DATA_ENABLE;
+		pps = PANEL_DISPLAY_CTRL_DATA;
 		crtdb = CRT_DISPLAY_CTRL_BLANK_OFF;
 		break;
 	case FB_BLANK_NORMAL:
 		pr_debug("flag = FB_BLANK_NORMAL\n");
 		dpms = SYSTEM_CTRL_DPMS_VPHP;
-		pps = PANEL_DISPLAY_CTRL_DATA_DISABLE;
 		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;
 		break;
 	case FB_BLANK_VSYNC_SUSPEND:
 		dpms = SYSTEM_CTRL_DPMS_VNHP;
-		pps = PANEL_DISPLAY_CTRL_DATA_DISABLE;
 		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;
 		break;
 	case FB_BLANK_HSYNC_SUSPEND:
 		dpms = SYSTEM_CTRL_DPMS_VPHN;
-		pps = PANEL_DISPLAY_CTRL_DATA_DISABLE;
 		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;
 		break;
 	case FB_BLANK_POWERDOWN:
 		dpms = SYSTEM_CTRL_DPMS_VNHN;
-		pps = PANEL_DISPLAY_CTRL_DATA_DISABLE;
 		crtdb = CRT_DISPLAY_CTRL_BLANK_ON;
 		break;
 	}
@@ -449,8 +445,13 @@ int hw_sm750_setBLANK(struct lynxfb_output *output, int blank)
 		POKE32(CRT_DISPLAY_CTRL, FIELD_VALUE(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, BLANK, crtdb));
 	}
 
-	if (output->paths & sm750_panel)
-		POKE32(PANEL_DISPLAY_CTRL, FIELD_VALUE(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, DATA, pps));
+	if (output->paths & sm750_panel) {
+		unsigned int val = PEEK32(PANEL_DISPLAY_CTRL);
+
+		val &= ~PANEL_DISPLAY_CTRL_DATA;
+		val |= pps;
+		POKE32(PANEL_DISPLAY_CTRL, val);
+	}
 
 	return 0;
 }