Commit 71b6c4a2 authored by yipechai's avatar yipechai Committed by Alex Deucher

drm/amdgpu: Fix the code style warnings in hdp xgmi mca and umc

drm/amdgpu: Fix the code style warnings in hdp xgmi mca and umc:
1. WARNING: missing space after struct definition.
2. WARNING: please, no space before tabs.
3. WARNING: line length of xxx exceeds 100 columns.
4. ERROR: "foo* bar" should be "foo *bar".
5. ERROR: space required before the open parenthesis '('.
6. ERROR: space prohibited after that open parenthesis '('.
Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8697a19e
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
#define __AMDGPU_HDP_H__ #define __AMDGPU_HDP_H__
#include "amdgpu_ras.h" #include "amdgpu_ras.h"
struct amdgpu_hdp_ras{ struct amdgpu_hdp_ras {
struct amdgpu_ras_block_object ras_block; struct amdgpu_ras_block_object ras_block;
}; };
......
...@@ -950,7 +950,8 @@ static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, ...@@ -950,7 +950,8 @@ static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, void *inject_if) static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, void *inject_if)
{ {
int ret = 0; int ret = 0;
struct ta_ras_trigger_error_input *block_info = (struct ta_ras_trigger_error_input *)inject_if; struct ta_ras_trigger_error_input *block_info =
(struct ta_ras_trigger_error_input *)inject_if;
if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))
dev_warn(adev->dev, "Failed to disallow df cstate"); dev_warn(adev->dev, "Failed to disallow df cstate");
......
...@@ -47,12 +47,13 @@ static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev) ...@@ -47,12 +47,13 @@ static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
amdgpu_mca_ras_fini(adev, &adev->mca.mp0); amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
} }
static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object* block_obj, enum amdgpu_ras_block block, uint32_t sub_block_index) static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
enum amdgpu_ras_block block, uint32_t sub_block_index)
{ {
if(!block_obj) if (!block_obj)
return -EINVAL; return -EINVAL;
if( (block_obj->block == block) && if ((block_obj->block == block) &&
(block_obj->sub_block_index == sub_block_index)) { (block_obj->sub_block_index == sub_block_index)) {
return 0; return 0;
} }
......
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