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Commit 722a9fa5 authored by Reeja John's avatar Reeja John Committed by Jeff Garzik
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[netdrvr amd8111e] interrupt coalescing, libmii, bug fixes 

* Dynamic interrupt coalescing
* mii lib support
* dynamic IPG support (disabled by default)
* jumbo frame fix
* vlan fix
* rx irq coalescing fix
parent 3216cf39
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Showing with 1173 additions and 832 deletions
drivers/net/amd8111e.c
View file @ 722a9fa5
/* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
* Copyright (C) 2002 Advanced Micro Devices
* Copyright (C) 2003 Advanced Micro Devices
*
*
* Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
......@@ -41,6 +41,18 @@ Module Name:
Kernel Mode
Revision History:
3.0.0
Initial Revision.
3.0.1
1. Dynamic interrupt coalescing.
2. Removed prev_stats.
3. MII support.
4. Dynamic IPG support
3.0.2 05/29/2003
1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
2. Bug fix: Fixed VLAN support failure.
3. Bug fix: Fixed receive interrupt coalescing bug.
4. Dynamic IPG support is disabled by default.
*/
......@@ -77,13 +89,16 @@ Revision History:
#include "amd8111e.h"
#define MODULE_NAME "amd8111e"
#define MODULE_VERSION "3.0.0"
#define MODULE_VERSION "3.0.2"
MODULE_AUTHOR("Advanced Micro Devices, Inc.");
MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.0");
MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.2");
MODULE_LICENSE("GPL");
MODULE_PARM(speed_duplex, "1-" __MODULE_STRING (MAX_UNITS) "i");
MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
MODULE_PARM(coalesce, "1-" __MODULE_STRING(MAX_UNITS) "i");
MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
MODULE_PARM(dynamic_ipg, "1-" __MODULE_STRING(MAX_UNITS) "i");
MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
static struct pci_device_id amd8111e_pci_tbl[] __devinitdata = {
......@@ -92,6 +107,88 @@ static struct pci_device_id amd8111e_pci_tbl[] __devinitdata = {
{ 0, }
};
/*
This function will read the PHY registers.
*/
static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
{
void * mmio = lp->mmio;
unsigned int reg_val;
unsigned int repeat= REPEAT_CNT;
reg_val = readl(mmio + PHY_ACCESS);
while (reg_val & PHY_CMD_ACTIVE)
reg_val = readl( mmio + PHY_ACCESS );
writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
((reg & 0x1f) << 16), mmio +PHY_ACCESS);
do{
reg_val = readl(mmio + PHY_ACCESS);
udelay(30); /* It takes 30 us to read/write data */
} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
if(reg_val & PHY_RD_ERR)
goto err_phy_read;
*val = reg_val & 0xffff;
return 0;
err_phy_read:
*val = 0;
return -EINVAL;
}
/*
This function will write into PHY registers.
*/
static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
{
unsigned int repeat = REPEAT_CNT
void * mmio = lp->mmio;
unsigned int reg_val;
reg_val = readl(mmio + PHY_ACCESS);
while (reg_val & PHY_CMD_ACTIVE)
reg_val = readl( mmio + PHY_ACCESS );
writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
do{
reg_val = readl(mmio + PHY_ACCESS);
udelay(30); /* It takes 30 us to read/write the data */
} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
if(reg_val & PHY_RD_ERR)
goto err_phy_write;
return 0;
err_phy_write:
return -EINVAL;
}
/*
This is the mii register read function provided to the mii interface.
*/
static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
{
struct amd8111e_priv* lp = dev->priv;
unsigned int reg_val;
amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
return reg_val;
}
/*
This is the mii register write function provided to the mii interface.
*/
static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
{
struct amd8111e_priv* lp = dev->priv;
amd8111e_write_phy(lp, phy_id, reg_num, val);
}
/*
This function will set PHY speed. During initialization sets the original speed to 100 full.
......@@ -99,26 +196,39 @@ This function will set PHY speed. During initialization sets the original speed
static void amd8111e_set_ext_phy(struct net_device *dev)
{
struct amd8111e_priv *lp = (struct amd8111e_priv *)dev->priv;
unsigned long reg_val = 0;
void * mmio = lp->mmio;
struct amd8111e_link_config *link_config = &lp->link_config;
u32 bmcr,advert,tmp;
if(!lp->opened){
/* Initializing SPEED_100 and DUPLEX_FULL as original values */
link_config->orig_speed = SPEED_100;
link_config->orig_duplex = DUPLEX_FULL;
link_config->orig_phy_option = XPHYSP |XPHYFD;
/* Determine mii register values to set the speed */
advert = amd8111e_mdio_read(dev, PHY_ID, MII_ADVERTISE);
tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
switch (lp->ext_phy_option){
default:
case SPEED_AUTONEG: /* advertise all values */
tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
ADVERTISE_100HALF|ADVERTISE_100FULL) ;
break;
case SPEED10_HALF:
tmp |= ADVERTISE_10HALF;
break;
case SPEED10_FULL:
tmp |= ADVERTISE_10FULL;
break;
case SPEED100_HALF:
tmp |= ADVERTISE_100HALF;
break;
case SPEED100_FULL:
tmp |= ADVERTISE_100FULL;
break;
}
reg_val = lp->ext_phy_option;
/* Disable port manager */
writel((u32) EN_PMGR, mmio + CMD3 );
/* Reset PHY */
writel((u32)XPHYRST | lp->ext_phy_option, mmio + CTRL2);
if(advert != tmp)
amd8111e_mdio_write(dev, PHY_ID, MII_ADVERTISE, tmp);
/* Restart auto negotiation */
bmcr = amd8111e_mdio_read(dev, PHY_ID, MII_BMCR);
bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
amd8111e_mdio_write(dev, PHY_ID, MII_BMCR, bmcr);
/* Enable port manager */
writel((u32)VAL1 | EN_PMGR, mmio + CMD3 );
}
/*
......@@ -156,7 +266,7 @@ static int amd8111e_free_skbs(struct net_device *dev)
}
/*
This will set the receive buffer length corresponding to the mtu size of network interface.
This will set the receive buffer length corresponding to the mtu size of networkinterface.
*/
static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
{
......@@ -226,13 +336,13 @@ static int amd8111e_init_ring(struct net_device *dev)
lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len);
lp->rx_ring[i].rx_dr_offset10 = cpu_to_le16(OWN_BIT);
lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
}
/* Initializing transmit descriptors */
for (i = 0; i < NUM_TX_RING_DR; i++) {
lp->tx_ring[i].buff_phy_addr = 0;
lp->tx_ring[i].tx_dr_offset2 = 0;
lp->tx_ring[i].tx_flags = 0;
lp->tx_ring[i].buff_count = 0;
}
......@@ -253,6 +363,65 @@ static int amd8111e_init_ring(struct net_device *dev)
err_no_mem:
return -ENOMEM;
}
/* This function will set the interrupt coalescing according to the input arguments */
static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
{
unsigned int timeout;
unsigned int event_count;
struct amd8111e_priv *lp = dev->priv;
void* mmio = lp->mmio;
struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
switch(cmod)
{
case RX_INTR_COAL :
timeout = coal_conf->rx_timeout;
event_count = coal_conf->rx_event_count;
if( timeout > MAX_TIMEOUT ||
event_count > MAX_EVENT_COUNT )
return -EINVAL;
timeout = timeout * DELAY_TIMER_CONV;
writel(VAL0|STINTEN, mmio+INTEN0);
writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
mmio+DLY_INT_A);
break;
case TX_INTR_COAL :
timeout = coal_conf->tx_timeout;
event_count = coal_conf->tx_event_count;
if( timeout > MAX_TIMEOUT ||
event_count > MAX_EVENT_COUNT )
return -EINVAL;
timeout = timeout * DELAY_TIMER_CONV;
writel(VAL0|STINTEN,mmio+INTEN0);
writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
mmio+DLY_INT_B);
break;
case DISABLE_COAL:
writel(0,mmio+STVAL);
writel(STINTEN, mmio+INTEN0);
writel(0, mmio +DLY_INT_B);
writel(0, mmio+DLY_INT_A);
break;
case ENABLE_COAL:
/* Start the timer */
writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */
writel(VAL0|STINTEN, mmio+INTEN0);
break;
default:
break;
}
return 0;
}
/*
This function initializes the device registers and starts the device.
*/
......@@ -267,13 +436,17 @@ static int amd8111e_restart(struct net_device *dev)
if(amd8111e_init_ring(dev))
return -ENOMEM;
/* enable the port manager and set auto negotiation always */
writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
amd8111e_set_ext_phy(dev);
/* set control registers */
reg_val = readl(mmio + CTRL1);
writel( reg_val| XMTSP_128 | CACHE_ALIGN | B1_MASK, mmio + CTRL1 );
reg_val &= ~XMTSP_MASK;
writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
/* enable interrupt */
writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
......@@ -288,15 +461,21 @@ static int amd8111e_restart(struct net_device *dev)
writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
/* set default IPG to 96 */
writew((u32)DEFAULT_IPG,mmio+IPG);
writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
if(lp->options & OPTION_JUMBO_ENABLE){
writel((u32)VAL2|JUMBO, mmio + CMD3);
/* Reset REX_UFLO */
writel( REX_UFLO, mmio + CMD2);
/* Should not set REX_UFLO for jumbo frames */
writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
}else
writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
}else{
writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
writel((u32)JUMBO, mmio + CMD3);
}
#if AMD8111E_VLAN_TAG_USED
writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
......@@ -306,11 +485,20 @@ static int amd8111e_restart(struct net_device *dev)
/* Setting the MAC address to the device */
for(i = 0; i < ETH_ADDR_LEN; i++)
writeb( dev->dev_addr[i], mmio + PADR + i );
/* Enable interrupt coalesce */
if(lp->options & OPTION_INTR_COAL_ENABLE){
printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
dev->name);
amd8111e_set_coalesce(dev,ENABLE_COAL);
}
/* set RUN bit to start the chip */
writel(VAL2 | RDMD0, mmio + CMD0);
writel(VAL0 | INTREN | RUN, mmio + CMD0);
/* To avoid PCI posting bug */
readl(mmio+CMD0);
return 0;
}
/*
......@@ -383,7 +571,7 @@ static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
writew(MIB_CLEAR, mmio + MIB_ADDR);
/* Clear LARF */
AMD8111E_WRITE_REG64(mmio, LADRF,logic_filter);
amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
/* SRAM_SIZE register */
reg_val = readl(mmio + SRAM_SIZE);
......@@ -393,8 +581,11 @@ static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
#if AMD8111E_VLAN_TAG_USED
writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
#endif
/* CMD2 register */
reg_val = readl(mmio + CMD2);
/* Set default value to CTRL1 Register */
writel(CTRL1_DEFAULT, mmio + CTRL1);
/* To avoid PCI posting bug */
readl(mmio + CMD2);
}
......@@ -412,6 +603,9 @@ static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
/* Clear INT0 */
intr0 = readl(lp->mmio + INT0);
writel(intr0, lp->mmio + INT0);
/* To avoid PCI posting bug */
readl(lp->mmio + INT0);
}
......@@ -421,6 +615,9 @@ This function stops the chip.
static void amd8111e_stop_chip(struct amd8111e_priv* lp)
{
writel(RUN, lp->mmio + CMD0);
/* To avoid PCI posting bug */
readl(lp->mmio + CMD0);
}
/*
......@@ -467,11 +664,10 @@ static int amd8111e_tx(struct net_device *dev)
struct amd8111e_priv* lp = dev->priv;
int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
int status;
/* Complete all the transmit packet */
while (lp->tx_complete_idx != lp->tx_idx){
tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
status = le16_to_cpu(lp->tx_ring[tx_index].tx_dr_offset2);
status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
if(status & OWN_BIT)
break; /* It still hasn't been Txed */
......@@ -487,11 +683,15 @@ static int amd8111e_tx(struct net_device *dev)
lp->tx_skbuff[tx_index] = 0;
lp->tx_dma_addr[tx_index] = 0;
}
lp->tx_complete_idx++;
lp->tx_complete_idx++;
/*COAL update tx coalescing parameters */
lp->coal_conf.tx_packets++;
lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
if (netif_queue_stopped(dev) &&
lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
/* The ring is no longer full, clear tbusy. */
/* lp->tx_full = 0; */
netif_wake_queue (dev);
}
}
......@@ -516,33 +716,31 @@ static int amd8111e_rx(struct net_device *dev)
/* If we own the next entry, it's a new packet. Send it up. */
while(++num_rx_pkt <= max_rx_pkt){
if(lp->rx_ring[rx_index].rx_dr_offset10 & OWN_BIT)
if(lp->rx_ring[rx_index].rx_flags & OWN_BIT)
return 0;
/* check if err summary bit is set */
if(le16_to_cpu(lp->rx_ring[rx_index].rx_dr_offset10) & ERR_BIT){
if(le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & ERR_BIT){
/*
* There is a tricky error noted by John Murphy,
* <murf@perftech.com> to Russ Nelson: Even with full-sized
* buffers it's possible for a jabber packet to use two
* buffers, with only the last correctly noting the error. */
/* reseting flags */
lp->rx_ring[rx_index].rx_dr_offset10 &=
cpu_to_le16(RESET_RX_FLAGS);
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
goto err_next_pkt;
}
/* check for STP and ENP */
status = le16_to_cpu(lp->rx_ring[rx_index].rx_dr_offset10);
status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
if(!((status & STP_BIT) && (status & ENP_BIT))){
/* reseting flags */
lp->rx_ring[rx_index].rx_dr_offset10 &=
cpu_to_le16(RESET_RX_FLAGS);
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
goto err_next_pkt;
}
pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
#if AMD8111E_VLAN_TAG_USED
vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_dr_offset10) & TT_MASK;
vtag = le16_to_cpu(lp->rx_ring[rx_index].rx_flags) & TT_MASK;
/*MAC will strip vlan tag*/
if(lp->vlgrp != NULL && vtag !=0)
min_pkt_len =MIN_PKT_LEN - 4;
......@@ -551,16 +749,14 @@ static int amd8111e_rx(struct net_device *dev)
min_pkt_len =MIN_PKT_LEN;
if (pkt_len < min_pkt_len) {
lp->rx_ring[rx_index].rx_dr_offset10 &=
cpu_to_le16(RESET_RX_FLAGS);
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->stats.rx_errors++;
goto err_next_pkt;
}
if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
/* if allocation fail,
ignore that pkt and go to next one */
lp->rx_ring[rx_index].rx_dr_offset10 &=
cpu_to_le16(RESET_RX_FLAGS);
lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
lp->stats.rx_errors++;
goto err_next_pkt;
}
......@@ -580,22 +776,26 @@ static int amd8111e_rx(struct net_device *dev)
#if AMD8111E_VLAN_TAG_USED
vtag = lp->rx_ring[rx_index].rx_dr_offset10 & TT_MASK;
vtag = lp->rx_ring[rx_index].rx_flags & TT_MASK;
if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
amd8111e_vlan_rx(lp, skb,
lp->rx_ring[rx_index].tag_ctrl_info);
} else
#endif
dev->last_rx = jiffies;
netif_rx (skb);
/*COAL update rx coalescing parameters*/
lp->coal_conf.rx_packets++;
lp->coal_conf.rx_bytes += pkt_len;
dev->last_rx = jiffies;
err_next_pkt:
lp->rx_ring[rx_index].buff_phy_addr
= cpu_to_le32(lp->rx_dma_addr[rx_index]);
lp->rx_ring[rx_index].buff_count =
cpu_to_le16(lp->rx_buff_len-2);
lp->rx_ring[rx_index].rx_dr_offset10 |= cpu_to_le16(OWN_BIT);
lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
}
......@@ -603,8 +803,8 @@ static int amd8111e_rx(struct net_device *dev)
}
/*
This function will store the original speed to restore later, if autoneg is turned on. This speed will be set later when the autoneg is turned off. If the link status indicates that link is down, that will be indicated to the kernel */
This function will indicate the link status to the kernel.
*/
static int amd8111e_link_change(struct net_device* dev)
{
struct amd8111e_priv *lp = dev->priv;
......@@ -614,21 +814,11 @@ static int amd8111e_link_change(struct net_device* dev)
status0 = readl(lp->mmio + STAT0);
if(status0 & LINK_STATS){
if(status0 & AUTONEG_COMPLETE){
/* keeping the original speeds */
if((lp->link_config.speed != SPEED_INVALID)&&
(lp->link_config.duplex != DUPLEX_INVALID)){
lp->link_config.orig_speed = lp->link_config.speed;
lp->link_config.orig_duplex = lp->link_config.duplex;
lp->link_config.orig_phy_option = lp->ext_phy_option;
}
lp->link_config.speed = SPEED_INVALID;
lp->link_config.duplex = DUPLEX_INVALID;
if(status0 & AUTONEG_COMPLETE)
lp->link_config.autoneg = AUTONEG_ENABLE;
netif_carrier_on(dev);
return 0;
}
else
lp->link_config.autoneg = AUTONEG_DISABLE;
if(status0 & FULL_DPLX)
lp->link_config.duplex = DUPLEX_FULL;
else
......@@ -638,13 +828,17 @@ static int amd8111e_link_change(struct net_device* dev)
lp->link_config.speed = SPEED_10;
else if(speed == PHY_SPEED_100)
lp->link_config.speed = SPEED_100;
lp->link_config.autoneg = AUTONEG_DISABLE;
printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name,
(lp->link_config.speed == SPEED_100) ? "100": "10",
(lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
netif_carrier_on(dev);
}
else{
lp->link_config.speed = SPEED_INVALID;
lp->link_config.duplex = DUPLEX_INVALID;
lp->link_config.autoneg = AUTONEG_INVALID;
printk(KERN_INFO "%s: Link is Down.\n",dev->name);
netif_carrier_off(dev);
}
......@@ -671,129 +865,250 @@ static int amd8111e_read_mib(void* mmio, u8 MIB_COUNTER)
}
/*
This function retuurns the reads the mib registers and returns the hardware statistics. It adds the previous statistics with new values.*/
This function reads the mib registers and returns the hardware statistics. It updates previous internal driver statistics with new values.
*/
static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
{
struct amd8111e_priv *lp = dev->priv;
void * mmio = lp->mmio;
unsigned long flags;
struct net_device_stats *prev_stats = &lp->prev_stats;
/* struct net_device_stats *prev_stats = &lp->prev_stats; */
struct net_device_stats* new_stats = &lp->stats;
if(!lp->opened)
return prev_stats;
return &lp->stats;
spin_lock_irqsave (&lp->lock, flags);
/* stats.rx_packets */
new_stats->rx_packets = prev_stats->rx_packets+
amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
amd8111e_read_mib(mmio, rcv_multicast_pkts)+
amd8111e_read_mib(mmio, rcv_unicast_pkts);
new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
amd8111e_read_mib(mmio, rcv_multicast_pkts)+
amd8111e_read_mib(mmio, rcv_unicast_pkts);
/* stats.tx_packets */
new_stats->tx_packets = prev_stats->tx_packets+
amd8111e_read_mib(mmio, xmt_packets);
new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
/*stats.rx_bytes */
new_stats->rx_bytes = prev_stats->rx_bytes+
amd8111e_read_mib(mmio, rcv_octets);
new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
/* stats.tx_bytes */
new_stats->tx_bytes = prev_stats->tx_bytes+
amd8111e_read_mib(mmio, xmt_octets);
new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
/* stats.rx_errors */
new_stats->rx_errors = prev_stats->rx_errors+
amd8111e_read_mib(mmio, rcv_undersize_pkts)+
amd8111e_read_mib(mmio, rcv_fragments)+
amd8111e_read_mib(mmio, rcv_jabbers)+
amd8111e_read_mib(mmio, rcv_alignment_errors)+
amd8111e_read_mib(mmio, rcv_fcs_errors)+
amd8111e_read_mib(mmio, rcv_miss_pkts);
new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
amd8111e_read_mib(mmio, rcv_fragments)+
amd8111e_read_mib(mmio, rcv_jabbers)+
amd8111e_read_mib(mmio, rcv_alignment_errors)+
amd8111e_read_mib(mmio, rcv_fcs_errors)+
amd8111e_read_mib(mmio, rcv_miss_pkts);
/* stats.tx_errors */
new_stats->tx_errors = prev_stats->tx_errors+
amd8111e_read_mib(mmio, xmt_underrun_pkts);
new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
/* stats.rx_dropped*/
new_stats->rx_dropped = prev_stats->rx_dropped+
amd8111e_read_mib(mmio, rcv_miss_pkts);
new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
/* stats.tx_dropped*/
new_stats->tx_dropped = prev_stats->tx_dropped+
amd8111e_read_mib(mmio, xmt_underrun_pkts);
new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts);
/* stats.multicast*/
new_stats->multicast = prev_stats->multicast+
amd8111e_read_mib(mmio, rcv_multicast_pkts);
new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
/* stats.collisions*/
new_stats->collisions = prev_stats->collisions+
amd8111e_read_mib(mmio, xmt_collisions);
new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
/* stats.rx_length_errors*/
new_stats->rx_length_errors = prev_stats->rx_length_errors+
new_stats->rx_length_errors =
amd8111e_read_mib(mmio, rcv_undersize_pkts)+
amd8111e_read_mib(mmio, rcv_oversize_pkts);
/* stats.rx_over_errors*/
new_stats->rx_over_errors = prev_stats->rx_over_errors+
amd8111e_read_mib(mmio, rcv_miss_pkts);
new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
/* stats.rx_crc_errors*/
new_stats->rx_crc_errors = prev_stats->rx_crc_errors+
amd8111e_read_mib(mmio, rcv_fcs_errors);
new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
/* stats.rx_frame_errors*/
new_stats->rx_frame_errors = prev_stats->rx_frame_errors+
new_stats->rx_frame_errors =
amd8111e_read_mib(mmio, rcv_alignment_errors);
/* stats.rx_fifo_errors */
new_stats->rx_fifo_errors = prev_stats->rx_fifo_errors+
amd8111e_read_mib(mmio, rcv_miss_pkts);
new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
/* stats.rx_missed_errors */
new_stats->rx_missed_errors = prev_stats->rx_missed_errors+
amd8111e_read_mib(mmio, rcv_miss_pkts);
new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
/* stats.tx_aborted_errors*/
new_stats->tx_aborted_errors = prev_stats->tx_aborted_errors+
new_stats->tx_aborted_errors =
amd8111e_read_mib(mmio, xmt_excessive_collision);
/* stats.tx_carrier_errors*/
new_stats->tx_carrier_errors = prev_stats->tx_carrier_errors+
new_stats->tx_carrier_errors =
amd8111e_read_mib(mmio, xmt_loss_carrier);
/* stats.tx_fifo_errors*/
new_stats->tx_fifo_errors = prev_stats->tx_fifo_errors+
amd8111e_read_mib(mmio, xmt_underrun_pkts);
new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
/* stats.tx_window_errors*/
new_stats->tx_window_errors = prev_stats->tx_window_errors+
new_stats->tx_window_errors =
amd8111e_read_mib(mmio, xmt_late_collision);
/* Reset the mibs for collecting new statistics */
/* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
spin_unlock_irqrestore (&lp->lock, flags);
return new_stats;
}
/* This function recalculate the interupt coalescing mode on every interrupt
according to the datarate and the packet rate.
*/
static int amd8111e_calc_coalesce(struct net_device *dev)
{
struct amd8111e_priv *lp = dev->priv;
struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
int tx_pkt_rate;
int rx_pkt_rate;
int tx_data_rate;
int rx_data_rate;
int rx_pkt_size;
int tx_pkt_size;
tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
coal_conf->tx_prev_packets = coal_conf->tx_packets;
tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
coal_conf->tx_prev_bytes = coal_conf->tx_bytes;
rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
coal_conf->rx_prev_packets = coal_conf->rx_packets;
rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
coal_conf->rx_prev_bytes = coal_conf->rx_bytes;
if(rx_pkt_rate < 800){
if(coal_conf->rx_coal_type != NO_COALESCE){
coal_conf->rx_timeout = 0x0;
coal_conf->rx_event_count = 0;
amd8111e_set_coalesce(dev,RX_INTR_COAL);
coal_conf->rx_coal_type = NO_COALESCE;
}
}
else{
rx_pkt_size = rx_data_rate/rx_pkt_rate;
if (rx_pkt_size < 128){
if(coal_conf->rx_coal_type != NO_COALESCE){
coal_conf->rx_timeout = 0;
coal_conf->rx_event_count = 0;
amd8111e_set_coalesce(dev,RX_INTR_COAL);
coal_conf->rx_coal_type = NO_COALESCE;
}
}
else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
if(coal_conf->rx_coal_type != LOW_COALESCE){
coal_conf->rx_timeout = 1;
coal_conf->rx_event_count = 4;
amd8111e_set_coalesce(dev,RX_INTR_COAL);
coal_conf->rx_coal_type = LOW_COALESCE;
}
}
else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
if(coal_conf->rx_coal_type != MEDIUM_COALESCE){
coal_conf->rx_timeout = 1;
coal_conf->rx_event_count = 4;
amd8111e_set_coalesce(dev,RX_INTR_COAL);
coal_conf->rx_coal_type = MEDIUM_COALESCE;
}
}
else if(rx_pkt_size >= 1024){
if(coal_conf->rx_coal_type != HIGH_COALESCE){
coal_conf->rx_timeout = 2;
coal_conf->rx_event_count = 3;
amd8111e_set_coalesce(dev,RX_INTR_COAL);
coal_conf->rx_coal_type = HIGH_COALESCE;
}
}
}
/* NOW FOR TX INTR COALESC */
if(tx_pkt_rate < 800){
if(coal_conf->tx_coal_type != NO_COALESCE){
coal_conf->tx_timeout = 0x0;
coal_conf->tx_event_count = 0;
amd8111e_set_coalesce(dev,TX_INTR_COAL);
coal_conf->tx_coal_type = NO_COALESCE;
}
}
else{
tx_pkt_size = tx_data_rate/tx_pkt_rate;
if (tx_pkt_size < 128){
if(coal_conf->tx_coal_type != NO_COALESCE){
coal_conf->tx_timeout = 0;
coal_conf->tx_event_count = 0;
amd8111e_set_coalesce(dev,TX_INTR_COAL);
coal_conf->tx_coal_type = NO_COALESCE;
}
}
else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
if(coal_conf->tx_coal_type != LOW_COALESCE){
coal_conf->tx_timeout = 1;
coal_conf->tx_event_count = 2;
amd8111e_set_coalesce(dev,TX_INTR_COAL);
coal_conf->tx_coal_type = LOW_COALESCE;
}
}
else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
if(coal_conf->tx_coal_type != MEDIUM_COALESCE){
coal_conf->tx_timeout = 2;
coal_conf->tx_event_count = 5;
amd8111e_set_coalesce(dev,TX_INTR_COAL);
coal_conf->tx_coal_type = MEDIUM_COALESCE;
}
}
else if(tx_pkt_size >= 1024){
if (tx_pkt_size >= 1024){
if(coal_conf->tx_coal_type != HIGH_COALESCE){
coal_conf->tx_timeout = 4;
coal_conf->tx_event_count = 8;
amd8111e_set_coalesce(dev,TX_INTR_COAL);
coal_conf->tx_coal_type = HIGH_COALESCE;
}
}
}
}
return 0;
}
/*
This is device interrupt function. It handles transmit, receive and link change interrupts.
This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
*/
static irqreturn_t
amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device * dev = (struct net_device *) dev_id;
struct amd8111e_priv *lp = dev->priv;
void * mmio = lp->mmio;
unsigned int intr0;
int handled = 0;
unsigned int handled = 1;
if(dev == NULL)
return IRQ_NONE;
spin_lock (&lp->lock);
if (regs) spin_lock (&lp->lock);
/* disabling interrupt */
writel(INTREN, mmio + CMD0);
......@@ -802,10 +1117,11 @@ amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
/* Process all the INT event until INTR bit is clear. */
if (!(intr0 & INTR))
if (!(intr0 & INTR)) {
handled = 0;
goto err_no_interrupt;
handled = 1;
}
/* Current driver processes 3 interrupts : RINT,TINT,LCINT */
writel(intr0, mmio + INT0);
......@@ -822,15 +1138,21 @@ amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
/* Check if Link Change Interrupt has occurred. */
if (intr0 & LCINT)
amd8111e_link_change(dev);
/* Check if Hardware Timer Interrupt has occurred. */
if (intr0 & STINT)
amd8111e_calc_coalesce(dev);
err_no_interrupt:
writel( VAL0 | INTREN,mmio + CMD0);
spin_unlock(&lp->lock);
if (regs) spin_unlock(&lp->lock);
return IRQ_RETVAL(handled);
}
/*
This function closes the network interface and copies the new set of statistics into the previous statistics structure so that most recent statistics will be available after the interface is down.
This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
*/
static int amd8111e_close(struct net_device * dev)
{
......@@ -845,10 +1167,15 @@ static int amd8111e_close(struct net_device * dev)
netif_carrier_off(lp->amd8111e_net_dev);
/* Delete ipg timer */
if(lp->options & OPTION_DYN_IPG_ENABLE)
del_timer_sync(&lp->ipg_data.ipg_timer);
/* Update the statistics before closing */
amd8111e_get_stats(dev);
spin_unlock_irq(&lp->lock);
free_irq(dev->irq, dev);
memcpy(&lp->prev_stats,amd8111e_get_stats(dev), sizeof(lp->prev_stats));
lp->opened = 0;
return 0;
}
......@@ -870,7 +1197,12 @@ static int amd8111e_open(struct net_device * dev )
spin_unlock_irq(&lp->lock);
return -ENOMEM;
}
/* Start ipg timer */
if(lp->options & OPTION_DYN_IPG_ENABLE){
add_timer(&lp->ipg_data.ipg_timer);
printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
}
lp->opened = 1;
spin_unlock_irq(&lp->lock);
......@@ -908,11 +1240,10 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
lp->tx_skbuff[tx_index] = skb;
lp->tx_ring[tx_index].tx_dr_offset2 = 0;
lp->tx_ring[tx_index].tx_flags = 0;
#if AMD8111E_VLAN_TAG_USED
if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
lp->tx_ring[tx_index].tag_ctrl_cmd |=
cpu_to_le32(TCC_VLAN_INSERT);
lp->tx_ring[tx_index].tag_ctrl_info =
......@@ -926,7 +1257,7 @@ static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
(u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
/* Set FCS and LTINT bits */
lp->tx_ring[tx_index].tx_dr_offset2 |=
lp->tx_ring[tx_index].tx_flags |=
cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
lp->tx_idx++;
......@@ -949,16 +1280,54 @@ This function returns all the memory mapped registers of the device.
static char* amd8111e_read_regs(struct amd8111e_priv* lp)
{
void * mmio = lp->mmio;
unsigned char * reg_buff;
u32 * reg_buff;
int i;
reg_buff = kmalloc( AMD8111E_REG_DUMP_LEN,GFP_KERNEL);
if(NULL == reg_buff)
return NULL;
for (i=0; i < AMD8111E_REG_DUMP_LEN; i+=4)
reg_buff[i]= readl(mmio + i);
return reg_buff;
/* Read only necessary registers */
reg_buff[0] = readl(mmio + XMT_RING_BASE_ADDR0);
reg_buff[1] = readl(mmio + XMT_RING_LEN0);
reg_buff[2] = readl(mmio + RCV_RING_BASE_ADDR0);
reg_buff[3] = readl(mmio + RCV_RING_LEN0);
reg_buff[4] = readl(mmio + CMD0);
reg_buff[5] = readl(mmio + CMD2);
reg_buff[6] = readl(mmio + CMD3);
reg_buff[7] = readl(mmio + CMD7);
reg_buff[8] = readl(mmio + INT0);
reg_buff[9] = readl(mmio + INTEN0);
reg_buff[10] = readl(mmio + LADRF);
reg_buff[11] = readl(mmio + LADRF+4);
reg_buff[12] = readl(mmio + STAT0);
return (char *)reg_buff;
}
/*
amd8111e crc generator implementation is different from the kernel
ether_crc() function.
*/
int amd8111e_ether_crc(int len, char* mac_addr)
{
int i,byte;
unsigned char octet;
u32 crc= INITCRC;
for(byte=0; byte < len; byte++){
octet = mac_addr[byte];
for( i=0;i < 8; i++){
/*If the next bit form the input stream is 1,subtract the divisor (CRC32) from the dividend(crc).*/
if( (octet & 0x1) ^ (crc & 0x1) ){
crc >>= 1;
crc ^= CRC32;
}
else
crc >>= 1;
octet >>= 1;
}
}
return crc;
}
/*
This function sets promiscuos mode, all-multi mode or the multicast address
......@@ -970,9 +1339,8 @@ static void amd8111e_set_multicast_list(struct net_device *dev)
struct amd8111e_priv *lp = dev->priv;
u32 mc_filter[2] ;
int i,bit_num;
if(dev->flags & IFF_PROMISC){
printk("%s: Setting promiscuous mode.\n",dev->name);
printk(KERN_INFO "%s: Setting promiscuous mode.\n",dev->name);
writel( VAL2 | PROM, lp->mmio + CMD2);
return;
}
......@@ -983,7 +1351,7 @@ static void amd8111e_set_multicast_list(struct net_device *dev)
mc_filter[1] = mc_filter[0] = 0xffffffff;
lp->mc_list = dev->mc_list;
lp->options |= OPTION_MULTICAST_ENABLE;
AMD8111E_WRITE_REG64(lp->mmio, LADRF,mc_filter);
amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
return;
}
if( dev->mc_count == 0 ){
......@@ -991,7 +1359,7 @@ static void amd8111e_set_multicast_list(struct net_device *dev)
mc_filter[1] = mc_filter[0] = 0;
lp->mc_list = 0;
lp->options &= ~OPTION_MULTICAST_ENABLE;
AMD8111E_WRITE_REG64(lp->mmio, LADRF,mc_filter);
amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
/* disable promiscous mode */
writel(PROM, lp->mmio + CMD2);
return;
......@@ -1002,14 +1370,16 @@ static void amd8111e_set_multicast_list(struct net_device *dev)
mc_filter[1] = mc_filter[0] = 0;
for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
i++, mc_ptr = mc_ptr->next) {
bit_num = ether_crc(ETH_ALEN, mc_ptr->dmi_addr) >> 26;
bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr) >> 26 ) & 0x3f;
mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
}
amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
/* To eliminate PCI posting bug */
readl(lp->mmio + CMD2);
AMD8111E_WRITE_REG64(lp->mmio, LADRF, mc_filter);
return;
}
/*
This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
*/
......@@ -1032,6 +1402,7 @@ static int amd8111e_ethtool_ioctl(struct net_device* dev, void* useraddr)
strcpy (info.driver, MODULE_NAME);
strcpy (info.version, MODULE_VERSION);
memset(&info.fw_version, 0, sizeof(info.fw_version));
sprintf(info.fw_version,"%u",chip_version);
strcpy (info.bus_info, pci_dev->slot_name);
info.eedump_len = 0;
info.regdump_len = AMD8111E_REG_DUMP_LEN;
......@@ -1039,85 +1410,27 @@ static int amd8111e_ethtool_ioctl(struct net_device* dev, void* useraddr)
return -EFAULT;
return 0;
}
case ETHTOOL_GSET:{
struct ethtool_cmd cmd = { ETHTOOL_GSET };
if (!lp->opened)
return -EAGAIN;
cmd.supported = SUPPORTED_Autoneg |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_MII;
cmd.advertising = ADVERTISED_Autoneg |
ADVERTISED_100baseT_Half |
ADVERTISED_100baseT_Full |
ADVERTISED_10baseT_Half |
ADVERTISED_10baseT_Full |
ADVERTISED_MII;
cmd.speed = lp->link_config.speed;
cmd.duplex = lp->link_config.duplex;
cmd.port = 0;
cmd.phy_address = PHY_ID;
cmd.transceiver = XCVR_EXTERNAL;
cmd.autoneg = lp->link_config.autoneg;
cmd.maxtxpkt = 0; /* not implemented interrupt coalasing */
cmd.maxrxpkt = 0; /* not implemented interrupt coalasing */
if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
/* get settings */
case ETHTOOL_GSET: {
struct ethtool_cmd ecmd = { ETHTOOL_GSET };
spin_lock_irq(&lp->lock);
mii_ethtool_gset(&lp->mii_if, &ecmd);
spin_unlock_irq(&lp->lock);
if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
return -EFAULT;
return 0;
}
}
/* set settings */
case ETHTOOL_SSET: {
struct ethtool_cmd cmd;
if (!lp->opened)
return -EAGAIN;
if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
int r;
struct ethtool_cmd ecmd;
if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
return -EFAULT;
spin_lock_irq(&lp->lock);
if(cmd.autoneg == AUTONEG_ENABLE){
/* keeping the original speeds */
if((lp->link_config.speed != SPEED_INVALID)&&
(lp->link_config.duplex != DUPLEX_INVALID)){
lp->link_config.orig_speed = lp->link_config.speed;
lp->link_config.orig_duplex = lp->link_config.duplex;
lp->link_config.orig_phy_option = lp->ext_phy_option;
}
lp->ext_phy_option = XPHYANE;
}
else if(cmd.speed == SPEED_100 && cmd.duplex == DUPLEX_HALF)
lp->ext_phy_option = XPHYSP;
else if(cmd.speed == SPEED_100 && cmd.duplex == DUPLEX_FULL)
lp->ext_phy_option = XPHYSP |XPHYFD;
else if(cmd.speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
lp->ext_phy_option = 0;
else if(cmd.speed == SPEED_10 && cmd.duplex == DUPLEX_FULL)
lp->ext_phy_option = XPHYFD;
else {
/* setting the original speed */
cmd.speed = lp->link_config.orig_speed;
cmd.duplex = lp->link_config.orig_duplex;
lp->ext_phy_option = lp->link_config.orig_phy_option;
}
lp->link_config.autoneg = cmd.autoneg;
if (cmd.autoneg == AUTONEG_ENABLE) {
lp->link_config.speed = SPEED_INVALID;
lp->link_config.duplex = DUPLEX_INVALID;
} else {
lp->link_config.speed = cmd.speed;
lp->link_config.duplex = cmd.duplex;
}
amd8111e_set_ext_phy(dev);
r = mii_ethtool_sset(&lp->mii_if, &ecmd);
spin_unlock_irq(&lp->lock);
return 0;
return r;
}
case ETHTOOL_GREGS: {
struct ethtool_regs regs;
......@@ -1143,24 +1456,17 @@ static int amd8111e_ethtool_ioctl(struct net_device* dev, void* useraddr)
kfree(regbuf);
return ret;
}
/* restart autonegotiation */
case ETHTOOL_NWAY_RST: {
int ret;
spin_lock_irq(&lp->lock);
if(lp->link_config.autoneg == AUTONEG_ENABLE){
lp->ext_phy_option = XPHYANE;
amd8111e_set_ext_phy(dev);
ret = 0;
}else
ret = -EINVAL;
spin_unlock_irq(&lp->lock);
return ret;
return mii_nway_restart(&lp->mii_if);
}
/* get link status */
case ETHTOOL_GLINK: {
struct ethtool_value val = { ETHTOOL_GLINK };
val.data = netif_carrier_ok(dev) ? 1 : 0;
struct ethtool_value val = {ETHTOOL_GLINK};
val.data = mii_link_ok(&lp->mii_if);
if (copy_to_user(useraddr, &val, sizeof(val)))
return -EFAULT;
return 0;
}
case ETHTOOL_GWOL: {
struct ethtool_wolinfo wol_info = { ETHTOOL_GWOL };
......@@ -1199,60 +1505,6 @@ static int amd8111e_ethtool_ioctl(struct net_device* dev, void* useraddr)
}
return -EOPNOTSUPP;
}
static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
{
void * mmio = lp->mmio;
unsigned int reg_val;
unsigned int repeat= REPEAT_CNT;
reg_val = readl(mmio + PHY_ACCESS);
while (reg_val & PHY_CMD_ACTIVE)
reg_val = readl( mmio + PHY_ACCESS );
writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
((reg & 0x1f) << 16), mmio +PHY_ACCESS);
do{
reg_val = readl(mmio + PHY_ACCESS);
udelay(30); /* It takes 30 us to read/write data */
} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
if(reg_val & PHY_RD_ERR)
goto err_phy_read;
*val = reg_val & 0xffff;
return 0;
err_phy_read:
*val = 0;
return -EINVAL;
}
static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
{
unsigned int repeat = REPEAT_CNT
void * mmio = lp->mmio;
unsigned int reg_val;
reg_val = readl(mmio + PHY_ACCESS);
while (reg_val & PHY_CMD_ACTIVE)
reg_val = readl( mmio + PHY_ACCESS );
writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
do{
reg_val = readl(mmio + PHY_ACCESS);
udelay(30); /* It takes 30 us to read/write the data */
} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
if(reg_val & PHY_RD_ERR)
goto err_phy_write;
return 0;
err_phy_write:
return -EINVAL;
}
static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
{
struct mii_ioctl_data *data = (struct mii_ioctl_data *)&ifr->ifr_data;
......@@ -1320,15 +1572,10 @@ int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
dev->mtu = new_mtu;
/* if (new_mtu > ETH_DATA_LEN)
lp->options |= OPTION_JUMBO_ENABLE;
else
lp->options &= ~OPTION_JUMBO_ENABLE;
*/
err = amd8111e_restart(dev);
spin_unlock_irq(&lp->lock);
netif_start_queue(dev);
if(!err)
netif_start_queue(dev);
return err;
}
......@@ -1354,73 +1601,41 @@ static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
{
writel( VAL1|MPPLBA, lp->mmio + CMD3);
writel( VAL0|MPEN_SW, lp->mmio + CMD7);
/* To eliminate PCI posting bug */
readl(lp->mmio + CMD7);
return 0;
}
static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
{
/* Adapter is already stoped/suspended/interrupt-disabled */
writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
/* To eliminate PCI posting bug */
readl(lp->mmio + CMD7);
return 0;
}
/* This function is called when a packet transmission fails to complete within a resonable period, on the assumption that an interrupts have been failed or the interface is locked up. This function will reinitialize the hardware */
/*
This function sets the power state of the device. When the device go to lower power states 1,2, and 3 it enables the wake on lan
*/
static int amd8111e_set_power_state(struct amd8111e_priv* lp, u32 state)
static void amd8111e_tx_timeout(struct net_device *dev)
{
u16 power_control;
int pm = lp->pm_cap;
pci_read_config_word(lp->pci_dev,
pm + PCI_PM_CTRL,
&power_control);
power_control |= PCI_PM_CTRL_PME_STATUS;
power_control &= ~(PCI_PM_CTRL_STATE_MASK);
switch (state) {
case 0:
power_control |= 0;
pci_write_config_word(lp->pci_dev,
pm + PCI_PM_CTRL,
power_control);
return 0;
case 1:
power_control |= 1;
break;
case 2:
power_control |= 2;
break;
case 3:
power_control |= 3;
break;
default:
printk(KERN_WARNING "%s: Invalid power state (%d) requested.\n",
lp->amd8111e_net_dev->name, state);
return -EINVAL;
}
if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
amd8111e_enable_magicpkt(lp);
if(lp->options & OPTION_WAKE_PHY_ENABLE)
amd8111e_enable_link_change(lp);
/* Setting new power state. */
pci_write_config_word(lp->pci_dev, pm + PCI_PM_CTRL, power_control);
return 0;
struct amd8111e_priv* lp = dev->priv;
int err;
printk(KERN_ERR "%s: transmit timed out, resetting\n",
dev->name);
spin_lock_irq(&lp->lock);
err = amd8111e_restart(dev);
spin_unlock_irq(&lp->lock);
if(!err)
netif_wake_queue(dev);
}
static int amd8111e_suspend(struct pci_dev *pci_dev, u32 state)
{
struct net_device *dev = pci_get_drvdata(pci_dev);
struct amd8111e_priv *lp = dev->priv;
int err;
if (!netif_running(dev))
return 0;
......@@ -1434,37 +1649,54 @@ static int amd8111e_suspend(struct pci_dev *pci_dev, u32 state)
/* stop chip */
spin_lock_irq(&lp->lock);
if(lp->options & OPTION_DYN_IPG_ENABLE)
del_timer_sync(&lp->ipg_data.ipg_timer);
amd8111e_stop_chip(lp);
spin_unlock_irq(&lp->lock);
err = amd8111e_set_power_state(lp, state);
if (err) {
if(lp->options & OPTION_WOL_ENABLE){
/* enable wol */
if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
amd8111e_enable_magicpkt(lp);
if(lp->options & OPTION_WAKE_PHY_ENABLE)
amd8111e_enable_link_change(lp);
spin_lock_irq(&lp->lock);
amd8111e_restart(dev);
spin_unlock_irq(&lp->lock);
pci_enable_wake(pci_dev, 3, 1);
pci_enable_wake(pci_dev, 4, 1); /* D3 cold */
netif_device_attach(dev);
}
return err;
else{
pci_enable_wake(pci_dev, 3, 0);
pci_enable_wake(pci_dev, 4, 0); /* 4 == D3 cold */
}
pci_save_state(pci_dev, lp->pm_state);
pci_set_power_state(pci_dev, 3);
return 0;
}
static int amd8111e_resume(struct pci_dev *pci_dev)
{
struct net_device *dev = pci_get_drvdata(pci_dev);
struct amd8111e_priv *lp = dev->priv;
int err;
if (!netif_running(dev))
return 0;
err = amd8111e_set_power_state(lp, 0);
if (err)
return err;
pci_set_power_state(pci_dev, 0);
pci_restore_state(pci_dev, lp->pm_state);
pci_enable_wake(pci_dev, 3, 0);
pci_enable_wake(pci_dev, 4, 0); /* D3 cold */
netif_device_attach(dev);
spin_lock_irq(&lp->lock);
amd8111e_restart(dev);
/* Restart ipg timer */
if(lp->options & OPTION_DYN_IPG_ENABLE)
mod_timer(&lp->ipg_data.ipg_timer,
jiffies + (IPG_CONVERGE_TIME * HZ));
spin_unlock_irq(&lp->lock);
return 0;
......@@ -1483,6 +1715,65 @@ static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
pci_set_drvdata(pdev, NULL);
}
}
static void amd8111e_config_ipg(struct net_device* dev)
{
struct amd8111e_priv *lp = dev->priv;
struct ipg_info* ipg_data = &lp->ipg_data;
void * mmio = lp->mmio;
unsigned int prev_col_cnt = ipg_data->col_cnt;
unsigned int total_col_cnt;
unsigned int tmp_ipg;
if(lp->link_config.duplex == DUPLEX_FULL){
ipg_data->ipg = DEFAULT_IPG;
return;
}
if(ipg_data->ipg_state == SSTATE){
if(ipg_data->timer_tick == IPG_STABLE_TIME){
ipg_data->timer_tick = 0;
ipg_data->ipg = MIN_IPG - IPG_STEP;
ipg_data->current_ipg = MIN_IPG;
ipg_data->diff_col_cnt = 0xFFFFFFFF;
ipg_data->ipg_state = CSTATE;
}
else
ipg_data->timer_tick++;
}
if(ipg_data->ipg_state == CSTATE){
/* Get the current collision count */
total_col_cnt = ipg_data->col_cnt =
amd8111e_read_mib(mmio, xmt_collisions);
if ((total_col_cnt - prev_col_cnt) <
(ipg_data->diff_col_cnt)){
ipg_data->diff_col_cnt =
total_col_cnt - prev_col_cnt ;
ipg_data->ipg = ipg_data->current_ipg;
}
ipg_data->current_ipg += IPG_STEP;
if (ipg_data->current_ipg <= MAX_IPG)
tmp_ipg = ipg_data->current_ipg;
else{
tmp_ipg = ipg_data->ipg;
ipg_data->ipg_state = SSTATE;
}
writew((u32)tmp_ipg, mmio + IPG);
writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
}
mod_timer(&lp->ipg_data.ipg_timer, jiffies + (IPG_CONVERGE_TIME * HZ));
return;
}
static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
const struct pci_device_id *ent)
......@@ -1491,7 +1782,6 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
unsigned long reg_addr,reg_len;
struct amd8111e_priv* lp;
struct net_device* dev;
unsigned int chip_version;
err = pci_enable_device(pdev);
if(err){
......@@ -1542,7 +1832,6 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
}
SET_MODULE_OWNER(dev);
SET_NETDEV_DEV(dev, &pdev->dev);
#if AMD8111E_VLAN_TAG_USED
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
......@@ -1551,11 +1840,16 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
#endif
lp = dev->priv;
memset (lp, 0, sizeof (*lp));
lp->pci_dev = pdev;
lp->amd8111e_net_dev = dev;
lp->pm_cap = pm_cap;
/* setting mii default values */
lp->mii_if.dev = dev;
lp->mii_if.mdio_read = amd8111e_mdio_read;
lp->mii_if.mdio_write = amd8111e_mdio_write;
lp->mii_if.phy_id = PHY_ID;
spin_lock_init(&lp->lock);
lp->mmio = ioremap(reg_addr, reg_len);
......@@ -1569,12 +1863,14 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
/* Initializing MAC address */
for(i = 0; i < ETH_ADDR_LEN; i++)
dev->dev_addr[i] =readb(lp->mmio + PADR + i);
/* Setting user defined speed */
if (speed_duplex[card_idx] > sizeof(speed_duplex_mapping))
lp->ext_phy_option = XPHYANE;
else
lp->ext_phy_option =
speed_duplex_mapping[speed_duplex[card_idx]];
/* Setting user defined parametrs */
lp->ext_phy_option = speed_duplex[card_idx];
if(coalesce[card_idx])
lp->options |= OPTION_INTR_COAL_ENABLE;
if(dynamic_ipg[card_idx++])
lp->options |= OPTION_DYN_IPG_ENABLE;
/* Initialize driver entry points */
dev->open = amd8111e_open;
dev->hard_start_xmit = amd8111e_start_xmit;
......@@ -1584,6 +1880,8 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
dev->do_ioctl = amd8111e_ioctl;
dev->change_mtu = amd8111e_change_mtu;
dev->irq =pdev->irq;
dev->tx_timeout = amd8111e_tx_timeout;
dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
#if AMD8111E_VLAN_TAG_USED
dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
......@@ -1593,10 +1891,6 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
/* Set receive buffer length and set jumbo option*/
amd8111e_set_rx_buff_len(dev);
/* dev->tx_timeout = tg3_tx_timeout; */
/* dev->watchdog_timeo = TG3_TX_TIMEOUT; */
err = register_netdev(dev);
if (err) {
......@@ -1607,15 +1901,26 @@ static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
pci_set_drvdata(pdev, dev);
/* Initialize software ipg timer */
if(lp->options & OPTION_DYN_IPG_ENABLE){
init_timer(&lp->ipg_data.ipg_timer);
lp->ipg_data.ipg_timer.data = (unsigned long) dev;
lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
lp->ipg_data.ipg_timer.expires = jiffies +
IPG_CONVERGE_TIME * HZ;
lp->ipg_data.ipg = DEFAULT_IPG;
lp->ipg_data.ipg_state = CSTATE;
};
/* display driver and device information */
chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
printk("%s: AMD-8111e Driver Version: %s\n",dev->name,MODULE_VERSION);
printk("%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
for (i = 0; i < 6; i++)
printk("%2.2x%c", dev->dev_addr[i],i == 5 ? ' ' : ':');
printk("\n");
return 0;
chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", dev->name,MODULE_VERSION);
printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ", dev->name, chip_version);
for (i = 0; i < 6; i++)
printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
printk( "\n");
return 0;
err_iounmap:
iounmap((void *) lp->mmio);
......
drivers/net/amd8111e.h
View file @ 722a9fa5
/*
* Advanced Micro Devices Inc. AMD8111E Linux Network Driver
* Copyright (C) 2003 Advanced Micro Devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
......@@ -27,73 +30,14 @@ Module Name:
Kernel Mode
Revision History:
3.0.0
Initial Revision.
3.0.1
*/
#ifndef _AMD811E_H
#define _AMD811E_H
/* Hardware definitions */
#define B31_MASK 0x80000000
#define B30_MASK 0X40000000
#define B29_MASK 0x20000000
#define B28_MASK 0x10000000
#define B27_MASK 0x08000000
#define B26_MASK 0x04000000
#define B25_MASK 0x02000000
#define B24_MASK 0x01000000
#define B23_MASK 0x00800000
#define B22_MASK 0x00400000
#define B21_MASK 0x00200000
#define B20_MASK 0x00100000
#define B19_MASK 0x00080000
#define B18_MASK 0x00040000
#define B17_MASK 0x00020000
#define B16_MASK 0x00010000
#define B15_MASK 0x8000
#define B14_MASK 0x4000
#define B13_MASK 0x2000
#define B12_MASK 0x1000
#define B11_MASK 0x0800
#define B10_MASK 0x0400
#define B9_MASK 0x0200
#define B8_MASK 0x0100
#define B7_MASK 0x0080
#define B6_MASK 0x0040
#define B5_MASK 0x0020
#define B4_MASK 0x0010
#define B3_MASK 0x0008
#define B2_MASK 0x0004
#define B1_MASK 0x0002
#define B0_MASK 0x0001
/* PCI register offset */
#define PCI_ID_REG 0x00
#define PCI_COMMAND_REG 0x04
/* #define MEMEN_BIT B1_MASK */
/* #define IOEN_BIT B0_MASK */
#define PCI_REV_ID_REG 0x08
#define PCI_MEM_BASE_REG 0x10
/* #define MEMBASE_MASK 0xFFFFF000 */
/* #define MEMBASE_SIZE 4096 */
#define PCI_INTR_REG 0x3C
#define PCI_STATUS_REG 0x06
#define PCI_CAP_ID_REG_OFFSET 0x34
#define PCI_PMC_REG_OFFSET 0x36
#define PCI_PMCSR_REG_OFFSET 0x38
/* #define NEW_CAP 0x0010 */
#define PME_EN 0x0100
#define PARTID_MASK 0xFFFFF000
#define PARTID_START_BIT 12
/* #define LANCE_DWIO_RESET_PORT 0x18
#define LANCE_WIO_RESET_PORT 0x14 */
#define MIB_OFFSET 0x28
/* Command style register access
Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
......@@ -155,7 +99,7 @@ eg., if the value 10011010b is written into the least significant byte of a comm
#define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */
#define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */
#define RCV_RING_LEN0 0x150 /* Transmit Ring0 length register */
#define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */
#define SRAM_SIZE 0x178 /* SRAM size register */
#define SRAM_BOUNDARY 0x17A /* SRAM boundary register */
......@@ -164,391 +108,398 @@ eg., if the value 10011010b is written into the least significant byte of a comm
#define PADR 0x160 /* Physical address register */
#define IFS1 0x18C /* Inter-frame spacing Part1 register */
#define IFS 0x18D /* Inter-frame spacing register */
#define IPG 0x18E /* Inter-frame gap register */
/* 64bit register */
#define LADRF 0x168 /* Logical address filter register */
/* 8bit regsisters */
#define IFS1 0x18C /* Inter-frame spacing Part1 register */
#define IFS 0x18D /* Inter-frame spacing register */
/* Register Bit Definitions */
typedef enum {
ASF_INIT_DONE = (1 << 1),
ASF_INIT_PRESENT = (1 << 0),
}STAT_ASF_BITS;
typedef enum {
MIB_CMD_ACTIVE = (1 << 15 ),
MIB_RD_CMD = (1 << 13 ),
MIB_CLEAR = (1 << 12 ),
MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
(1 << 4) | (1 << 5),
}MIB_ADDR_BITS;
typedef enum {
PMAT_DET = (1 << 12),
MP_DET = (1 << 11),
LC_DET = (1 << 10),
SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
FULL_DPLX = (1 << 6),
LINK_STATS = (1 << 5),
AUTONEG_COMPLETE = (1 << 4),
MIIPD = (1 << 3),
RX_SUSPENDED = (1 << 2),
TX_SUSPENDED = (1 << 1),
RUNNING = (1 << 0),
}STAT0_BITS;
/* STAT_ASF 0x00, 32bit register */
#define ASF_INIT_DONE B1_MASK
#define ASF_INIT_PRESENT B0_MASK
/* MIB_ADDR 0x14, 16bit register */
#define MIB_CMD_ACTIVE B15_MASK
#define MIB_RD_CMD B13_MASK
#define MIB_CLEAR B12_MASK
#define MIB_ADDRESS 0x0000003F /* 5:0 */
/* QOS_ADDR 0x1C, 16bit register */
#define QOS_CMD_ACTIVE B15_MASK
#define QOS_WR_CMD B14_MASK
#define QOS_RD_CMD B13_MASK
#define QOS_ADDRESS 0x0000001F /* 4:0 */
/* STAT0 0x30, 32bit register */
#define PAUSE_PEND B14_MASK
#define PAUSING B13_MASK
#define PMAT_DET B12_MASK
#define MP_DET B11_MASK
#define LC_DET B10_MASK
#define SPEED_MASK 0x0380 /* 9:7 */
#define FULL_DPLX B6_MASK
#define LINK_STATS B5_MASK
#define AUTONEG_COMPLETE B4_MASK
#define MIIPD B3_MASK
#define RX_SUSPENDED B2_MASK
#define TX_SUSPENDED B1_MASK
#define RUNNING B0_MASK
#define PHY_SPEED_10 0x2
#define PHY_SPEED_100 0x3
/* INT0 0x38, 32bit register */
#define INTR B31_MASK
#define PCSINT B28_MASK
#define LCINT B27_MASK
#define APINT5 B26_MASK
#define APINT4 B25_MASK
#define APINT3 B24_MASK
#define TINT_SUM B23_MASK
#define APINT2 B22_MASK
#define APINT1 B21_MASK
#define APINT0 B20_MASK
#define MIIPDTINT B19_MASK
#define MCCIINT B18_MASK
#define MCCINT B17_MASK
#define MREINT B16_MASK
#define RINT_SUM B15_MASK
#define SPNDINT B14_MASK
#define MPINT B13_MASK
#define SINT B12_MASK
#define TINT3 B11_MASK
#define TINT2 B10_MASK
#define TINT1 B9_MASK
#define TINT0 B8_MASK
#define UINT B7_MASK
#define STINT B4_MASK
#define RINT3 B3_MASK
#define RINT2 B2_MASK
#define RINT1 B1_MASK
#define RINT0 B0_MASK
/* INTEN0 0x40, 32bit register */
#define VAL3 B31_MASK /* VAL bit for byte 3 */
#define VAL2 B23_MASK /* VAL bit for byte 2 */
#define VAL1 B15_MASK /* VAL bit for byte 1 */
#define VAL0 B7_MASK /* VAL bit for byte 0 */
/* VAL3 */
#define PSCINTEN B28_MASK
#define LCINTEN B27_MASK
#define APINT5EN B26_MASK
#define APINT4EN B25_MASK
#define APINT3EN B24_MASK
/* VAL2 */
#define APINT2EN B22_MASK
#define APINT1EN B21_MASK
#define APINT0EN B20_MASK
#define MIIPDTINTEN B19_MASK
#define MCCIINTEN B18_MASK
#define MCCINTEN B17_MASK
#define MREINTEN B16_MASK
/* VAL1 */
#define SPNDINTEN B14_MASK
#define MPINTEN B13_MASK
#define SINTEN B12_MASK
#define TINTEN3 B11_MASK
#define TINTEN2 B10_MASK
#define TINTEN1 B9_MASK
#define TINTEN0 B8_MASK
/* VAL0 */
#define STINTEN B4_MASK
#define RINTEN3 B3_MASK
#define RINTEN2 B2_MASK
#define RINTEN1 B1_MASK
#define RINTEN0 B0_MASK
#define INTEN0_CLEAR 0x1F7F7F1F /* Command style register */
/* CMD0 0x48, 32bit register */
/* VAL2 */
#define RDMD3 B19_MASK
#define RDMD2 B18_MASK
#define RDMD1 B17_MASK
#define RDMD0 B16_MASK
/* VAL1 */
#define TDMD3 B11_MASK
#define TDMD2 B10_MASK
#define TDMD1 B9_MASK
#define TDMD0 B8_MASK
/* VAL0 */
#define UINTCMD B6_MASK
#define RX_FAST_SPND B5_MASK
#define TX_FAST_SPND B4_MASK
#define RX_SPND B3_MASK
#define TX_SPND B2_MASK
#define INTREN B1_MASK
#define RUN B0_MASK
#define CMD0_CLEAR 0x000F0F7F /* Command style register */
/* CMD2 0x50, 32bit register */
/* VAL3 */
#define CONDUIT_MODE B29_MASK
/* VAL2 */
#define RPA B19_MASK
#define DRCVPA B18_MASK
#define DRCVBC B17_MASK
#define PROM B16_MASK
/* VAL1 */
#define ASTRP_RCV B13_MASK
#define FCOLL B12_MASK
#define EMBA B11_MASK
#define DXMT2PD B10_MASK
#define LTINTEN B9_MASK
#define DXMTFCS B8_MASK
/* VAL0 */
#define APAD_XMT B6_MASK
#define DRTY B5_MASK
#define INLOOP B4_MASK
#define EXLOOP B3_MASK
#define REX_RTRY B2_MASK
#define REX_UFLO B1_MASK
#define REX_LCOL B0_MASK
#define CMD2_CLEAR 0x3F7F3F7F /* Command style register */
/* CMD3 0x54, 32bit register */
/* VAL3 */
#define ASF_INIT_DONE_ALIAS B29_MASK
/* VAL2 */
#define JUMBO B21_MASK
#define VSIZE B20_MASK
#define VLONLY B19_MASK
#define VL_TAG_DEL B18_MASK
/* VAL1 */
#define EN_PMGR B14_MASK
#define INTLEVEL B13_MASK
#define FORCE_FULL_DUPLEX B12_MASK
#define FORCE_LINK_STATUS B11_MASK
#define APEP B10_MASK
#define MPPLBA B9_MASK
/* VAL0 */
#define RESET_PHY_PULSE B2_MASK
#define RESET_PHY B1_MASK
#define PHY_RST_POL B0_MASK
/* CMD7 0x64, 32bit register */
/* VAL0 */
#define PMAT_SAVE_MATCH B4_MASK
#define PMAT_MODE B3_MASK
#define MPEN_SW B1_MASK
#define LCMODE_SW B0_MASK
#define CMD7_CLEAR 0x0000001B /* Command style register */
/* CTRL0 0x68, 32bit register */
#define PHY_SEL 0x03000000 /* 25:24 */
#define RESET_PHY_WIDTH 0x00FF0000 /* 23:16 */
#define BSWP_REGS B10_MASK
#define BSWP_DESC B9_MASK
#define BSWP_DATA B8_MASK
#define CACHE_ALIGN B4_MASK
#define BURST_LIMIT 0x0000000F /* 3:0 */
/* CTRL1 0x6C, 32bit register */
#define SLOTMOD_MASK 0x03000000 /* 25:24 */
#define XMTSP_MASK 0x300 /* 17:16 */
#define XMTSP_128 0x200
#define XMTSP_64 0x100
#define CRTL1_DEFAULT 0x00000017
/* CTRL2 0x70, 32bit register */
#define FS_MASK 0x00070000 /* 18:16 */
#define FMDC_MASK 0x00000300 /* 9:8 */
#define XPHYRST B7_MASK
#define XPHYANE B6_MASK
#define XPHYFD B5_MASK
#define XPHYSP B3_MASK /* 4:3 */
#define APDW_MASK 0x00000007 /* 2:0 */
/* RCV_RING_CFG 0x78, 16bit register */
#define RCV_DROP3 B11_MASK
#define RCV_DROP2 B10_MASK
#define RCV_DROP1 B9_MASK
#define RCV_DROP0 B8_MASK
#define RCV_RING_DEFAULT 0x0030 /* 5:4 */
#define RCV_RING3_EN B3_MASK
#define RCV_RING2_EN B2_MASK
#define RCV_RING1_EN B1_MASK
#define RCV_RING0_EN B0_MASK
typedef enum {
INTR = (1 << 31),
PCSINT = (1 << 28),
LCINT = (1 << 27),
APINT5 = (1 << 26),
APINT4 = (1 << 25),
APINT3 = (1 << 24),
TINT_SUM = (1 << 23),
APINT2 = (1 << 22),
APINT1 = (1 << 21),
APINT0 = (1 << 20),
MIIPDTINT = (1 << 19),
MCCINT = (1 << 17),
MREINT = (1 << 16),
RINT_SUM = (1 << 15),
SPNDINT = (1 << 14),
MPINT = (1 << 13),
SINT = (1 << 12),
TINT3 = (1 << 11),
TINT2 = (1 << 10),
TINT1 = (1 << 9),
TINT0 = (1 << 8),
UINT = (1 << 7),
STINT = (1 << 4),
RINT0 = (1 << 0),
}INT0_BITS;
typedef enum {
VAL3 = (1 << 31), /* VAL bit for byte 3 */
VAL2 = (1 << 23), /* VAL bit for byte 2 */
VAL1 = (1 << 15), /* VAL bit for byte 1 */
VAL0 = (1 << 7), /* VAL bit for byte 0 */
}VAL_BITS;
typedef enum {
/* VAL3 */
LCINTEN = (1 << 27),
APINT5EN = (1 << 26),
APINT4EN = (1 << 25),
APINT3EN = (1 << 24),
/* VAL2 */
APINT2EN = (1 << 22),
APINT1EN = (1 << 21),
APINT0EN = (1 << 20),
MIIPDTINTEN = (1 << 19),
MCCIINTEN = (1 << 18),
MCCINTEN = (1 << 17),
MREINTEN = (1 << 16),
/* VAL1 */
SPNDINTEN = (1 << 14),
MPINTEN = (1 << 13),
TINTEN3 = (1 << 11),
SINTEN = (1 << 12),
TINTEN2 = (1 << 10),
TINTEN1 = (1 << 9),
TINTEN0 = (1 << 8),
/* VAL0 */
STINTEN = (1 << 4),
RINTEN0 = (1 << 0),
INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
}INTEN0_BITS;
typedef enum {
/* VAL2 */
RDMD0 = (1 << 16),
/* VAL1 */
TDMD3 = (1 << 11),
TDMD2 = (1 << 10),
TDMD1 = (1 << 9),
TDMD0 = (1 << 8),
/* VAL0 */
UINTCMD = (1 << 6),
RX_FAST_SPND = (1 << 5),
TX_FAST_SPND = (1 << 4),
RX_SPND = (1 << 3),
TX_SPND = (1 << 2),
INTREN = (1 << 1),
RUN = (1 << 0),
CMD0_CLEAR = 0x000F0F7F, /* Command style register */
}CMD0_BITS;
typedef enum {
/* VAL3 */
CONDUIT_MODE = (1 << 29),
/* VAL2 */
RPA = (1 << 19),
DRCVPA = (1 << 18),
DRCVBC = (1 << 17),
PROM = (1 << 16),
/* VAL1 */
ASTRP_RCV = (1 << 13),
RCV_DROP0 = (1 << 12),
EMBA = (1 << 11),
DXMT2PD = (1 << 10),
LTINTEN = (1 << 9),
DXMTFCS = (1 << 8),
/* VAL0 */
APAD_XMT = (1 << 6),
DRTY = (1 << 5),
INLOOP = (1 << 4),
EXLOOP = (1 << 3),
REX_RTRY = (1 << 2),
REX_UFLO = (1 << 1),
REX_LCOL = (1 << 0),
CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
}CMD2_BITS;
typedef enum {
/* VAL3 */
ASF_INIT_DONE_ALIAS = (1 << 29),
/* VAL2 */
JUMBO = (1 << 21),
VSIZE = (1 << 20),
VLONLY = (1 << 19),
VL_TAG_DEL = (1 << 18),
/* VAL1 */
EN_PMGR = (1 << 14),
INTLEVEL = (1 << 13),
FORCE_FULL_DUPLEX = (1 << 12),
FORCE_LINK_STATUS = (1 << 11),
APEP = (1 << 10),
MPPLBA = (1 << 9),
/* VAL0 */
RESET_PHY_PULSE = (1 << 2),
RESET_PHY = (1 << 1),
PHY_RST_POL = (1 << 0),
}CMD3_BITS;
typedef enum {
/* VAL0 */
PMAT_SAVE_MATCH = (1 << 4),
PMAT_MODE = (1 << 3),
MPEN_SW = (1 << 1),
LCMODE_SW = (1 << 0),
CMD7_CLEAR = 0x0000001B /* Command style register */
}CMD7_BITS;
typedef enum {
RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */
XMTSP_128 = (1 << 9), /* 9 */
XMTSP_64 = (1 << 8),
CACHE_ALIGN = (1 << 4),
BURST_LIMIT_MASK = (0xF << 0 ),
CTRL1_DEFAULT = 0x00010111,
}CTRL1_BITS;
typedef enum {
FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */
XPHYRST = (1 << 7),
XPHYANE = (1 << 6),
XPHYFD = (1 << 5),
XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */
APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
}CTRL2_BITS;
/* XMT_RING_LIMIT 0x7C, 32bit register */
#define XMT_RING2_LIMIT 0x00FF0000 /* 23:16 */
#define XMT_RING1_LIMIT 0x0000FF00 /* 15:8 */
#define XMT_RING0_LIMIT 0x000000FF /* 7:0 */
typedef enum {
XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */
XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */
XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */
}XMT_RING_LIMIT_BITS;
typedef enum {
/* AUTOPOLL0 0x88, 16bit register */
#define AP_REG0_EN B15_MASK
#define AP_REG0_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PHY0_ADDR_MASK 0x001F /* 4:0 */
AP_REG0_EN = (1 << 15),
AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL0_BITS;
/* AUTOPOLL1 0x8A, 16bit register */
#define AP_REG1_EN B15_MASK
#define AP_REG1_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PRE_SUP1 B6_MASK
#define AP_PHY1_DFLT B5_MASK
#define AP_PHY1_ADDR_MASK 0x001F /* 4:0 */
/* AUTOPOLL2 0x8C, 16bit register */
#define AP_REG2_EN B15_MASK
#define AP_REG2_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PRE_SUP2 B6_MASK
#define AP_PHY2_DFLT B5_MASK
#define AP_PHY2_ADDR_MASK 0x001F /* 4:0 */
/* AUTOPOLL3 0x8E, 16bit register */
#define AP_REG3_EN B15_MASK
#define AP_REG3_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PRE_SUP3 B6_MASK
#define AP_PHY3_DFLT B5_MASK
#define AP_PHY3_ADDR_MASK 0x001F /* 4:0 */
/* AUTOPOLL4 0x90, 16bit register */
#define AP_REG4_EN B15_MASK
#define AP_REG4_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PRE_SUP4 B6_MASK
#define AP_PHY4_DFLT B5_MASK
#define AP_PHY4_ADDR_MASK 0x001F /* 4:0 */
/* AUTOPOLL5 0x92, 16bit register */
#define AP_REG5_EN B15_MASK
#define AP_REG5_ADDR_MASK 0x1F00 /* 12:8 */
#define AP_PRE_SUP5 B6_MASK
#define AP_PHY5_DFLT B5_MASK
#define AP_PHY5_ADDR_MASK 0x001F /* 4:0 */
typedef enum {
AP_REG1_EN = (1 << 15),
AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PRE_SUP1 = (1 << 6),
AP_PHY1_DFLT = (1 << 5),
AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL1_BITS;
typedef enum {
AP_REG2_EN = (1 << 15),
AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PRE_SUP2 = (1 << 6),
AP_PHY2_DFLT = (1 << 5),
AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL2_BITS;
typedef enum {
AP_REG3_EN = (1 << 15),
AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PRE_SUP3 = (1 << 6),
AP_PHY3_DFLT = (1 << 5),
AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL3_BITS;
typedef enum {
AP_REG4_EN = (1 << 15),
AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PRE_SUP4 = (1 << 6),
AP_PHY4_DFLT = (1 << 5),
AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL4_BITS;
typedef enum {
AP_REG5_EN = (1 << 15),
AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
AP_PRE_SUP5 = (1 << 6),
AP_PHY5_DFLT = (1 << 5),
AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
}AUTOPOLL5_BITS;
/* AP_VALUE 0x98, 32bit ragister */
#define AP_VAL_ACTIVE B31_MASK
#define AP_VAL_RD_CMD B29_MASK
#define AP_ADDR 0x00070000 /* 18:16 */
#define AP_VAL 0x0000FFFF /* 15:0 */
/* PCS_ANEG 0x9C, 32bit register */
#define SYNC_LOST B10_MASK
#define IMATCH B9_MASK
#define CMATCH B8_MASK
#define PCS_AN_IDLE B1_MASK
#define PCS_AN_CFG B0_MASK
/* DLY_INT_A 0xA8, 32bit register */
#define DLY_INT_A_R3 B31_MASK
#define DLY_INT_A_R2 B30_MASK
#define DLY_INT_A_R1 B29_MASK
#define DLY_INT_A_R0 B28_MASK
#define DLY_INT_A_T3 B27_MASK
#define DLY_INT_A_T2 B26_MASK
#define DLY_INT_A_T1 B25_MASK
#define DLY_INT_A_T0 B24_MASK
#define EVENT_COUNT_A 0x00FF0000 /* 20:16 */
#define MAX_DELAY_TIME_A 0x000007FF /* 10:0 */
/* DLY_INT_B 0xAC, 32bit register */
#define DLY_INT_B_R3 B31_MASK
#define DLY_INT_B_R2 B30_MASK
#define DLY_INT_B_R1 B29_MASK
#define DLY_INT_B_R0 B28_MASK
#define DLY_INT_B_T3 B27_MASK
#define DLY_INT_B_T2 B26_MASK
#define DLY_INT_B_T1 B25_MASK
#define DLY_INT_B_T0 B24_MASK
#define EVENT_COUNT_B 0x00FF0000 /* 20:16 */
#define MAX_DELAY_TIME_B 0x000007FF /* 10:0 */
/* DFC_THRESH2 0xC0, 16bit register */
#define DFC_THRESH2_HIGH 0xFF00 /* 15:8 */
#define DFC_THRESH2_LOW 0x00FF /* 7:0 */
/* DFC_THRESH3 0xC2, 16bit register */
#define DFC_THRESH3_HIGH 0xFF00 /* 15:8 */
#define DFC_THRESH3_LOW 0x00FF /* 7:0 */
/* DFC_THRESH0 0xC4, 16bit register */
#define DFC_THRESH0_HIGH 0xFF00 /* 15:8 */
#define DFC_THRESH0_LOW 0x00FF /* 7:0 */
/* DFC_THRESH1 0xC6, 16bit register */
#define DFC_THRESH1_HIGH 0xFF00 /* 15:8 */
#define DFC_THRESH1_LOW 0x00FF /* 7:0 */
typedef enum {
AP_VAL_ACTIVE = (1 << 31),
AP_VAL_RD_CMD = ( 1 << 29),
AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
(0xF << 12), /* 15:0 */
}AP_VALUE_BITS;
typedef enum {
DLY_INT_A_R3 = (1 << 31),
DLY_INT_A_R2 = (1 << 30),
DLY_INT_A_R1 = (1 << 29),
DLY_INT_A_R0 = (1 << 28),
DLY_INT_A_T3 = (1 << 27),
DLY_INT_A_T2 = (1 << 26),
DLY_INT_A_T1 = (1 << 25),
DLY_INT_A_T0 = ( 1 << 24),
EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */
MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
(1 << 9) | (1 << 10), /* 10:0 */
}DLY_INT_A_BITS;
typedef enum {
DLY_INT_B_R3 = (1 << 31),
DLY_INT_B_R2 = (1 << 30),
DLY_INT_B_R1 = (1 << 29),
DLY_INT_B_R0 = (1 << 28),
DLY_INT_B_T3 = (1 << 27),
DLY_INT_B_T2 = (1 << 26),
DLY_INT_B_T1 = (1 << 25),
DLY_INT_B_T0 = ( 1 << 24),
EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
(1 << 9) | (1 << 10), /* 10:0 */
}DLY_INT_B_BITS;
/* FLOW_CONTROL 0xC8, 32bit register */
#define PAUSE_LEN_CHG B30_MASK
#define FFC_EN B28_MASK
#define DFC_RING3_EN B27_MASK
#define DFC_RING2_EN B26_MASK
#define DFC_RING1_EN B25_MASK
#define DFC_RING0_EN B24_MASK
#define FIXP_CONGEST B21_MASK
#define FPA B20_MASK
#define NPA B19_MASK
#define FIXP B18_MASK
#define FCPEN B17_MASK
#define FCCMD B16_MASK
#define PAUSE_LEN 0x0000FFFF /* 15:0 */
/* FFC THRESH 0xCC, 32bit register */
#define FFC_HIGH 0xFFFF0000 /* 31:16 */
#define FFC_LOW 0x0000FFFF /* 15:0 */
typedef enum {
PAUSE_LEN_CHG = (1 << 30),
FTPE = (1 << 22),
FRPE = (1 << 21),
NAPA = (1 << 20),
NPA = (1 << 19),
FIXP = ( 1 << 18),
FCCMD = ( 1 << 16),
PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */
}FLOW_CONTROL_BITS;
/* PHY_ ACCESS 0xD0, 32bit register */
#define PHY_CMD_ACTIVE B31_MASK
#define PHY_WR_CMD B30_MASK
#define PHY_RD_CMD B29_MASK
#define PHY_RD_ERR B28_MASK
#define PHY_PRE_SUP B27_MASK
#define PHY_ADDR 0x03E00000 /* 25:21 */
#define PHY_REG_ADDR 0x001F0000 /* 20:16 */
#define PHY_DATA 0x0000FFFF /* 15:0 */
/* LED0..3 0xE0..0xE6, 16bit register */
#define LEDOUT B15_MASK
#define LEDPOL B14_MASK
#define LEDDIS B13_MASK
#define LEDSTRETCH B12_MASK
#define LED1000 B8_MASK
#define LED100 B7_MASK
#define LEDMP B6_MASK
#define LEDFD B5_MASK
#define LEDLINK B4_MASK
#define LEDRCVMAT B3_MASK
#define LEDXMT B2_MASK
#define LEDRCV B1_MASK
#define LEDCOLOUT B0_MASK
/* EEPROM_ACC 0x17C, 16bit register */
#define PVALID B15_MASK
#define PREAD B14_MASK
#define EEDET B13_MASK
#define EEN B4_MASK
#define ECS B2_MASK
#define EESK B1_MASK
#define edi_edo b0_MASK
typedef enum {
PHY_CMD_ACTIVE = (1 << 31),
PHY_WR_CMD = (1 << 30),
PHY_RD_CMD = (1 << 29),
PHY_RD_ERR = (1 << 28),
PHY_PRE_SUP = (1 << 27),
PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|
(1 << 24) |(1 << 25),/* 25:21 */
PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */
PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
(0xF << 12),/* 15:0 */
}PHY_ACCESS_BITS;
/* PMAT0 0x190, 32bit register */
#define PMR_ACTIVE B31_MASK
#define PMR_WR_CMD B30_MASK
#define PMR_RD_CMD B29_MASK
#define PMR_BANK B28_MASK
#define PMR_ADDR 0x007F0000 /* 22:16 */
#define PMR_B4 0x000000FF /* 15:0 */
typedef enum {
PMR_ACTIVE = (1 << 31),
PMR_WR_CMD = (1 << 30),
PMR_RD_CMD = (1 << 29),
PMR_BANK = (1 <<28),
PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
(1 << 22),/* 22:16 */
PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */
}PMAT0_BITS;
/* PMAT1 0x194, 32bit register */
#define PMR_B3 0xFF000000 /* 31:24 */
#define PMR_B2 0x00FF0000 /* 23:16 */
#define PMR_B1 0x0000FF00 /* 15:8 */
#define PMR_B0 0x000000FF /* 7:0 */
typedef enum {
PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */
PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */
PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */
PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
}PMAT1_BITS;
/************************************************************************/
/* */
......@@ -615,7 +566,7 @@ eg., if the value 10011010b is written into the least significant byte of a comm
#define PCI_VENDOR_ID_AMD 0x1022
#define PCI_DEVICE_ID_AMD8111E_7462 0x7462
#define MAX_UNITS 16 /* Maximum number of devices possible */
#define MAX_UNITS 8 /* Maximum number of devices possible */
#define NUM_TX_BUFFERS 32 /* Number of transmit buffers */
#define NUM_RX_BUFFERS 32 /* Number of receive buffers */
......@@ -637,45 +588,73 @@ eg., if the value 10011010b is written into the least significant byte of a comm
#define MIN_PKT_LEN 60
#define ETH_ADDR_LEN 6
#define AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */
#define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */
#define DELAY_TIMER_CONV 50 /* msec to 10 usec conversion.
Only 500 usec resolution */
#define OPTION_VLAN_ENABLE 0x0001
#define OPTION_JUMBO_ENABLE 0x0002
#define OPTION_MULTICAST_ENABLE 0x0004
#define OPTION_WOL_ENABLE 0x0008
#define OPTION_WAKE_MAGIC_ENABLE 0x0010
#define OPTION_WAKE_PHY_ENABLE 0x0020
#define OPTION_INTR_COAL_ENABLE 0x0040
#define OPTION_DYN_IPG_ENABLE 0x0080
#define PHY_REG_ADDR_MASK 0x1f
/* ipg parameters */
#define DEFAULT_IPG 0x60
#define IFS1_DELTA 36
#define IPG_CONVERGE_TIME 0.5
#define IPG_STABLE_TIME 5
#define MIN_IPG 96
#define MAX_IPG 255
#define IPG_STEP 16
#define CSTATE 1
#define SSTATE 2
/* Assume contoller gets data 10 times the maximum processing time */
#define REPEAT_CNT 10;
/* amd8111e decriptor flag definitions */
typedef enum {
OWN_BIT = (1 << 15),
ADD_FCS_BIT = (1 << 13),
LTINT_BIT = (1 << 12),
STP_BIT = (1 << 9),
ENP_BIT = (1 << 8),
KILL_BIT = (1 << 6),
TCC_VLAN_INSERT = (1 << 1),
TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
}TX_FLAG_BITS;
typedef enum {
ERR_BIT = (1 << 14),
FRAM_BIT = (1 << 13),
OFLO_BIT = (1 << 12),
CRC_BIT = (1 << 11),
PAM_BIT = (1 << 6),
LAFM_BIT = (1 << 5),
BAM_BIT = (1 << 4),
TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */
TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */
}RX_FLAG_BITS;
#define OWN_BIT B15_MASK
#define ADD_FCS_BIT B13_MASK
#define LTINT_BIT B12_MASK
#define STP_BIT B9_MASK
#define ENP_BIT B8_MASK
#define KILL_BIT B6_MASK
#define TCC_MASK 0x0003
#define TCC_VLAN_INSERT B1_MASK
#define TCC_VLAN_REPLACE 0x0003
#define RESET_RX_FLAGS 0x0000
#define ERR_BIT B14_MASK
#define FRAM_BIT B13_MASK
#define OFLO_BIT B12_MASK
#define CRC_BIT B11_MASK
#define PAM_BIT B6_MASK
#define LAFM_BIT B5_MASK
#define BAM_BIT B4_MASK
#define TT_MASK 0x000c
#define TT_VLAN_TAGGED 0x000c
#define TT_PRTY_TAGGED 0x0008
#define TCC_MASK 0x0003
/* driver ioctl parameters */
#define PHY_ID 0x01 /* currently it is fixed */
#define AMD8111E_REG_DUMP_LEN 4096 /* Memory mapped register length */
#define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
/* crc generator constants */
#define CRC32 0xedb88320
#define INITCRC 0xFFFFFFFF
/* amd8111e desriptor format */
......@@ -683,7 +662,7 @@ struct amd8111e_tx_dr{
u16 buff_count; /* Size of the buffer pointed by this descriptor */
u16 tx_dr_offset2;
u16 tx_flags;
u16 tag_ctrl_info;
......@@ -704,7 +683,7 @@ struct amd8111e_rx_dr{
u16 buff_count; /* Len of the buffer pointed by descriptor. */
u16 rx_dr_offset10;
u16 rx_flags;
u32 buff_phy_addr;
......@@ -719,10 +698,58 @@ struct amd8111e_link_config{
u16 speed;
u8 duplex;
u8 autoneg;
u16 orig_speed;
u8 orig_duplex;
u8 reserved; /* 32bit alignment */
};
enum coal_type{
NO_COALESCE,
LOW_COALESCE,
MEDIUM_COALESCE,
HIGH_COALESCE,
};
enum coal_mode{
RX_INTR_COAL,
TX_INTR_COAL,
DISABLE_COAL,
ENABLE_COAL,
};
#define MAX_TIMEOUT 40
#define MAX_EVENT_COUNT 31
struct amd8111e_coalesce_conf{
unsigned int rx_timeout;
unsigned int rx_event_count;
unsigned long rx_packets;
unsigned long rx_prev_packets;
unsigned long rx_bytes;
unsigned long rx_prev_bytes;
unsigned int rx_coal_type;
unsigned int tx_timeout;
unsigned int tx_event_count;
unsigned long tx_packets;
unsigned long tx_prev_packets;
unsigned long tx_bytes;
unsigned long tx_prev_bytes;
unsigned int tx_coal_type;
};
struct ipg_info{
unsigned int ipg_state;
unsigned int ipg;
unsigned int current_ipg;
unsigned int col_cnt;
unsigned int diff_col_cnt;
unsigned int timer_tick;
unsigned int prev_ipg;
struct timer_list ipg_timer;
};
struct amd8111e_priv{
struct amd8111e_tx_dr* tx_ring;
......@@ -742,45 +769,54 @@ struct amd8111e_priv{
void * mmio;
spinlock_t lock; /* Guard lock */
unsigned long rx_idx, tx_idx; /* The next free ring entry */
unsigned long tx_complete_idx;
unsigned long rx_idx, tx_idx; /* The next free ring entry */
unsigned long tx_complete_idx;
unsigned long tx_ring_complete_idx;
unsigned long tx_ring_idx;
int rx_buff_len; /* Buffer length of rx buffers */
unsigned int rx_buff_len; /* Buffer length of rx buffers */
int options; /* Options enabled/disabled for the device */
unsigned long ext_phy_option;
struct amd8111e_link_config link_config;
int pm_cap;
u32 pm_state[12];
struct net_device *next;
int mii;
struct mii_if_info mii_if;
#if AMD8111E_VLAN_TAG_USED
struct vlan_group *vlgrp;
#endif
char opened;
struct net_device_stats stats;
struct net_device_stats prev_stats;
struct dev_mc_list* mc_list;
struct amd8111e_coalesce_conf coal_conf;
struct ipg_info ipg_data;
};
#define AMD8111E_READ_REG64(_memMapBase, _offset, _pUlData) \
*(u32*)(_pUlData) = readl(_memMapBase + (_offset)); \
*((u32*)(_pUlData))+1) = readl(_memMapBase + ((_offset)+4))
#define AMD8111E_WRITE_REG64(_memMapBase, _offset, _pUlData) \
writel(*(u32*)(_pUlData), _memMapBase + (_offset)); \
writel(*(u32*)((u8*)(_pUlData)+4), _memMapBase + ((_offset)+4)) \
/* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
BUG? */
#define amd8111e_writeq(_UlData,_memMap) \
writel(*(u32*)(&_UlData), _memMap); \
writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
/* maps the external speed options to internal value */
static unsigned char speed_duplex_mapping[] = {
typedef enum {
SPEED_AUTONEG,
SPEED10_HALF,
SPEED10_FULL,
SPEED100_HALF,
SPEED100_FULL,
}EXT_PHY_OPTION;
XPHYANE, /* Auto-negotiation, speed_duplex option 0 */
0, /* 10M Half, speed_duplex option 1 */
XPHYFD, /* 10M Full, speed_duplex option 2 */
XPHYSP, /* 100M Half, speed_duplex option 3 */
XPHYFD | XPHYSP /* 100M Full, speed_duplex option 4 */
};
static int card_idx;
static int speed_duplex[MAX_UNITS] = { 0, };
static int coalesce[MAX_UNITS] = {1,1,1,1,1,1,1,1};
static int dynamic_ipg[MAX_UNITS] = {0,0,0,0,0,0,0,0};
static unsigned int chip_version;
#endif /* _AMD8111E_H */
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