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Commit 741deade authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu: simplify Raven, Raven2, and Picasso handling 

Treat them all as Raven rather than adding a new picasso
asic type.  This simplifies a lot of code and also handles the
case of rv2 chips with the 0x15d8 pci id.  It also fixes dmcu
fw handling for picasso.
Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 23ecdc61
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Showing with 60 additions and 113 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View file @ 741deade
...@@ -91,7 +91,6 @@ static const char *amdgpu_asic_name[] = { ...@@ -91,7 +91,6 @@ static const char *amdgpu_asic_name[] = {
"VEGA12", "VEGA12",
"VEGA20", "VEGA20",
"RAVEN", "RAVEN",
"PICASSO",
"LAST", "LAST",
}; };
...@@ -1337,12 +1336,11 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) ...@@ -1337,12 +1336,11 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 8) if (adev->rev_id >= 8)
chip_name = "raven2"; chip_name = "raven2";
else if (adev->pdev->device == 0x15d8)
chip_name = "picasso";
else else
chip_name = "raven"; chip_name = "raven";
break; break;
case CHIP_PICASSO:
chip_name = "picasso";
break;
} }
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name); snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
...@@ -1468,8 +1466,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) ...@@ -1468,8 +1466,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO: if (adev->asic_type == CHIP_RAVEN)
if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO))
adev->family = AMDGPU_FAMILY_RV; adev->family = AMDGPU_FAMILY_RV;
else else
adev->family = AMDGPU_FAMILY_AI; adev->family = AMDGPU_FAMILY_AI;
...@@ -2183,7 +2180,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) ...@@ -2183,7 +2180,6 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
case CHIP_VEGA20: case CHIP_VEGA20:
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
#endif #endif
return amdgpu_dc != 0; return amdgpu_dc != 0;
#endif #endif
......
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
View file @ 741deade
...@@ -874,8 +874,7 @@ static const struct pci_device_id pciidlist[] = { ...@@ -874,8 +874,7 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
/* Raven */ /* Raven */
{0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
/* Picasso */ {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
{0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PICASSO|AMD_IS_APU},
{0, 0, 0} {0, 0, 0}
}; };
......
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View file @ 741deade
...@@ -56,7 +56,6 @@ static int psp_sw_init(void *handle) ...@@ -56,7 +56,6 @@ static int psp_sw_init(void *handle)
psp_v3_1_set_psp_funcs(psp); psp_v3_1_set_psp_funcs(psp);
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
psp_v10_0_set_psp_funcs(psp); psp_v10_0_set_psp_funcs(psp);
break; break;
case CHIP_VEGA20: case CHIP_VEGA20:
......
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
View file @ 741deade
...@@ -303,7 +303,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) ...@@ -303,7 +303,6 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
return AMDGPU_FW_LOAD_SMU; return AMDGPU_FW_LOAD_SMU;
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
if (!load_type) if (!load_type)
......
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View file @ 741deade
...@@ -65,12 +65,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) ...@@ -65,12 +65,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 8) if (adev->rev_id >= 8)
fw_name = FIRMWARE_RAVEN2; fw_name = FIRMWARE_RAVEN2;
else if (adev->pdev->device == 0x15d8)
fw_name = FIRMWARE_PICASSO;
else else
fw_name = FIRMWARE_RAVEN; fw_name = FIRMWARE_RAVEN;
break; break;
case CHIP_PICASSO:
fw_name = FIRMWARE_PICASSO;
break;
default: default:
return -EINVAL; return -EINVAL;
} }
......
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
View file @ 741deade
...@@ -2981,7 +2981,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ...@@ -2981,7 +2981,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
AMDGPU_VM_USE_CPU_FOR_COMPUTE); AMDGPU_VM_USE_CPU_FOR_COMPUTE);
if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) if (adev->asic_type == CHIP_RAVEN)
vm->pte_support_ats = true; vm->pte_support_ats = true;
} else { } else {
vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
...@@ -3073,7 +3073,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, ...@@ -3073,7 +3073,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
*/ */
int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid) int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
{ {
bool pte_support_ats = (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO); bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
int r; int r;
r = amdgpu_bo_reserve(vm->root.base.bo, true); r = amdgpu_bo_reserve(vm->root.base.bo, true);
......
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View file @ 741deade
...@@ -277,7 +277,6 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] = ...@@ -277,7 +277,6 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
#define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042
#define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
...@@ -329,14 +328,6 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -329,14 +328,6 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
golden_settings_gc_9_1_rv1, golden_settings_gc_9_1_rv1,
ARRAY_SIZE(golden_settings_gc_9_1_rv1)); ARRAY_SIZE(golden_settings_gc_9_1_rv1));
break; break;
case CHIP_PICASSO:
soc15_program_register_sequence(adev,
golden_settings_gc_9_1,
ARRAY_SIZE(golden_settings_gc_9_1));
soc15_program_register_sequence(adev,
golden_settings_gc_9_1_rv1,
ARRAY_SIZE(golden_settings_gc_9_1_rv1));
break;
default: default:
break; break;
} }
...@@ -617,12 +608,11 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev) ...@@ -617,12 +608,11 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 8) if (adev->rev_id >= 8)
chip_name = "raven2"; chip_name = "raven2";
else if (adev->pdev->device == 0x15d8)
chip_name = "picasso";
else else
chip_name = "raven"; chip_name = "raven";
break; break;
case CHIP_PICASSO:
chip_name = "picasso";
break;
default: default:
BUG(); BUG();
} }
...@@ -1076,7 +1066,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev) ...@@ -1076,7 +1066,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
} }
if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { if (adev->asic_type == CHIP_RAVEN) {
/* TODO: double check the cp_table_size for RV */ /* TODO: double check the cp_table_size for RV */
adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */ adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
...@@ -1328,14 +1318,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) ...@@ -1328,14 +1318,6 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
else else
gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN; gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
break; break;
case CHIP_PICASSO:
adev->gfx.config.max_hw_contexts = 8;
adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
gb_addr_config = PICASSO_GB_ADDR_CONFIG_GOLDEN;
break;
default: default:
BUG(); BUG();
break; break;
...@@ -1614,7 +1596,6 @@ static int gfx_v9_0_sw_init(void *handle) ...@@ -1614,7 +1596,6 @@ static int gfx_v9_0_sw_init(void *handle)
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_mec = 2;
break; break;
default: default:
...@@ -1776,7 +1757,7 @@ static int gfx_v9_0_sw_fini(void *handle) ...@@ -1776,7 +1757,7 @@ static int gfx_v9_0_sw_fini(void *handle)
amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
&adev->gfx.rlc.clear_state_gpu_addr, &adev->gfx.rlc.clear_state_gpu_addr,
(void **)&adev->gfx.rlc.cs_ptr); (void **)&adev->gfx.rlc.cs_ptr);
if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) { if (adev->asic_type == CHIP_RAVEN) {
amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
&adev->gfx.rlc.cp_table_gpu_addr, &adev->gfx.rlc.cp_table_gpu_addr,
(void **)&adev->gfx.rlc.cp_table_ptr); (void **)&adev->gfx.rlc.cp_table_ptr);
...@@ -2442,7 +2423,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) ...@@ -2442,7 +2423,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
return r; return r;
} }
if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) { if (adev->asic_type == CHIP_RAVEN) {
if (amdgpu_lbpw != 0) if (amdgpu_lbpw != 0)
gfx_v9_0_enable_lbpw(adev, true); gfx_v9_0_enable_lbpw(adev, true);
else else
...@@ -3846,7 +3827,6 @@ static int gfx_v9_0_set_powergating_state(void *handle, ...@@ -3846,7 +3827,6 @@ static int gfx_v9_0_set_powergating_state(void *handle,
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
if (!enable) { if (!enable) {
amdgpu_gfx_off_ctrl(adev, false); amdgpu_gfx_off_ctrl(adev, false);
cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
...@@ -3901,7 +3881,6 @@ static int gfx_v9_0_set_clockgating_state(void *handle, ...@@ -3901,7 +3881,6 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
gfx_v9_0_update_gfx_clock_gating(adev, gfx_v9_0_update_gfx_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
break; break;
...@@ -4911,7 +4890,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev) ...@@ -4911,7 +4890,6 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs; adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
break; break;
default: default:
......
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View file @ 741deade
...@@ -846,7 +846,6 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) ...@@ -846,7 +846,6 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.gart_size = 512ULL << 20; adev->gmc.gart_size = 512ULL << 20;
break; break;
case CHIP_RAVEN: /* DCE SG support */ case CHIP_RAVEN: /* DCE SG support */
case CHIP_PICASSO: /* DCE SG support */
adev->gmc.gart_size = 1024ULL << 20; adev->gmc.gart_size = 1024ULL << 20;
break; break;
} }
...@@ -935,7 +934,6 @@ static int gmc_v9_0_sw_init(void *handle) ...@@ -935,7 +934,6 @@ static int gmc_v9_0_sw_init(void *handle)
adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev); adev->gmc.vram_type = amdgpu_atomfirmware_get_vram_type(adev);
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
} else { } else {
...@@ -1062,7 +1060,6 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -1062,7 +1060,6 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA12: case CHIP_VEGA12:
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
soc15_program_register_sequence(adev, soc15_program_register_sequence(adev,
golden_settings_athub_1_0_0, golden_settings_athub_1_0_0,
ARRAY_SIZE(golden_settings_athub_1_0_0)); ARRAY_SIZE(golden_settings_athub_1_0_0));
...@@ -1097,7 +1094,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) ...@@ -1097,7 +1094,6 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
mmhub_v1_0_update_power_gating(adev, true); mmhub_v1_0_update_power_gating(adev, true);
break; break;
default: default:
......
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
View file @ 741deade
...@@ -412,7 +412,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad ...@@ -412,7 +412,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG);
if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) { if (adev->asic_type != CHIP_RAVEN) {
def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2);
} else } else
...@@ -428,7 +428,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad ...@@ -428,7 +428,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) if (adev->asic_type != CHIP_RAVEN)
data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
...@@ -445,7 +445,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad ...@@ -445,7 +445,7 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) if (adev->asic_type != CHIP_RAVEN)
data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
...@@ -458,13 +458,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad ...@@ -458,13 +458,13 @@ static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *ad
WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data);
if (def1 != data1) { if (def1 != data1) {
if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO) if (adev->asic_type != CHIP_RAVEN)
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
else else
WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1);
} }
if (adev->asic_type != CHIP_RAVEN && adev->asic_type != CHIP_PICASSO && def2 != data2) if (adev->asic_type != CHIP_RAVEN && def2 != data2)
WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2);
} }
...@@ -528,7 +528,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, ...@@ -528,7 +528,6 @@ int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev,
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
mmhub_v1_0_update_medium_grain_clock_gating(adev, mmhub_v1_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
athub_update_medium_grain_clock_gating(adev, athub_update_medium_grain_clock_gating(adev,
......
drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
View file @ 741deade
...@@ -121,12 +121,11 @@ static int psp_v10_0_init_microcode(struct psp_context *psp) ...@@ -121,12 +121,11 @@ static int psp_v10_0_init_microcode(struct psp_context *psp)
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 0x8) if (adev->rev_id >= 0x8)
chip_name = "raven2"; chip_name = "raven2";
else if (adev->pdev->device == 0x15d8)
chip_name = "picasso";
else else
chip_name = "raven"; chip_name = "raven";
break; break;
case CHIP_PICASSO:
chip_name = "picasso";
break;
default: BUG(); default: BUG();
} }
......
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
View file @ 741deade
...@@ -229,7 +229,6 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -229,7 +229,6 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
ARRAY_SIZE(golden_settings_sdma1_4_2)); ARRAY_SIZE(golden_settings_sdma1_4_2));
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
soc15_program_register_sequence(adev, soc15_program_register_sequence(adev,
golden_settings_sdma_4_1, golden_settings_sdma_4_1,
ARRAY_SIZE(golden_settings_sdma_4_1)); ARRAY_SIZE(golden_settings_sdma_4_1));
...@@ -283,12 +282,11 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) ...@@ -283,12 +282,11 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 8) if (adev->rev_id >= 8)
chip_name = "raven2"; chip_name = "raven2";
else if (adev->pdev->device == 0x15d8)
chip_name = "picasso";
else else
chip_name = "raven"; chip_name = "raven";
break; break;
case CHIP_PICASSO:
chip_name = "picasso";
break;
default: default:
BUG(); BUG();
} }
...@@ -869,7 +867,6 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev) ...@@ -869,7 +867,6 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_1_init_power_gating(adev); sdma_v4_1_init_power_gating(adev);
sdma_v4_1_update_power_gating(adev, true); sdma_v4_1_update_power_gating(adev, true);
break; break;
...@@ -1277,7 +1274,7 @@ static int sdma_v4_0_early_init(void *handle) ...@@ -1277,7 +1274,7 @@ static int sdma_v4_0_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) if (adev->asic_type == CHIP_RAVEN)
adev->sdma.num_instances = 1; adev->sdma.num_instances = 1;
else else
adev->sdma.num_instances = 2; adev->sdma.num_instances = 2;
...@@ -1620,7 +1617,6 @@ static int sdma_v4_0_set_clockgating_state(void *handle, ...@@ -1620,7 +1617,6 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_0_update_medium_grain_clock_gating(adev, sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
sdma_v4_0_update_medium_grain_light_sleep(adev, sdma_v4_0_update_medium_grain_light_sleep(adev,
...@@ -1639,7 +1635,6 @@ static int sdma_v4_0_set_powergating_state(void *handle, ...@@ -1639,7 +1635,6 @@ static int sdma_v4_0_set_powergating_state(void *handle,
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_1_update_power_gating(adev, sdma_v4_1_update_power_gating(adev,
state == AMD_PG_STATE_GATE ? true : false); state == AMD_PG_STATE_GATE ? true : false);
break; break;
......
drivers/gpu/drm/amd/amdgpu/soc15.c
View file @ 741deade
...@@ -491,7 +491,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) ...@@ -491,7 +491,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
vega10_reg_base_init(adev); vega10_reg_base_init(adev);
break; break;
case CHIP_VEGA20: case CHIP_VEGA20:
...@@ -546,7 +545,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) ...@@ -546,7 +545,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
...@@ -698,6 +696,13 @@ static int soc15_common_early_init(void *handle) ...@@ -698,6 +696,13 @@ static int soc15_common_early_init(void *handle)
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
if (adev->rev_id >= 0x8) if (adev->rev_id >= 0x8)
adev->external_rev_id = adev->rev_id + 0x81;
else if (adev->pdev->device == 0x15d8)
adev->external_rev_id = adev->rev_id + 0x41;
else
adev->external_rev_id = 0x1;
if (adev->rev_id >= 0x8) {
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CP_LS |
...@@ -713,65 +718,55 @@ static int soc15_common_early_init(void *handle) ...@@ -713,65 +718,55 @@ static int soc15_common_early_init(void *handle)
AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_VCN_MGCG; AMD_CG_SUPPORT_VCN_MGCG;
else
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
AMD_CG_SUPPORT_GFX_MGLS | } else if (adev->pdev->device == 0x15d8) {
AMD_CG_SUPPORT_GFX_RLC_LS | adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS | AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS | AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_DRM_MGCG |
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_ROM_MGCG | AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_LS;
AMD_CG_SUPPORT_VCN_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_RLC_SMU_HS;
if (adev->rev_id >= 0x8) adev->pg_flags = AMD_PG_SUPPORT_SDMA |
adev->external_rev_id = adev->rev_id + 0x81; AMD_PG_SUPPORT_MMHUB |
else AMD_PG_SUPPORT_VCN;
adev->external_rev_id = 0x1; } else {
break; adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
case CHIP_PICASSO: AMD_CG_SUPPORT_GFX_MGLS |
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS | AMD_CG_SUPPORT_GFX_RLC_LS |
AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_CP_LS |
AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGCG |
AMD_CG_SUPPORT_GFX_3D_CGLS | AMD_CG_SUPPORT_GFX_3D_CGLS |
AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGLS |
AMD_CG_SUPPORT_BIF_MGCG |
AMD_CG_SUPPORT_BIF_LS | AMD_CG_SUPPORT_BIF_LS |
AMD_CG_SUPPORT_HDP_MGCG |
AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_DRM_MGCG |
AMD_CG_SUPPORT_DRM_LS |
AMD_CG_SUPPORT_ROM_MGCG | AMD_CG_SUPPORT_ROM_MGCG |
AMD_CG_SUPPORT_MC_MGCG | AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_LS |
AMD_CG_SUPPORT_SDMA_MGCG | AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS; AMD_CG_SUPPORT_SDMA_LS |
AMD_CG_SUPPORT_VCN_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_SDMA | adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
AMD_PG_SUPPORT_MMHUB | }
AMD_PG_SUPPORT_VCN;
if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG | adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
AMD_PG_SUPPORT_CP | AMD_PG_SUPPORT_CP |
AMD_PG_SUPPORT_RLC_SMU_HS; AMD_PG_SUPPORT_RLC_SMU_HS;
adev->external_rev_id = adev->rev_id + 0x41;
break; break;
default: default:
/* FIXME: not supported yet */ /* FIXME: not supported yet */
...@@ -973,7 +968,6 @@ static int soc15_common_set_clockgating_state(void *handle, ...@@ -973,7 +968,6 @@ static int soc15_common_set_clockgating_state(void *handle,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
adev->nbio_funcs->update_medium_grain_clock_gating(adev, adev->nbio_funcs->update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
adev->nbio_funcs->update_medium_grain_light_sleep(adev, adev->nbio_funcs->update_medium_grain_light_sleep(adev,
......
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View file @ 741deade
...@@ -1215,8 +1215,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) ...@@ -1215,8 +1215,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
if (adev->asic_type == CHIP_VEGA10 || if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RAVEN)
adev->asic_type == CHIP_PICASSO)
client_id = SOC15_IH_CLIENTID_DCE; client_id = SOC15_IH_CLIENTID_DCE;
int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
...@@ -1635,7 +1634,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) ...@@ -1635,7 +1634,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
if (dcn10_register_irq_handlers(dm->adev)) { if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n"); DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail; goto fail;
...@@ -1862,7 +1860,6 @@ static int dm_early_init(void *handle) ...@@ -1862,7 +1860,6 @@ static int dm_early_init(void *handle)
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0) #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
adev->mode_info.num_crtc = 4; adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 4; adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4; adev->mode_info.num_dig = 4;
...@@ -2111,8 +2108,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, ...@@ -2111,8 +2108,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 || if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_RAVEN) {
adev->asic_type == CHIP_PICASSO) {
/* Fill GFX9 params */ /* Fill GFX9 params */
plane_state->tiling_info.gfx9.num_pipes = plane_state->tiling_info.gfx9.num_pipes =
adev->gfx.config.gb_addr_config_fields.num_pipes; adev->gfx.config.gb_addr_config_fields.num_pipes;
......
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
View file @ 741deade
...@@ -171,7 +171,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr) ...@@ -171,7 +171,6 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
case AMDGPU_FAMILY_RV: case AMDGPU_FAMILY_RV:
switch (hwmgr->chip_id) { switch (hwmgr->chip_id) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
hwmgr->od_enabled = false; hwmgr->od_enabled = false;
hwmgr->smumgr_funcs = &smu10_smu_funcs; hwmgr->smumgr_funcs = &smu10_smu_funcs;
smu10_init_function_pointers(hwmgr); smu10_init_function_pointers(hwmgr);
......
drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c
View file @ 741deade
...@@ -832,7 +832,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table( ...@@ -832,7 +832,7 @@ static const ATOM_PPLIB_POWERPLAYTABLE *get_powerplay_table(
uint16_t size; uint16_t size;
if (!table_addr) { if (!table_addr) {
if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) { if (hwmgr->chip_id == CHIP_RAVEN) {
table_addr = &soft_dummy_pp_table[0]; table_addr = &soft_dummy_pp_table[0];
hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
...@@ -1055,7 +1055,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, ...@@ -1055,7 +1055,7 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
hwmgr->platform_descriptor.maxOverdriveVDDC = 0; hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr->platform_descriptor.overdriveVDDCStep = 0; hwmgr->platform_descriptor.overdriveVDDCStep = 0;
if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) if (hwmgr->chip_id == CHIP_RAVEN)
return 0; return 0;
/* We assume here that fw_info is unchanged if this call fails.*/ /* We assume here that fw_info is unchanged if this call fails.*/
...@@ -1595,7 +1595,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) ...@@ -1595,7 +1595,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
int result; int result;
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table; const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table;
if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) if (hwmgr->chip_id == CHIP_RAVEN)
return 0; return 0;
hwmgr->need_pp_table_upload = true; hwmgr->need_pp_table_upload = true;
...@@ -1644,7 +1644,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr) ...@@ -1644,7 +1644,7 @@ static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr) static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
{ {
if (hwmgr->chip_id == CHIP_RAVEN || hwmgr->chip_id == CHIP_PICASSO) if (hwmgr->chip_id == CHIP_RAVEN)
return 0; return 0;
kfree(hwmgr->dyn_state.vddc_dependency_on_sclk); kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
......
include/drm/amd_asic_type.h
View file @ 741deade
...@@ -49,7 +49,6 @@ enum amd_asic_type { ...@@ -49,7 +49,6 @@ enum amd_asic_type {
CHIP_VEGA12, CHIP_VEGA12,
CHIP_VEGA20, CHIP_VEGA20,
CHIP_RAVEN, CHIP_RAVEN,
CHIP_PICASSO,
CHIP_LAST, CHIP_LAST,
}; };
......
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